CN111312724B - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN111312724B CN111312724B CN202010113079.4A CN202010113079A CN111312724B CN 111312724 B CN111312724 B CN 111312724B CN 202010113079 A CN202010113079 A CN 202010113079A CN 111312724 B CN111312724 B CN 111312724B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
The invention discloses an array substrate, a manufacturing method thereof and a display device, comprising a gate insulating layer, a gate line and a switch transistor which are positioned on a substrate; the gate insulating layer includes: a first subsection covering the gate line, and a second subsection covering the gate of the switching transistor; the first distance between the edge of the first subsection and the edge of the grid line is larger than the second distance between the edge of the second subsection and the edge of the grid electrode of the switch transistor, namely the GI tail of the grid insulating layer in the area of the switch transistor is unchanged, the GI tail of the grid line area is increased, and in the process that the follow-up interlayer dielectric layer continuously finishes twice climbing, the interlayer dielectric layer is not easy to wrinkle because the distance between the edge of the grid insulating layer and the edge of the grid line is large, and the follow-up source drain metal layer is not thinned or pointed because of the existence of wrinkles, so that the DGS defect can be well improved, meanwhile, the structure of the switch transistor is unchanged, no new defect is ensured, and the product yield is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display device.
Background
Active matrix electroluminescent display products (AMOLEDs) are currently moving towards high definition, large size and high refresh rates. This places higher demands on the transistor (TFT) performance of the AMOLED driver circuit. At present, a TFT structure for an AMOLED driving circuit mainly comprises an etching barrier layer structure (ESL), a Top Gate structure (Top Gate) and a back channel etching structure (BCE). The Gate and the source and drain of the Top Gate structure are not overlapped, so that the parasitic capacitance can be effectively reduced, the refreshing frequency is better, the size is smaller, the development requirement of the AMOLED can be met, and the Top Gate structure is a key direction for research and development.
However, in the prior art Top Gate structure, in order to reduce the effect of the short channel effect, it is generally required to ensure that the Gate insulating layer (GI) covers the Gate metal layer (Gate) including the Gate electrode and the Gate line, wherein a portion of the GI edge that is more than the Gate edge is called a Gate insulating layer Tail (GI Tail). When an interlayer dielectric layer (ILD) is formed subsequently, the ILD needs to finish two times of climbing (GI slope and Gate slope) continuously at the GI Tail position, and the phenomenon of wrinkling is easy to occur. During the process of forming the source drain metal layer (SD), wrinkles appear at the same positions, and the SD is thin due to poor covering capability and is easy to have tips in the wrinkle areas. If an electrostatic effect or an applied voltage occurs, electromigration (Migration) or metal (e.g., cu) diffusion is easily generated in the SD of the corrugated region, which may cause poor short circuit (DGS) between the Gate line and the data line in the Gate-SD overlapping region.
Disclosure of Invention
In view of this, embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device, so as to improve the DGS defect and increase the yield of the product.
Therefore, an array substrate provided in an embodiment of the present invention includes: the transistor comprises a substrate, a gate insulating layer, a gate line and a switching transistor, wherein the gate insulating layer, the gate line and the switching transistor are positioned on the substrate; wherein the content of the first and second substances,
the gate insulating layer includes: a first subsection covering the gate line, and a second subsection covering the gate of the switching transistor;
the edge of the first subsection has a first distance with the edge of the grid line, the edge of the second subsection has a second distance with the edge of the grid electrode of the switch transistor, and the first distance is larger than the second distance.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a drive transistor;
the gate insulating layer further includes: a third division covering the gate of the driving transistor;
and a third distance is formed between the edge of the third subsection and the edge of the grid electrode of the driving transistor, and the third distance is larger than the second distance.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: and the light shielding layer is positioned between the driving transistor and the substrate and covers the channel region of the driving transistor.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: and a data line crossing the gate line in an extending direction.
Based on the same inventive concept, the embodiment of the invention also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate base plate;
forming a gate insulating layer, a gate line and a switching transistor on the substrate;
wherein the gate insulating layer includes: a first subsection covering the gate line, and a second subsection covering the gate of the switching transistor;
the edge of the first subsection has a first distance with the edge of the grid line, the edge of the second subsection has a second distance with the edge of the grid electrode of the switch transistor, and the first distance is larger than the second distance.
In a possible implementation manner, in the manufacturing method provided in the embodiment of the present invention, the method further includes: forming a driving transistor;
the gate insulating layer further includes: a third subsection covering the gate of the drive transistor;
and a third pitch is formed between the edge of the third subsection and the edge of the grid electrode of the driving transistor, and the third pitch is larger than the second pitch.
Forming the gate insulating layer, the gate line, the gate electrode of the switching transistor, and the gate electrode of the driving transistor on the substrate, specifically including:
sequentially depositing an insulating material layer, a metal material layer and a photoresist layer on the substrate base plate;
exposing the photoresist layer by adopting a semi-exposure mask plate, removing the photoresist layer between the area where the grid line is to be manufactured, the area where the switch transistor is to be manufactured and the area where the drive transistor is to be manufactured, wherein the photoresist layer in the area where the grid line is to be manufactured, the area where the drive transistor is to be manufactured and the area where the grid electrode of the switch transistor is to be manufactured has a first thickness, and the photoresist layer in the area where the switch transistor is to be manufactured except for the area where the grid electrode of the switch transistor is formed has a second thickness smaller than the first thickness;
performing wet etching on the metal material layer to form the grid line and the grid electrode of the driving transistor;
ashing the photoresist layer to remove the photoresist layer with the second thickness;
performing wet etching on the metal material layer to form a gate electrode of the switching transistor, wherein the line widths of the gate line and the gate electrode of the driving transistor are narrowed;
and etching the insulating material layer to form the gate insulating layer which covers the first subsection of the gate line, the second subsection of the switch transistor and the third subsection of the drive transistor.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, before depositing an insulating material layer on the substrate base plate, the method further includes:
an active layer of the switching transistor and an active layer of the driving transistor are formed on the substrate base plate.
In a possible implementation manner, in the manufacturing method provided in an embodiment of the present invention, after etching the insulating material layer, the method further includes:
conducting a conductor treatment on an active layer of a switching transistor and an active layer of the driving transistor;
and stripping the photoresist layer.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, after the stripping the photoresist layer, the method further includes:
sequentially forming an interlayer dielectric layer and a source drain metal layer on the gate line, the gate of the switch transistor and the gate of the drive transistor;
wherein, the source leakage metal layer includes: a data line extending in a direction crossing the gate line, a source and a drain of the switching transistor, and a source and a drain of the driving transistor;
the source electrode and the drain electrode of the switch transistor are electrically connected with the active layer of the switch transistor through the first via hole of the interlayer dielectric layer;
and the source electrode and the drain electrode of the driving transistor are electrically connected with the active layer of the driving transistor through the second through hole of the interlayer dielectric layer.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including: the array substrate is provided.
The invention has the following beneficial effects:
the array substrate, the manufacturing method thereof and the display device provided by the embodiment of the invention comprise the following steps: the gate circuit comprises a substrate, a gate insulating layer, a gate line and a switching transistor, wherein the gate insulating layer, the gate line and the switching transistor are positioned on the substrate; wherein, the gate insulating layer includes: a first subsection covering the gate line, and a second subsection covering the gate of the switching transistor; a first distance is formed between the edge of the first subsection and the edge of the grid line, a second distance is formed between the edge of the second subsection and the edge of the grid electrode of the switch transistor, and the first distance is larger than the second distance. In the invention, the first distance between the edge of the first subsection and the edge of the grid line is larger than the second distance between the edge of the second subsection and the edge of the grid electrode of the switch transistor, which is equivalent to that the GI tail of the grid insulating layer in the area of the switch transistor is unchanged, the GI tail of the grid line area is increased, and in the process that the subsequent interlayer dielectric layer continuously finishes twice climbing, the interlayer dielectric layer is difficult to wrinkle because the distance between the edge of the grid insulating layer and the edge of the grid line is larger, and the subsequent source drain metal layer is not thinned or pointed because of the existence of wrinkles, so that the DGS (defectivity glass) can be well improved, meanwhile, the structure of the switch transistor is unchanged, no new defects are ensured, and the product yield is improved.
Drawings
Fig. 1 and fig. 2 are schematic structural diagrams of an array substrate according to an embodiment of the present invention;
fig. 3 to 5 are schematic structural diagrams of the array substrate provided in the embodiment of the invention in the manufacturing process.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. The thicknesses and shapes of the various film layers in the drawings are not to be considered true proportions, but are merely intended to illustrate the present invention. It should be apparent that the described embodiments are only some of the embodiments of the present invention, and not all of them. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. "inner", "outer", "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
An embodiment of the present invention provides an array substrate, as shown in fig. 1 and 2, including: a substrate base 101, a gate insulating layer 102 on the substrate base 101, a gate line 103, and a switching transistor 104; wherein the content of the first and second substances,
a gate insulating layer 102 comprising: a first subsection 1021 covering the gate line 103, and a second subsection 1022 covering the gate 1041 of the switching transistor;
a first distance T1 is provided between an edge of the first division 1021 and an edge of the gate line 103, a second distance T2 is provided between an edge of the second division 1022 and an edge of the gate 1041 of the switching transistor, and the first distance T1 is greater than the second distance T2.
In the array substrate provided by the embodiment of the present invention, a first distance T1 between an edge of the first division 1021 and an edge of the gate line 103 is greater than a second distance T2 between an edge of the second division 1022 and an edge of the gate 1041 of the switching transistor, which is equivalent to that the GI tail of the gate insulating layer 102 in the region of the switching transistor 104 is unchanged, the GI tail of the region of the gate line 103 is increased, and in the process that the subsequent interlayer dielectric layer continuously completes two times of climbing, because the distance between the edge of the gate insulating layer 102 and the edge of the gate line 103 is greater, the interlayer dielectric layer is not prone to wrinkle, and the subsequent source and drain metal layer is relatively smooth and does not become thinner or have tips due to the presence of wrinkles, so that the DGS defect can be well improved, meanwhile, the structure of the switching transistor 104 is not changed, no new defect is ensured, and the product yield is improved.
In the related art, a driving transistor 105 is usually further provided, and due to the requirement of stability, as shown in fig. 1, a light shielding layer 106 needs to be added between the driving transistor and the substrate 101, and the light shielding layer 106 covers a channel region of the driving transistor 105. However, at present, the light shielding layer 106 is generally formed by a metal film process, and a CVD deposition process and a DE conductor process in the metal film process may cause a certain interference to the active layer 1052 of the driving transistor, so that the characteristics of the driving transistor 105 and the switching transistor 104 are different, specifically, the characteristics of the driving transistor 105 are more negative than those of the switching transistor 104, and the uniformity of the transistor is poor.
Based on this, as shown in fig. 1 and fig. 2, the array substrate provided in the embodiment of the present invention further includes: a driving transistor 105;
the gate insulating layer 102, further including: a third section 1023 covering the gate 1051 of the driving transistor;
a third distance T3 is provided between an edge of the third section 1023 and an edge of the gate 1051 of the driving transistor, and the third distance T3 is greater than the second distance T2.
A third distance T3 between the edge of the third section 1023 and the edge of the gate 1051 of the driving transistor is greater than a second distance T2 between the edge of the second section 1022 and the edge of the gate 1041 of the switching transistor, which is equivalent to that the GI tail of the gate insulating layer 102 in the area where the switching transistor 104 is located is unchanged, the GI tail in the area where the driving transistor 105 is located is increased, the effective channel length of the driving transistor 105 is increased, the short channel effect of the driving transistor 105 is effectively improved, and the uniformity of the driving transistor 105 and the switching transistor 104 is improved. In specific implementation, the value of the third pitch T3 can be selectively and quantitatively adjusted by a Half-exposure Mask (Half-tone Mask).
Generally, the array substrate provided in the embodiment of the present invention further includes: and a data line extending in a direction crossing the gate line 103.
Because the first distance T1 between the edge of the first division 1021 and the edge of the gate line 103 is greater than the second distance T2 between the edge of the second division 1022 and the edge of the gate 1041 of the switching transistor, that is, the distance between the edge of the gate insulating layer 102 and the edge of the gate line 103 is relatively large, a wrinkle phenomenon is not easy to occur in the process of continuously finishing two times of climbing of a subsequent interlayer dielectric layer, a data line pattern in an overlapping area of the gate line 103 and a data line is relatively smooth and cannot become thin or have a tip due to the existence of the wrinkle, and thus, the poor DGS is well improved.
In addition, as shown in fig. 1, the array substrate according to the embodiment of the invention generally further includes a buffer layer 107 located between the light-shielding layer 106 and the active layers 1042 and 1052 of the switching transistor and the driving transistor.
Based on the same inventive concept, embodiments of the present invention provide a method for manufacturing an array substrate, and because a principle of the method for solving the problem is similar to a principle of the method for solving the problem of the array substrate, the implementation of the method for manufacturing the array substrate provided by embodiments of the present invention can refer to the implementation of the array substrate provided by embodiments of the present invention, and repeated details are not repeated.
Specifically, the method for manufacturing an array substrate provided by the embodiment of the invention comprises the following steps:
providing a substrate 101;
forming a gate insulating layer 102, a gate line 103, and a switching transistor 104 on a substrate 101, as shown in fig. 1;
the gate insulating layer 102 includes: a first subsection 1021 covering the gate line 103, and a second subsection 1022 covering the gate 1041 of the switching transistor;
a first distance T1 is provided between an edge of the first division 1021 and an edge of the gate line 103, a second distance T2 is provided between an edge of the second division 1022 and an edge of the gate 1041 of the switching transistor, and the first distance T1 is greater than the second distance T2.
Optionally, in the manufacturing method provided in the embodiment of the present invention, the method may further include: forming a driving transistor 105, as shown in fig. 1;
the gate insulating layer 102, further including: a third section 1023 covering the gate 1051 of the driving transistor;
a third distance T3 is provided between an edge of the third section 1023 and an edge of the gate 1051 of the driving transistor, and the third distance T3 is greater than the second distance T2.
Forming the gate insulating layer 102, the gate line 103, the gate electrode 1041 of the switching transistor, and the gate electrode 1051 of the driving transistor on the substrate 101 may be specifically implemented as follows:
sequentially depositing an insulating material layer 108, a metal material layer 109 and a photoresist layer 110 on the substrate base plate 101;
exposing the photoresist layer 110 by using a Half-exposure mask (Half-tone mask), removing the photoresist layer 110 between the region where the gate line 103 to be manufactured is located, the region where the switching transistor 104 to be manufactured is located, and the region where the driving transistor 105 to be manufactured is located, wherein the photoresist layer 110 in the region where the gate line 103 to be manufactured is located, the region where the driving transistor 105 to be manufactured is located, and the region where the gate 1041 of the switching transistor to be manufactured is located has a first thickness H1, and the photoresist layer 110 in the region where the switching transistor 104 to be manufactured is located, except the region where the gate 1041 of the switching transistor is formed, has a second thickness H2 smaller than the first thickness H1, as shown in fig. 3;
performing wet etching on the metal material layer 109 to form a gate line 103 and a gate electrode 1051 of the driving transistor;
performing ashing treatment on the photoresist layer 110 to remove the photoresist layer 110 with the second thickness H2, as shown in fig. 4;
performing wet etching on the metal material layer 109 to form a gate 1041 of the switching transistor, and simultaneously narrowing line widths of the gate line 103 and a gate 1051 of the driving transistor;
etching the insulating material layer 108 to form a gate insulating layer 102 including a first subsection 1021 covering the gate line 103, a second subsection 1042 covering the switching transistor 104, and a third subsection 1023 covering the driving transistor 105, as shown in fig. 5;
to this end, the metal material layer 109 for forming the gate line 103 and the gate electrode 1051 of the driving transistor is subjected to two wet etches, the gate electrode 1041 for forming the switching transistor is subjected to one wet etch, and during the second wet etch, the metal material layer 109 in the region where the gate line 103 is located and the gate electrode 1051 of the driving transistor is over-etched by the wet etch due to the isotropic characteristic of the wet etch, so as to form a larger CD Bias, such that a first distance T1 between an edge of the first partition 1021 and an edge of the gate line 103, and a third distance T3 between an edge of the third partition 1023 and an edge of the gate electrode 1051 of the driving transistor are both greater than a second distance T2 between an edge of the second partition 1022 and an edge of the gate electrode 1041 of the switching transistor.
Optionally, in the manufacturing method provided by the embodiment of the present invention, before depositing the insulating material layer on the substrate base plate, the following steps may be further performed:
an active layer 1042 of a switching transistor and an active layer 1052 of a driving transistor are formed over the substrate 101.
Optionally, in the manufacturing method provided in the embodiment of the present invention, after etching the insulating material layer 108, the following steps need to be further performed:
conducting a conductive process to the active layer 1042 of the switching transistor and the active layer 1052 of the driving transistor;
the photoresist layer 110 is stripped as shown in fig. 1.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, after the photoresist layer 110 is stripped, the following steps generally need to be performed:
sequentially forming an interlayer dielectric layer and a source-drain metal layer on the gate metal layer where the gate line 103, the gate electrode 1041 of the switching transistor and the gate electrode 1051 of the driving transistor are located;
wherein, source leakage metal level includes: a data line extending in a direction crossing the gate line, a source and a drain of the switching transistor, and a source and a drain of the driving transistor;
the source electrode and the drain electrode of the switch transistor are electrically connected with the active layer of the switch transistor through the first via hole of the interlayer dielectric layer;
and the source electrode and the drain electrode of the driving transistor are electrically connected with the active layer of the driving transistor through the second through hole of the interlayer dielectric layer.
It should be noted that, in the manufacturing method provided in the embodiment of the present invention, the patterning process related to forming each layer structure may include not only some or all of the processes of deposition, photoresist coating, mask masking, exposure, development, etching, and photoresist stripping, but also other processes, and specifically, a pattern to be patterned is formed in an actual manufacturing process, which is not limited herein. For example, a post-bake process may also be included after development and before etching. The deposition process may be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or a physical vapor deposition method, which is not limited herein; the etching may be dry etching or wet etching, and is not limited herein.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the array substrate provided in the embodiment of the present invention, where the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an intelligent watch, a fitness wrist strap, and a personal digital assistant. Other essential components of the display device should be understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention. In addition, because the principle of solving the problems of the display device is similar to that of solving the problems of the array substrate, the implementation of the display device can be referred to the embodiment of the array substrate, and repeated details are not repeated.
The array substrate, the manufacturing method thereof and the display device provided by the embodiment of the invention comprise the following steps: the transistor comprises a substrate, a grid insulating layer, a grid line and a switch transistor, wherein the grid insulating layer, the grid line and the switch transistor are positioned on the substrate; wherein, the gate insulating layer includes: a first subsection covering the gate line, and a second subsection covering the gate of the switching transistor; a first distance is formed between the edge of the first subsection and the edge of the grid line, a second distance is formed between the edge of the second subsection and the edge of the grid electrode of the switch transistor, and the first distance is larger than the second distance. In the invention, the first distance between the edge of the first subsection and the edge of the grid line is larger than the second distance between the edge of the second subsection and the edge of the grid electrode of the switch transistor, which is equivalent to that the GI tail of the grid insulating layer in the area of the switch transistor is unchanged, the GI tail of the grid line area is increased, and in the process that the subsequent interlayer dielectric layer continuously finishes twice climbing, the interlayer dielectric layer is difficult to wrinkle because the distance between the edge of the grid insulating layer and the edge of the grid line is larger, the subsequent source and drain metal layer is smoother and can not become thinner or have sharp ends because of the existence of wrinkles, thereby the DGS defect can be well improved, meanwhile, the structure of the switch transistor is unchanged, no new defect is ensured, and the product yield is improved. In addition, the size of a third distance between the edge of a third subsection contained in the gate insulating layer and the gate electrode edge of the driving transistor is selectively and quantitatively adjusted through the semi-exposure mask plate, so that the third distance is larger than a second distance between the edge of the second subsection and the gate electrode edge of the switching transistor, namely the GI tail of the area where the driving transistor is located is increased, the effective length of a channel of the driving transistor is increased, the short-channel effect of the driving transistor is obviously improved, and the uniformity of the driving transistor and the switching transistor is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. An array substrate, comprising: the transistor comprises a substrate, a grid insulating layer, a grid line, a switch transistor and a driving transistor, wherein the grid insulating layer, the grid line, the switch transistor and the driving transistor are positioned on the substrate; wherein the content of the first and second substances,
the gate insulating layer includes: a first subsection covering the gate line, a second subsection covering the gate of the switching transistor, and a third subsection covering the gate of the driving transistor;
a first distance is formed between the edge of the first subsection and the edge of the grid line, a second distance is formed between the edge of the second subsection and the edge of the grid electrode of the switch transistor, and the first distance is larger than the second distance; a third pitch is arranged between the edge of the third subsection and the edge of the grid electrode of the driving transistor, and the third pitch is larger than the second pitch; and the third distance is adjusted by a half-exposure mask plate.
2. The array substrate of claim 1, further comprising: and the light shielding layer is positioned between the driving transistor and the substrate and covers the channel region of the driving transistor.
3. The array substrate of any one of claims 1-2, further comprising: and a data line crossing the gate line in an extending direction.
4. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate base plate;
forming a gate insulating layer, a gate line, a switching transistor and a driving transistor on the substrate;
wherein the gate insulating layer includes: a first subsection covering the gate line, a second subsection covering the gate of the switching transistor, and a third subsection covering the gate of the driving transistor;
a first pitch is formed between the edge of the first subsection and the edge of the gate line, a second pitch is formed between the edge of the second subsection and the edge of the gate electrode of the switching transistor, and the first pitch is larger than the second pitch; and a third distance is formed between the edge of the third subsection and the edge of the grid electrode of the driving transistor, the third distance is larger than the second distance, and the third distance is adjusted through a half-exposure mask plate.
5. The method according to claim 4, wherein forming the gate insulating layer, the gate line, the gate electrode of the switching transistor, and the gate electrode of the driving transistor on the substrate includes:
sequentially depositing an insulating material layer, a metal material layer and a photoresist layer on the substrate base plate;
exposing the photoresist layer by using a semi-exposure mask plate, removing the photoresist layer between a region where the grid line is to be manufactured, a region where the switch transistor is to be manufactured and a region where the drive transistor is to be manufactured, wherein the photoresist layer in the region where the grid line is to be manufactured, the region where the drive transistor is to be manufactured and the region where the grid electrode of the switch transistor is to be manufactured has a first thickness, and the photoresist layer in the region where the switch transistor is to be manufactured except for the region where the grid electrode of the switch transistor is formed has a second thickness smaller than the first thickness;
performing wet etching on the metal material layer to form the grid line and the grid electrode of the driving transistor;
ashing the photoresist layer to remove the photoresist layer with the second thickness;
performing wet etching on the metal material layer to form a gate electrode of the switching transistor, and narrowing line widths of the gate line and the gate electrode of the driving transistor;
and etching the insulating material layer to form the gate insulating layer covering the first subsection of the gate line, the second subsection of the switch transistor and the third subsection of the drive transistor.
6. The method of manufacturing of claim 5, further comprising, prior to depositing a layer of insulating material on the substrate base plate:
an active layer of the switching transistor and an active layer of the driving transistor are formed on the substrate base plate.
7. The method of claim 6, further comprising, after etching the layer of insulating material:
conducting an active layer of a switching transistor and an active layer of the driving transistor;
and stripping the photoresist layer.
8. The method of claim 7, further comprising, after stripping the photoresist layer:
sequentially forming an interlayer dielectric layer and a source drain metal layer on the gate line, the gate of the switch transistor and the gate of the drive transistor;
wherein, the source leakage metal layer includes: a data line extending in a direction crossing the gate line, a source and a drain of the switching transistor, and a source and a drain of the driving transistor;
the source electrode and the drain electrode of the switch transistor are electrically connected with the active layer of the switch transistor through the first via hole of the interlayer dielectric layer;
and the source electrode and the drain electrode of the driving transistor are electrically connected with the active layer of the driving transistor through the second through hole of the interlayer dielectric layer.
9. A display device, comprising: an array substrate as claimed in any one of claims 1 to 3.
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| KR102561113B1 (en) * | 2015-08-13 | 2023-07-28 | 삼성디스플레이 주식회사 | Organic light emitting diode display device and manufacturing method thereof |
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