CN111312708A - Low-capacitance transient voltage suppressor and manufacturing method thereof - Google Patents

Low-capacitance transient voltage suppressor and manufacturing method thereof Download PDF

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CN111312708A
CN111312708A CN202010236372.XA CN202010236372A CN111312708A CN 111312708 A CN111312708 A CN 111312708A CN 202010236372 A CN202010236372 A CN 202010236372A CN 111312708 A CN111312708 A CN 111312708A
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layer
region
deep
substrate
shallow
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蒋骞苑
赵德益
赵志方
吕海凤
张啸
王允
李亚文
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Shanghai Wei'an Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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Abstract

The invention relates to a low-capacitance transient voltage suppressor and a manufacturing method thereof, wherein the low-capacitance transient voltage suppressor adopts a substrate silicon wafer, and an N + buried layer is added between a substrate and an epitaxy and is led out through a deep N +/shallow N + region or a P + buried layer is added between the substrate and the epitaxy and is led out through a deep P +/shallow P + region on the basis of a TVS device structure. Compared with the TVS device with the traditional low-capacitance structure, the TVS device with the low-capacitance structure has the advantages that the anti-surge and electrostatic discharge capabilities are greatly improved by increasing the current conducting area under the condition of not increasing the area of a silicon chip, the requirements of a high-speed signal transmission port are met, and the TVS device can be applied to equipment such as a network port, an RJ45, a wireless local area network and a notebook computer.

Description

Low-capacitance transient voltage suppressor and manufacturing method thereof
Technical Field
The invention belongs to the field of semiconductor protection devices, and particularly relates to a low-capacitance transient voltage suppressor applied to a signal port and a manufacturing method thereof.
Background
A Transient Voltage Suppressor (TVS) is a commonly used protection device, and has an extremely fast response speed and a relatively large surge discharge capability. When the transient high-energy surge or electrostatic shock is suffered by the TVS, the TVS can change the impedance value between two ends from high impedance to low impedance at a very high speed so as to discharge a transient large current, and simultaneously clamp the voltage at two ends of the TVS at a small value, so that a rear-stage circuit chip is protected from the shock of transient high-voltage surge pulse, and the TVS is an indispensable protection device.
When the transient voltage suppressor is applied to various signal transmission ports, on one hand, the transient voltage suppressor is required to have higher surge and electrostatic protection capabilities. On the other hand, it is required that its own parasitic capacitance is small, because when the capacitance is large, signal transmission is affected, data loss is caused, and the quality of signal transmission is seriously affected.
In order to improve the protection capability of the transient voltage suppressor, the surge and electrostatic capability is generally improved by increasing the device area to obtain a larger junction area. At the same time, however, the parasitic capacitance of the device will be increased significantly, which causes data loss during signal transmission, and cannot meet the requirement of high-speed signal port transmission.
Disclosure of Invention
In order to solve the above problems, the present invention aims to: the low-capacitance transient voltage suppressor has the advantages that the capacitance is maintained at the original small level, and the high surge and electrostatic protection capability is realized by optimizing a current conduction path so as to meet the performance requirement of a high-speed signal transmission port on the transient voltage suppressor.
Yet another object of the present invention is to: a method for manufacturing the low-capacitance transient voltage suppressor is provided.
The purpose of the invention is realized by the following scheme: a low capacitance transient voltage suppressor using an N + substrate silicon wafer, comprising:
the N + substrate layer is formed by growing a P-epitaxial layer on the front side of the N + substrate and a metal layer with the back side serving as a grounding end;
an N + buried layer is arranged in the upper surface of the P-epitaxial layer, deep N + regions are connected to the N + buried layer, and the P + regions between the deep N + regions are connected with the P-epitaxial layer;
a shallow N + layer is arranged on the upper surfaces of the deep N + region and the P + region;
and a front metal layer is arranged on the shallow N + layer and is used as an input end.
Based on the scheme, the resistivity of the N + substrate silicon wafer is 0.0005-0.01 omega cm.
On the basis of the scheme, a thin concentration buffer layer can be further added between the P-epitaxy layer and the N + substrate.
Preferably, the thickness of the P-epitaxial layer is 4-12 μm, and the resistivity is 20-200 Ω cm.
The element implanted by the N + buried layer is antimony or arsenic, and the implantation dosage is 1E 15-1E 16/cm2The implantation energy is 100 to 120KeV, and the implantation angle is 7 degrees.
The invention provides a transient voltage suppressor with better performance, which sequentially comprises: the N + substrate, the P-epitaxial layer, the N + buried layer, the P-epitaxial layer and the shallow N + region which form a P + region and a deep N + region, wherein the upper surface of the shallow N + region is provided with a front metal layer connected with the input end, the back surface of the N + substrate is provided with a back metal layer connected with the ground end, the N + buried layer is arranged in the upper surface of the P-epitaxial layer, and the deep N + region is arranged on the upper surface of the N + buried layer.
The invention also provides a manufacturing method of the low-capacitance transient voltage suppressor, which comprises the following steps:
step 1: firstly, selecting an N + type substrate silicon wafer, and then growing a P-epitaxial layer with the thickness of 4-12 mu m and the resistivity of 20-200 omega cm on the upper surface of the N + type substrate silicon wafer;
step 2: photoetching and ion implantation are carried out on the upper surface of the P-epitaxial layer through an N + buried layer, implantation of the N + buried layer is carried out on the partial surface of the P-epitaxial layer, and the P-epitaxial layer enters a high-temperature furnace tube to carry out thermal process propulsion;
and step 3: carrying out second epitaxial growth on the surface, and growing a P-type epitaxial layer with the thickness of 3-10 microns and the resistivity of 0.1-50 omega cm;
step (ii) of4: defining a deep N + well region on the surface of the P epitaxial layer by deep N + photoetching, and then carrying out deep N + ion implantation, wherein phosphorus is implanted into the deep N + ions, and the implantation dosage is 5E 15-1E 16/cm2The injection energy is 100K-1 MeV;
and 5: defining a P + region on the surface by P + photoetching, and then carrying out P + ion implantation, wherein boron is implanted into the P + region by ion implantation with the implantation dosage of 5E 15-1E 16/cm2The injection energy is 100K-1 MeV; the silicon wafer enters a furnace tube to be propelled at high temperature, so that a deep N + region is connected with an N + buried layer, and a P + region is connected with a P-epitaxy layer;
step 6: forming a shallow N + region on the surface of the deep N + region and the surface of the P + region by shallow N + region photoetching and ion implantation, wherein phosphorus or arsenic is implanted into the shallow N + region in an implantation dosage of 1E 15-1E 16/cm2Injecting energy of 60-100 KeV, and then performing an annealing process;
and 7: performing metal deposition on the surface of the shallow N + region to form a front metal layer with the thickness ranging from 2 to 6 microns as an input end;
and 8: and (3) carrying out blue film pasting protection on the front surface of the silicon wafer, then thinning the back surface of the silicon wafer to 80-150 microns through chemical mechanical grinding, then carrying out metal evaporation or deposition process on the back surface of the silicon wafer to form back surface metal which is used as a grounding end, and obtaining the low-capacitance transient voltage suppressor.
The back of the silicon chip is thinned, so that the substrate resistance can be further reduced, and the reduction of the on-resistance and the clamping voltage is facilitated.
In step 1, the temperature of the epitaxial process is not limited, and the epitaxial layer can be grown by a conventional high-temperature technology or a low-temperature technology. More preferably, a thin concentration buffer layer can be added between the P-epitaxy and the N + substrate.
The thermal process conditions of the furnace tube in the step 2 are that the temperature is 1100-1200 ℃, and the time is 80-120 minutes.
In step 4, the deep N + can be subjected to ion implantation with energy from large to small for multiple times to obtain better conduction characteristics.
In step 5, the P + region may be subjected to ion implantation with energy decreasing from large to small for multiple times to obtain better conduction characteristics.
In the step 5, the high-temperature propulsion condition is 1100-1150 ℃, the time range is 60-360 minutes, the deep N + region can be connected with the N + buried layer, and meanwhile, the P + region is connected with the P-epitaxy. The drive-in time is selected based on the epitaxial layer thickness.
In the step 6, annealing the annealing process by using a furnace tube, wherein the process conditions are 900-950 ℃ for 30-60 minutes; or a rapid thermal annealing (RTP) process is used, wherein the process conditions are 980-1100 ℃ and the time is 15-45 seconds. Both methods can activate the implanted impurities, eliminate implantation damage and prevent junction leakage.
In the step 7, aluminum or an aluminum-silicon compound can be used for metal deposition, or a three-layer structure consisting of titanium, titanium nitride and aluminum is used, wherein the thickness of titanium is 300-600 Å, the thickness of titanium nitride is 400-1000 Å, and the total metal is obtained.
Compared with the conventional TVS device with a low-capacity structure, the TVS device meets the requirement of a high-speed signal transmission port, can be applied to equipment such as a network port, RJ45, a wireless local area network, a notebook computer and the like, and has the following technical advantages:
(1) and innovating a device structure, and adding an N + buried layer between the substrate and the epitaxy, and leading out the N + buried layer through a deep N +/shallow N + region. Since the shallow N +, deep N +, N + buried layer and the P + region are all heavily doped, three junctions (shallow N +/P + junction, deep N +/P + junction, N + buried layer/P + junction) formed by the shallow N +, the deep N +, the N + buried layer and the P + region have lower reverse breakdown voltage. When the input end of the device is impacted by surge voltage or electrostatic discharge, the three junctions break down first, so that two junctions, namely a deep N +/P + junction and an N + buried layer/P + junction are added compared with the traditional TVS, the current conduction area is increased, and the capacity of resisting surge and electrostatic discharge is greatly improved.
(2) When the device encounters a larger surge or electrostatic discharge, another NP junction, consisting of a shallow N +/deep N +/P-epi, will also turn on conduction, since the P-epi has a lower doping concentration and therefore a slightly higher breakdown voltage. Namely, current flows into the P-epitaxial body below the N + buried layer/P-epitaxial junction through the N + buried layer/P-epitaxial junction, which is equivalent to increasing the current conducting area again and further improving the surge impact resistance and the electrostatic discharge resistance.
(3) When the current flows downwards continuously through the two points, the current passes through the forward diode consisting of the P-epitaxy/N + substrate, and the diode has a wide space charge region due to the small doping concentration of the P-epitaxy, and the junction area of the P-epitaxy/N + substrate is not increased, so that the capacitance of the diode is still small, and the capacitance of the whole device can be effectively reduced.
Drawings
Fig. 1 is a schematic structural cross-sectional view of a low-capacitance transient voltage suppressor according to embodiment 1 of the present invention;
fig. 2 to 8 are schematic cross-sectional structures of silicon wafers in steps 1 to seven of example 1;
FIG. 9 is an equivalent circuit diagram of the device of FIG. 1;
FIG. 10 is a schematic diagram of current paths of a shallow N +/P + junction, a deep N +/P + junction, and an N + buried layer/P + junction breakdown first, and surge and electrostatic discharge when the input terminal of the device in embodiment 1 is subjected to surge voltage or electrostatic discharge impact;
FIG. 11 is a schematic diagram of a current path for current to flow into a P-epi below an N + buried layer/P-epi junction when the device is subjected to a larger surge or electrostatic discharge;
fig. 12 is a schematic cross-sectional view of a low-capacitance tvs structure in embodiment 2;
fig. 13 is a schematic cross-sectional view of a low-capacitance tvs structure in embodiment 3;
fig. 14 is a schematic cross-sectional view of a low-capacitance tvs structure according to embodiment 4;
fig. 15 is a schematic cross-sectional view of a low-capacitance tvs structure according to embodiment 5;
the reference numbers in the figures illustrate:
in fig. 1 to 13:
100-N + substrate;
101-P-epitaxy;
1011-N + buried layer; 1011. 1012, 1013-first, second, third of N + buried layer;
102-P epitaxy;
1021-deep N + region; 10211. 10212, 10213-deep N + regions one, two, three;
1022-P + region; 10221. 10222-P + regions one, two;
103-shallow N + layer;
104-front side metal layer;
105-back side metal layer;
106. 107-deep N + polysilicon deep grooves I and II;
in fig. 14:
200-P-substrate; 2001. 2002-one and two buried layers of N +;
201-P + epitaxy; 2011. 2012-deep N + regions one, two;
202-Back side N +;
203-shallow N + layer;
204 — front side metal layer;
205 — back side metal layer;
FIG. 15:
300-P + substrate;
301-N-epitaxy;
3011. 3012-P + buried layer;
302-N + region;
3021. 3022-deep P + regions one and two;
1022-P + region; 10221. 10222-P + regions one, two;
303-shallow P + layer;
304 — front side metal layer;
305-back side metal layer.
Detailed Description
Example 1
A low capacitance Transient Voltage Suppressor (TVS) with a structure shown in FIG. 1, which is an N + substrate silicon wafer with a resistivity of 0.0005-0.01 Ω cmN +, comprising:
an N + substrate 100, wherein a P-epitaxy 101 with the thickness of 4-12 μm and the resistivity of 20-200 omega cm and a back metal layer 105 with the back surface serving as a grounding end are grown on the front surface of the N + substrate;
two N + buried layers I, II 1011 and 1012 are respectively arranged on the left and right sides in the upper surface of the P-epitaxy 101, and deep N + regions are connected to the upper surfaces of the two N + buried layers I, II 1011 and 1012A first and a second 10211, 10212, a P + region 1022 connected with the P-epitaxy 101 between the first and the second 10211, 10212, wherein the ion implantation elements of the N + buried layers 1011, 1012 are antimony or arsenic, and the implantation dosage is 1E 15-1E 16/cm2The implantation energy is 100-120 KeV, and the implantation angle is 7 degrees;
a shallow N + layer 103 is formed on the upper surfaces of the two deep N + regions one, two 10211, 10212 and the P + region 1022;
the shallow N + layer 103 has a front side metal layer 104 as an input terminal.
The low-capacitance transient voltage suppressor provided in this embodiment is prepared by the following steps, as shown in fig. 2 to 8, which are schematic cross-sectional structures of silicon wafers in steps 1 to 7:
step 1: firstly, selecting a 100N + type substrate silicon wafer, and then growing a layer of P-epitaxy 101 with the thickness of 4-12 mu m and the resistivity of 20-200 omega cm on the upper surface of the silicon wafer, as shown in figure 2;
step 2: carrying out photoetching and ion implantation on the upper surface of the P-epitaxy 101 by using an N + buried layer, locally carrying out implantation on the surface of the N + buried layer 1011, and entering a high-temperature furnace tube for thermal process propulsion at the temperature of 1100-1200 ℃ for 80-120 minutes to obtain a silicon wafer shown in figure 3;
and step 3: carrying out second epitaxial growth on the surface, and growing a P epitaxial layer 102 with the thickness of 3-10 microns and the resistivity of 0.1-50 omega cm to obtain the silicon wafer shown in the figure 4;
and 4, step 4: defining a deep N + well region on the surface of the P epitaxy 102 by deep N + photoetching, and then carrying out deep N + ion implantation, wherein phosphorus is implanted into the deep N + ions at an implantation dose of 5E 15-1E 16/cm2Injecting energy of 100K-1 MeV to obtain the silicon wafer shown in the figure 5;
and 5: defining a P + region on the surface by P + photoetching, and then carrying out P + ion implantation, wherein boron is implanted into the P + region by ions, the implantation dose is 5E 15-1E 16/cm2, and the implantation energy is 100K-1 MeV; the silicon wafer enters a furnace tube to be advanced at high temperature, wherein the advancing condition of the high temperature is 1100-1150 ℃, the time range is 60-360 minutes, so that a deep N + region 1021 is connected with an N + buried layer 1011, and a P + region 1022 is connected with a P-epitaxy 101, and the silicon wafer shown in the figure 6 is obtained;
step 6: forming a shallow N + region 103 on the surface of the deep N + region 1021 and the P + region 1022 by shallow N + region lithography and ion implantation, wherein the shallow N + region is ion-implanted with phosphorus or arsenic at a dose of 1E 15-1E 16/cm2Injecting energy of 60-100 KeV, then performing an annealing process, annealing for 30-60 minutes at 900-950 ℃ by using a furnace tube to activate injected impurities, eliminating injection damage and preventing junction leakage, and obtaining the silicon wafer shown in FIG. 7;
and 7: performing metal deposition on the surface of the shallow N + region 103 to form a front metal layer 104 with the thickness ranging from 2 to 6 microns, and using the front metal layer as an input end to obtain a silicon wafer shown in FIG. 8;
and 8: and (3) carrying out blue film pasting protection on the front surface of the silicon wafer, then thinning the back surface of the silicon wafer to 80-150 microns through chemical mechanical grinding, and then carrying out metal evaporation or deposition process on the back surface of the silicon wafer to form a back metal layer 105 serving as a grounding end to obtain the low-capacitance transient voltage suppressor.
The back of the silicon chip is thinned, so that the substrate resistance can be further reduced, and the reduction of the on-resistance and the clamping voltage is facilitated.
The temperature of the epitaxial process is not limited, and the epitaxial process can be grown by a conventional high-temperature technology or a low-temperature technology. More preferably, a thin concentration buffer layer can be added between the P-epitaxy and the N + substrate.
In step 4, the deep N + may be implanted with a plurality of times of energy from large to small in order to obtain better on-state characteristics.
In step 5, the P + region may also be implanted with ions of decreasing energy for a plurality of times to obtain better on-state characteristics.
In step 6, the annealing process can also use a rapid thermal annealing (RTP) process, wherein the annealing temperature is 980-1100 ℃ and the annealing time is 15-45 seconds.
In the step 7, aluminum, an aluminum-silicon compound or a titanium, titanium nitride and aluminum are used for metal deposition, or a three-layer structure is formed by titanium, titanium nitride and aluminum, wherein the thickness of titanium is 300-600 Å, and the thickness of titanium nitride is 400-1000 Å.
An equivalent circuit of the device of the present embodiment is shown in fig. 9, where Q1 is an NPN transistor formed by a deep N +/N + buried layer/P +/P-epi/N + substrate on the left side of fig. 1, Q2 is an NPN transistor formed by a deep N +/N + buried layer/P +/P-epi/N + substrate on the right side of fig. 1, and Q3 is an NPN transistor formed by a shallow N +/P-epi/N + substrate in the middle of fig. 1.
Embodiments add an N + buried layer between the substrate and the epitaxy and lead out through a deep N +/shallow N + region. Because the shallow N +, deep N +, N + buried layer and the P + region are all heavily doped, three PN junctions formed by the shallow N +/P + junction, the deep N +/P + junction and the N + buried layer/P + junction have lower reverse breakdown voltage. When the input end of the device is impacted by surge voltage or electrostatic discharge, the three junctions break down first, so that compared with the traditional TVS, two junctions (a deep N +/P + junction, an N + buried layer/P + junction) are added, the current conducting area is increased, and the current capacity of surge and electrostatic discharge is greatly improved. The current path is shown by the black arrows in fig. 10.
When the device of this embodiment encounters a larger surge or electrostatic discharge, another NP junction, consisting of a shallow N +/deep N +/P-epi, will also turn on conduction in addition to the current path shown in fig. 10, since the P-epi has a lower doping concentration and therefore a slightly higher breakdown voltage. Namely, current flows into the P-epitaxial body below the N + buried layer/P-epitaxial junction through the N + buried layer/P-epitaxial junction, which is equivalent to increasing the current conducting area again and further improving the surge impact resistance and the electrostatic discharge resistance. The additional current paths are shown by the white arrows in fig. 11.
Example 2
A low capacitance tvs, otherwise the same as in example 1, except that a third N + buried layer having the same structure and doping concentration and a corresponding deep N + third are added between two N + buried layers, and P + regions are doped between the deep N + regions, as shown in fig. 12, and an N + substrate silicon wafer having a resistivity of 0.0005 to 0.01 Ω cmN + is used, comprising:
an N + substrate 100, wherein a P-epitaxy 101 with the thickness of 4-12 μm and the resistivity of 20-200 omega cm and a back metal layer 105 with the back surface serving as a grounding end are grown on the front surface of the N + substrate;
three N + buried layers I, II, III 1011, 1012, 1013 are arranged in the upper surface of the P-epitaxy 101, and three N + buried layers I, II are arranged in the upper surface of the P-epitaxyThe upper surfaces of the three 1011, 1012 and 1013 are connected with a first deep N + region, a second deep N + region, a third deep N10211, a 10212 and a 10213, a first P + region, a second deep N + region 10221 and a P + region 10222 are connected with the P-epitaxy 101 between the first deep N + region, the third deep N + region 10211 and the deep N + region 10213 and the second deep N + region, the third deep N + region 10212 and the deep N + region 10213, wherein the ion implantation element of the first N + buried layer, the second deep N + buried layer, the third deep N + buried layer, the 1012 and the deep 1013 is antimony or arsenic, and the2The implantation energy is 100-120 KeV, and the implantation angle is 7 degrees;
a shallow N + layer 103 on the upper surface of the deep N + region 1021 and the P + region 1022;
the shallow N + layer 103 has a front side metal layer 104 as an input terminal.
Example 3
A low capacitance tvs similar to that of example 1 except that the N + region (well) is replaced by an N + polysilicon deep trench, the structure shown in fig. 13, which uses an N + substrate silicon wafer with a resistivity of 0.0005 to 0.01 Ω cmN +, comprising:
an N + substrate 100;
growing a P-epitaxy 101 with the thickness of 4-12 mu m and the resistivity of 20-200 omega cm and a back metal layer 105 with the back surface serving as a grounding end on the front surface of an N + substrate 100;
the first, the second and the left sides of the N + buried layers 1011 and 1012 are arranged on the left and the right sides in the upper surface of the P-epitaxy 101, a P + region 102 and a shallow N + layer 103 are sequentially grown on the upper surface of the P-epitaxy 101, and two deep N + polysilicon grooves 106 and 107 penetrate through the shallow N + layer 103 and the P + region 102 and are respectively connected with the upper surfaces of the first, the second and the 1012 of the N + buried layers;
the top surfaces of the two deep N + polysilicon trenches I, II 106, 107 and the shallow N + layer 103 are provided with a front metal layer 104 as an input end.
Example 4
A low capacitance tvs, otherwise the same as in embodiment 1, using a P-substrate silicon wafer, and adding an N + region 202 on the back of the P-substrate, as shown in fig. 14, comprising the following structure:
a P-substrate 200;
growing a back surface N +202 on the back surface of the P-substrate 200, wherein a back surface metal layer 205 serving as a grounding end is arranged on the bottom surface of the back surface N + 202;
the first N + buried layer, the second N + buried layer, the first N + region, the second N + region, the first N + region, the second;
a shallow N + layer 203 is arranged on the upper surface of the deep N + region and the P + epitaxy 201;
the shallow N + layer 203 has a front metal layer 204 thereon as an input terminal.
Example 5
A low capacitance transient voltage suppressor is the same as embodiment 1, but different from the silicon chip, and the structure shown in FIG. 15 adopts a P + substrate silicon chip, which includes:
a P + substrate 300;
growing an N-epitaxy layer 301 and a back metal layer 305 with the back surface serving as a grounding end on the front surface of the P + substrate 300;
the first, the second and the third P + buried layers 3011 and 3012 are arranged on the left and the right sides in the upper surface of the N-epitaxy 301, the first, the second and the third P + buried layers 3011 and 3012 are connected with the first, the second and the 3022 of the deep P + region, and an N + region 302 is arranged between the first, the second and the 3022 of the deep P + region and connected with the N-epitaxy 301;
a shallow P + layer 303 is formed on the upper surfaces of the deep P + regions 3021 and 3022 and the N + region 302;
the shallow P + layer 303 has a front metal layer 304 as an input terminal.
The foregoing is illustrative of the preferred embodiments of the present invention and is not to be construed as limiting thereof in any way. Although the invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or equivalent modifications, without departing from the spirit and scope of the invention, using the methods and techniques disclosed above. Therefore, any modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims (16)

1. A low-capacitance transient voltage suppressor adopts a substrate silicon wafer, and is characterized in that an N + buried layer is additionally arranged between a substrate and an epitaxy and is led out through a deep N +/shallow N + region, or a P + buried layer is additionally arranged between the substrate and the epitaxy and is led out through a deep P +/shallow P + region.
2. A low capacitance TVS as claimed in claim 1 wherein said substrate is an N + substrate layer, wherein,
growing a P-epitaxial layer and a metal layer with the back as a grounding terminal on the front side of the N + substrate;
two N + buried layers are arranged in the upper surface of the P-epitaxial layer, the N + buried layers are connected with deep N + regions, and the P + regions between the deep N + regions are connected with the P-epitaxial layer;
a shallow N + layer is arranged on the upper surfaces of the deep N + region and the P + region;
and a front metal layer is arranged on the shallow N + layer and is used as an input end.
3. A low capacitance tvs according to claim 1 or 2, wherein said substrate is an N + substrate silicon wafer having a resistivity of 0.0005-0.01 Ω cm.
4. A low capacitance tvs according to claim 2, wherein a thin concentration buffer layer is added between the P-epi and the N + substrate.
5. The transient voltage suppressor of claim 2, wherein said P-epi layer has a thickness of 4-12 μm and a resistivity of 20-200 Ω cm.
6. The TVS of claim 2, wherein the N + buried layer is implanted with antimony or arsenic at a dose of 1E 15-1E 16/cm2The implantation energy is 100 to 120KeV, and the implantation angle is 7 degrees.
7. The transient voltage suppressor of claim 2, wherein said N + region is replaced by an N + polysilicon deep trench, using an N + substrate silicon wafer, comprising:
growing a P-epitaxy layer with the thickness of 4-12 mu m and the resistivity of 20-200 omega cm on the front surface of the N + substrate and a back metal layer with the back surface serving as a grounding end;
more than two N + buried layers are arranged in the upper surface of the P-epitaxy, a P + region layer and a shallow N + layer are sequentially grown on the upper surface of the P-epitaxy, more than two deep N + polycrystalline silicon deep grooves corresponding to the number of the N + buried layers penetrate through the shallow N + layer and the P + region layer is connected with the upper surface of the N + buried layer;
and front metal layers are arranged on the deep N + polysilicon groove and the shallow N + layer and are used as input ends.
8. The low-capacitance transient voltage suppressor according to claim 1, wherein a P-substrate silicon wafer is adopted, and an N + region layer is added on the back surface of the P-substrate, and the low-capacitance transient voltage suppressor comprises the following structure:
growing a back N + layer on the back of the P-substrate 200, wherein a back metal layer serving as a grounding end is arranged on the bottom surface of the back N + layer;
more than two N + buried layers are arranged in the upper surface of the P-substrate, the upper surfaces of the N + buried layers are connected with deep N + regions, and a P + epitaxy is arranged between the deep N + regions and connected with the P-substrate;
a shallow N + layer is arranged on the upper surface of the deep N + region and the upper surface of the P + epitaxy;
the shallow N + layer 203 has a front metal layer 204 thereon as an input terminal.
9. The low-capacitance transient voltage suppressor according to claim 1, wherein a P + substrate silicon wafer is used, comprising:
growing a layer of N-epitaxy on the front surface of the P + substrate and a back metal layer with the back surface serving as a grounding end;
more than two P + buried layers are arranged in the upper surface of the N-epitaxy, the upper surface of each P + buried layer is connected with deep P + regions, and the N + regions among the deep P + regions are connected with the N-epitaxy;
a shallow P + layer is arranged on the upper surfaces of the deep P + region and the N + region;
the shallow P + layer has a front metal layer 304 as an input terminal.
10. A method of manufacturing a low capacitance transient voltage suppressor according to any of claims 2-6, comprising the steps of:
step 1: firstly, selecting an N + type substrate silicon wafer, and then growing a P-epitaxial layer with the thickness of 4-12 mu m and the resistivity of 20-200 omega cm on the upper surface of the N + type substrate silicon wafer;
step 2: photoetching and ion implantation are carried out on the upper surface of the P-epitaxial layer through an N + buried layer, implantation of the N + buried layer is carried out on the partial surface of the P-epitaxial layer, and the P-epitaxial layer enters a high-temperature furnace tube to carry out thermal process propulsion;
and step 3: carrying out second epitaxial growth on the surface, and growing a P-type epitaxial layer with the thickness of 3-10 microns and the resistivity of 0.1-50 omega cm;
and 4, step 4: defining a deep N + well region on the surface of the P epitaxial layer by deep N + photoetching, and then carrying out deep N + ion implantation, wherein phosphorus is implanted into the deep N + ions, and the implantation dosage is 5E 15-1E 16/cm2The injection energy is 100K-1 MeV;
and 5: defining a P + region on the surface by P + photoetching, and then carrying out P + ion implantation, wherein boron is implanted into the P + region by ion implantation with the implantation dosage of 5E 15-1E 16/cm2The injection energy is 100K-1 MeV; the silicon wafer enters a furnace tube to be propelled at high temperature, so that a deep N + region is connected with an N + buried layer, and a P + region is connected with a P-epitaxy layer;
step 6: forming a shallow N + region on the surface of the deep N + region and the surface of the P + region by shallow N + region photoetching and ion implantation, wherein phosphorus or arsenic is implanted into the shallow N + region in an implantation dosage of 1E 15-1E 16/cm2Injecting energy of 60-100 KeV, and then performing an annealing process;
and 7: performing metal deposition on the surface of the shallow N + region to form a front metal layer with the thickness ranging from 2 to 6 microns as an input end;
and 8: and (3) carrying out blue film pasting protection on the front surface of the silicon wafer, then thinning the back surface of the silicon wafer to 80-150 microns through chemical mechanical grinding, then carrying out metal evaporation or deposition process on the back surface of the silicon wafer to form back surface metal which is used as a grounding end, and obtaining the low-capacitance transient voltage suppressor.
11. The method of claim 10, wherein the furnace tube in step 2 is heated at 1100-1200 ℃ for 80-120 minutes.
12. The method as claimed in claim 10, wherein in step 4, the deep N + is subjected to ion implantation with energy decreasing from large to small for obtaining better on-state characteristics.
13. The method as claimed in claim 10, wherein in step 5, the P + region is implanted with ions with energy from large to small for a plurality of times to obtain better on-state characteristics.
14. The method as claimed in claim 10, wherein in step 5, the high temperature driving condition is 1100-1150 ℃ for 60-360 minutes according to the thickness of the epitaxial layer, so that the deep N + region is connected to the N + buried layer and the P + region is connected to the P-epi.
15. The method for manufacturing a low-capacitance transient voltage suppressor according to claim 10, wherein in step 6, the annealing process is performed by using a furnace tube under the process conditions of 900-950 ℃ for 30-60 minutes; or a rapid thermal annealing (RTP) process is used, wherein the process conditions are 980-1100 ℃ and the time is 15-45 seconds.
16. The method of claim 10, wherein the metal deposition in step 7 is aluminum, aluminum silicon, or a combination of titanium, titanium nitride, and aluminum, wherein the thickness of titanium is 300-600 Å, the thickness of titanium nitride is 400-1000 Å, and the total metal is total.
CN202010236372.XA 2020-03-30 2020-03-30 Low-capacitance transient voltage suppressor and manufacturing method thereof Pending CN111312708A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367393A (en) * 2012-03-28 2013-10-23 上海华虹Nec电子有限公司 Transient voltage suppressing device and manufacturing technology method
US20170141097A1 (en) * 2014-12-09 2017-05-18 Madhur Bobde TVS Structures for High Surge AND Low Capacitance
CN207217533U (en) * 2017-08-16 2018-04-10 上海领矽半导体有限公司 A kind of low appearance Transient Voltage Suppressor of miniaturization
CN110416335A (en) * 2019-08-05 2019-11-05 南京邮电大学 Silicon substrate near-infrared single photon avalanche diode detector and preparation method thereof
CN212434623U (en) * 2020-03-30 2021-01-29 上海维安半导体有限公司 Low-capacitance transient voltage suppressor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367393A (en) * 2012-03-28 2013-10-23 上海华虹Nec电子有限公司 Transient voltage suppressing device and manufacturing technology method
US20170141097A1 (en) * 2014-12-09 2017-05-18 Madhur Bobde TVS Structures for High Surge AND Low Capacitance
CN207217533U (en) * 2017-08-16 2018-04-10 上海领矽半导体有限公司 A kind of low appearance Transient Voltage Suppressor of miniaturization
CN110416335A (en) * 2019-08-05 2019-11-05 南京邮电大学 Silicon substrate near-infrared single photon avalanche diode detector and preparation method thereof
CN212434623U (en) * 2020-03-30 2021-01-29 上海维安半导体有限公司 Low-capacitance transient voltage suppressor

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