CN111312692A - Integrated circuit packaging element and carrier plate thereof - Google Patents
Integrated circuit packaging element and carrier plate thereof Download PDFInfo
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- CN111312692A CN111312692A CN201811507440.0A CN201811507440A CN111312692A CN 111312692 A CN111312692 A CN 111312692A CN 201811507440 A CN201811507440 A CN 201811507440A CN 111312692 A CN111312692 A CN 111312692A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
An integrated circuit package device and a carrier thereof. The integrated circuit package device comprises a chip device and a package module. The chip device includes two driving units. The packaging module is connected with the chip element and comprises two power supply wiring networks and a grounding shielding structure. The power supply wiring network is electrically connected with the driving units respectively. The grounding shielding structure is arranged between the two power supply wiring networks and used for blocking the power supply noise coupling generated by the two power supply wiring networks. Thus, by the above structure, the power noise coupling generated between the two power wiring networks can be reduced, thereby reducing the signal jitter at the output terminal of the chip device and improving the noise isolation and signal integrity of the chip device.
Description
Technical Field
The present invention relates to an integrated circuit package device, and more particularly, to an integrated circuit package device with shield ground and a carrier thereof.
Background
The current flip chip technology has been widely used in the field of chip packaging because of its advantages of reducing the chip packaging area and signal transmission path. Generally, the finished chip (die) is disposed on a carrier and is packaged by an integrated circuit to form a semiconductor package device. After the semiconductor package device is mounted on a circuit board, the chip can exchange signals through the circuit board.
However, as the size design of the semiconductor package devices is in a trend toward high density, Power Distribution Networks (PDNs) in the semiconductor package devices are disposed closely to each other, which often causes crosstalk (crosstalk) phenomenon of power noise coupling, thereby causing jitter (jitter) and further reducing signal integrity (signal integrity) of the semiconductor chip.
Disclosure of Invention
An embodiment of the invention provides an integrated circuit package component. The integrated circuit package device comprises a chip device and a package module. The chip device includes a first driving unit and a second driving unit. The first driving unit is connected with the second driving unit. The packaging module is connected with the wafer element and comprises a first power supply wiring network, a second power supply wiring network, a grounding shielding structure and a grounding area. The first power supply wiring network is electrically connected with the first driving unit and used for transmitting power to the first driving unit. The second power supply wiring network is electrically connected with the second driving unit and used for transmitting power to the second driving unit. The ground shield structure is completely arranged between the first power supply wiring network and the second power supply wiring network and used for blocking power supply noise coupling generated by the first power supply wiring network and the second power supply wiring network. The grounding area is connected with the first power supply wiring network, the second power supply wiring network and the grounding shielding structure.
According to one or more embodiments of the present invention, in the integrated circuit package device, the package module further includes a carrier, a plurality of first contacts and a plurality of second contacts. The first contacts are distributed on one surface of the carrier plate. The second contacts are distributed on the other surface of the carrier plate. The first power supply wiring network, the second power supply wiring network and the grounding shielding structure are respectively positioned in the carrier plate and are connected with the first contacts and the second contacts, and the first power supply wiring network and the second power supply wiring network are respectively connected with the first driving unit and the second driving unit through the first contacts.
According to one or more embodiments of the present invention, in the integrated circuit package device, the carrier includes a plurality of layers. These layers are laminated to each other. The first power supply wiring network comprises at least one first through conducting part. The second power supply wiring network comprises at least one second penetrating conducting part, and the grounding shielding structure comprises at least one third penetrating conducting part. The first through conduction part, the second through conduction part and the third through conduction part are all located in the same layer, and the third through conduction part is located between the first through conduction part and the second through conduction part.
In accordance with one or more embodiments of the present invention, in the integrated circuit package device, the first power routing network and the second power routing network are electrically isolated from each other.
In one or more embodiments of the present invention, in the integrated circuit package device, the first power routing network and the second power routing network are both rf signal routing structures.
In the integrated circuit package device according to one or more embodiments of the present invention, the chip device has a serializer-deserializer. The first driving unit is a front driving unit of the serializer-deserializer. The second driving unit is a rear driving unit of the serializer-deserializer. The first power supply wiring network and the second power supply wiring network are positioned in the same circuit area block corresponding to the serializer-deserializer.
In accordance with one or more embodiments of the present invention, in the integrated circuit package device, the integrated circuit package device is a ball grid array package device.
Another embodiment of the present invention provides a carrier for carrying wafer components. The carrier plate comprises a plate body, a first power supply wiring network, a second power supply wiring network, a grounding shielding structure and a grounding area. The plate body is provided with a first surface and a second surface which are opposite. The first power supply wiring network penetrates through the board body, is connected with the first surface and the second surface and is used for being electrically connected with a driving unit of the chip element through the first surface. The second power supply wiring network penetrates through the board body, is connected with the first surface and the second surface and is used for being electrically connected with the other driving unit of the chip element through the first surface. The grounding shielding structure penetrates through the plate body, is connected with the first surface and the second surface, is arranged between the first power supply wiring network and the second power supply wiring network, is electrically connected with the wafer element and is used for blocking the coupling of power supply noise generated by the first power supply wiring network and the second power supply wiring network. The grounding area is located on the plate body and connected with the first power supply wiring network, the second power supply wiring network and the grounding shielding structure.
According to one or more embodiments of the present invention, in the carrier plate, the plate body further includes a plurality of layer bodies. These layers are laminated to each other. The first power supply wiring network comprises at least one first through conducting part. The second power supply wiring network comprises at least one second penetrating conducting part, and the grounding shielding structure comprises at least one third penetrating conducting part. The first through conduction part, the second through conduction part and the third through conduction part are all located in the same layer, and the third through conduction part is located between the first through conduction part and the second through conduction part.
According to one or more embodiments of the present invention, in the carrier board, the first power wiring network and the second power wiring network are electrically isolated from each other.
Thus, with the structure of the above embodiment, the power noise coupling generated between the first power routing network and the second power routing network can be reduced, thereby reducing the signal jitter (jitter) at the output terminal of the chip device, and improving the noise isolation and signal integrity of the chip device.
The foregoing is merely illustrative of the problems, solutions to problems, and other advantages that may be realized and attained by the invention, and the details of which are set forth in the following description and the drawings.
Drawings
In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description taken in conjunction with the accompanying drawings in which:
fig. 1 is a top view of an integrated circuit package component of one embodiment of the present invention positioned in a wiring board;
FIG. 2 is a cross-sectional view of an integrated circuit package device according to an embodiment of the invention;
fig. 3 is a schematic view of a carrier in one layer according to an embodiment of the invention;
FIG. 4 is a graph showing electromagnetic simulation results comparing two modules of an integrated circuit package device before optimization and an integrated circuit package device according to an embodiment of the invention;
FIG. 5A is a graph of power noise waveforms of an integrated circuit package device before optimization;
FIG. 5B is a power noise waveform of an integrated circuit package device according to an embodiment of the present invention;
FIG. 6A is an eye diagram of signal waveforms for an integrated circuit package component before optimization; and
FIG. 6B is an eye diagram of signal waveforms of an integrated circuit package device according to an embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the various embodiments of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, these implementation details are not necessary in the embodiments of the present invention. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simplified schematic manner.
Fig. 1 is a top view of an integrated circuit package element 10 in a wiring board 500 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view of an integrated circuit package component 10 according to an embodiment of the invention. As shown in fig. 1 and 2, the ic package component 10 is configured to be soldered to a wiring board 500 (e.g., a hard pcb, a flexible pcb, or other circuit carrier substrate). The integrated circuit package device 10 includes a chip device 100 and a package module 200. The chip device 100 includes a first driving unit 111 and a second driving unit 112. The first driving unit 111 has an on-chip power network (on-chip power network), and the second driving unit 112 has another on-chip power network (on-chip power network). The two on-chip power supply networks are independent of each other. The package module 200 is connected to the chip component 100 and is combined with the chip component 100 to form the integrated circuit package component 10. The package module 200 includes a first power routing network 240, a second power routing network 250, a ground shielding structure 260, a signal routing structure 270, and a ground region (not shown). The first power supply wiring network 240 is electrically connected to the first driving unit 111 for transmitting power to the first driving unit 111. For example, the first power supply wiring network 240 delivers power from the wiring board 500 to the on-board power supply network of the first drive unit 111. The second power routing network 250 is electrically connected to the second driving unit 112 for transmitting power to the second driving unit 112. For example, the second power wiring network 250 delivers power from the wiring board 500 to another on-board power supply network of the second drive unit 112. The first power routing net 240 and the second power routing net 250 are electrically isolated from each other. The signal routing structure 270 is electrically connected to the second driving unit 112 for transmitting signals processed therein from the second driving unit 112 to the ic package device 10. For example, the signal wiring structure 270 transfers signals processed inside thereof to the wiring board 500. The ground region connects the first power routing network 240, the second power routing network 250, and the ground shield structure 260. For example, the ground region contacts a common ground 520 of the patch panel 500 such that the ground shield structure 260, the first power routing network 240, and the second power routing network 250 all have a common ground.
For example, in the present embodiment, the wafer device 100 is applied to a High-speed serial Link Technology (High-speed serial Link Technology), and has a serializer-deserializer 110 (SerDes) operation interface. The first driving unit 111 is a front driving unit (e.g., receiving end, RX) of the serializer-deserializer 110, and the second driving unit 112 is a rear driving unit (e.g., transmitting end, TX) of the serializer-deserializer 110, and the rear driving unit is connected to the front driving unit. The front-end driving unit is used for processing internal signals, and the rear-end driving unit is used for sending signals processed inside the front-end driving unit out of the chip component 100. The wafer element 100 also contains channels (not shown).
In the present embodiment, the first power routing network 240 and the second power routing network 250 are located in the same circuit block corresponding to the serializer-deserializer 110. In the present embodiment, the first power routing network 240 and the second power routing network 250 are both rf signal routing structures or analog signal routing structures, however, the invention is not limited thereto.
To reduce crosstalk between power sources due to coupling, the present embodiment improves the isolation between parasitic inductances of the power sources and the crossed power domains, for example, by disposing the ground shield structure 260 between the first power routing network 240 and the second power routing network 250. Since the first power routing net 240 and the second power routing net 250 are closely arranged, when the first power routing net 240 and the second power routing net 250 generate power noise coupling, because the ground shielding structure 260 is interposed between the first power routing net 240 and the second power routing net 250, the ground shielding structure 260 can block the power noise coupling generated by the first power routing net 240 and the second power routing net 250 as much as possible, thereby effectively suppressing the crosstalk phenomenon, further reducing the signal jitter (jitter) of the signal routing structure 270 (i.e., the output terminal of the chip device), and improving the noise isolation and signal integrity of the chip device 100.
More specifically, in the present embodiment, the package module 200 further includes a package body 210, a carrier 220, a plurality of first contacts 300, and a plurality of second contacts 400. The chip component 100 is placed on the carrier 220. The package 210 encapsulates the chip device 100 and the carrier 220 and fixes the chip device 100 and the carrier 220 in the package 210. The grounding region is located on the carrier 220. The carrier 220 includes a plate 230. The plate body 230 has a first surface 231 and a second surface 232 opposite to each other. The first contacts 300 are distributed on the first surface 231 of the board body 230. The first contacts 300 are, for example, conductive bumps (bumps). These second contacts 400 are, for example, ball pads (ball pads). However, the invention is not limited to the type of integrated circuit package component 10.
The first power supply wiring network 240 penetrates the board body 230, connects the first surface 231 and the second surface 232, and is electrically connected to the first driving unit 111 through the first surface 231 and the wiring board 500 through the second surface 232. Further, the first power wiring network 240 is connected to the first driving unit 111 through a part of the first contacts 300, connected to the power supply point 510 of the wiring board 500 through a part of the second contacts 400, and electrically connected to the common ground 520 of the wiring board 500 through the ground area.
The second power supply wiring network 250 penetrates the board body 230, connects the first surface 231 and the second surface 232, and is electrically connected to the second driving unit 112 through the first surface 231 and the wiring board 500 through the second surface 232. Further, the second power wiring network 250 is connected to the second driving unit 112 through another part of the first contacts 300, connected to the power supply point 510 of the wiring board 500 through another part of the second contacts 400, and electrically connected to the common ground 520 of the wiring board 500 through the ground area.
The ground shield 260 penetrates the board 230, connects the first surface 231 and the second surface 232, is interposed between the first power wiring network 240 and the second power wiring network 250, and is electrically connected to the chip component 100 through the first surface 231. Further, the ground shield structure 260 is connected to the chip element 100 through another part of the first contacts 300, and is electrically connected to the common ground 520 of the wiring board 500 through the ground area.
The signal wiring structure 270 penetrates the board body 230, connects the first surface 231 and the second surface 232, is electrically connected to the second driving unit 112 through the first surface 231, and is electrically connected to the wiring board 500 through the second surface 232, so as to transmit the signal processed by the second driving unit 112 to the wiring board 500. Further, the signal wiring structure 270 is connected to the second driving unit 112 through another part of the first contacts 300, and is connected to the wiring board 500 through another part of the second contacts 400.
The package module 200 also includes other ground shield structures 280. The other ground shielding structure 280 is not located between the first power routing network 240 and the second power routing network 250, and is connected to the ground region to serve as a ground terminal for the other power routing networks.
In the embodiment, although the first power routing network 240, the second power routing network 250 and the ground shielding structure 260 are all located on the carrier 220, the invention is not limited thereto, and in other embodiments, the first power routing network 240, the second power routing network 250 and the ground shielding structure 260 may be located in other elements in the package module 200.
More specifically, the carrier 220 includes a plurality of layer bodies 233. These layer bodies 233 are provided laminated with each other. The vertical direction from the first surface 231 to the second surface 232 is the same as the stacking direction of the layer bodies 233. The first power wiring network 240 penetrates through these layers 233. For example, the first power routing network 240 is stepped and includes a plurality of first through vias 241 and a plurality of first planar vias 242. These first through-conductors 241 are parallel to each other. Each first through conductive portion 241 penetrates one of the layer bodies 233. Each first planar conducting portion 242 is located between any two layer bodies 233 and is connected to any two first through conducting portions 241. The first Through Via portion 241 is, for example, a Through Silicon Via (TSV), however, the invention is not limited thereto.
The second power wiring network 250 penetrates through these layers 233. For example, the second power routing network 250 is stepped and includes a plurality of second through vias 251 and a plurality of second planar vias 252. The second through lead parts 251 are parallel to each other. Each second through guide 251 penetrates one of the layer bodies 233. Each second planar conducting portion 252 is located between any two layer bodies 233 and is connected to any two second through conducting portions 251. The second Through connection portion 251 is, for example, a Through Silicon Via (TSV), however, the invention is not limited thereto.
The ground shield structure 260 extends through the layers 233. The ground shield 260 is stepped and includes a plurality of third through conductive portions 261 and a plurality of third planar conductive portions 262. These third through leads 261 are parallel to each other. Each third through-connection portion 261 penetrates one of the layer bodies 233. Each third plane conductive portion 262 is located between any two layer bodies 233 and connected to any two third through conductive portions 261. The third Through connection portion 261 is, for example, a Through Silicon Via (TSV), however, the present invention is not limited thereto.
It should be understood that each layer 233 has a first through conductive portion 241, a second through conductive portion 251 and a third through conductive portion 261, and the third through conductive portion 261 in each layer 233 is located between the first through conductive portion 241 and the second through conductive portion 251, so that the ground shielding structure 260 is completely located between the first power distribution network 240 and the second power distribution network 250.
Fig. 3 is a schematic view of a carrier 221 in which a layer 233 is disposed according to an embodiment of the invention. As shown in fig. 3, the carrier board 221 of fig. 3 is substantially the same as the carrier board 220 of fig. 1, and one of the differences is: as shown in fig. 2 and 3, the number of the ground shielding structures 260A may be multiple (e.g., 2 to 3), and the ground shielding structures 260A are arranged to form a virtual interface a. The virtual interface a is arranged between two first through conductive portions 241 and one second through conductive portion 251, so as to block the power noise coupling generated between any one of the first through conductive portions 241 and any one of the second through conductive portions 251. For example, the first power routing net 240 surrounds the second power routing net 250, and the ground shield structure 260A is located between the first power routing net 240 and the second power routing net 250.
Fig. 4 shows the results of electromagnetic simulations of the integrated circuit package component before optimization (see curve C1) and the integrated circuit package component 10 according to an embodiment of the present invention (see curve C2). In the present embodiment, the integrated circuit package device is a ball grid array package device, and the carrier has 10 layers, and the total thickness thereof is 850 μm. As can be seen from fig. 4, compared to the ic package before optimization, the ic package 10 of the present embodiment has a crosstalk suppression (crosstalk suppression) capability, and particularly in the frequency band above 9GHz, the ic package is better than the ic package before optimization.
In addition, compared with the curve C1 of the ic package device before optimization and the curve C2 of the present embodiment, it can be seen that, when the electromagnetic simulation result of fig. 4 is at 5.5GHz (see the position of arrow R), the curve C2 of the design of the present embodiment is significantly reduced by 12dB, and thus, the electromagnetic wave isolation is significantly improved. Therefore, shielding the ground shielding structure 260 between the first power routing network 240 and the second power routing network 250 does have a significant shielding effect.
FIG. 5A is a graph of power noise waveforms of an integrated circuit package device before optimization. FIG. 5B is a power noise waveform of an integrated circuit package device according to an embodiment of the invention. Fig. 6A is an eye diagram of signal waveforms for an integrated circuit package component before optimization. FIG. 6B is an eye diagram of signal waveforms of an integrated circuit package device according to an embodiment of the invention.
Fig. 5A and 6A are power noise waveforms, where the unit of X-axis is nano-second (n) and the unit of Y-axis is voltage (V). Fig. 5A and 6A are signal waveform eye diagrams in which the unit of the X-axis is pico-second (p) and the unit of the Y-axis is voltage (V). As shown in fig. 5A and 5B, two power routing nets (see curves C4, C5, fig. 5A) in the ic package before optimization generate a noise coupling ratio of 1: 1, its power supply noise induced jitter (see segment J1, fig. 5B) is 5.25 per picosecond (ps); in contrast, as shown in fig. 6A and 6B, when the design of the present embodiment reduces the noise coupling ratio generated by the first power routing network and the second power routing network (see curves C6, C7, fig. 6A) to 1: at 0.1, its power supply noise-induced jitter (see line segment J2, fig. 6B) is reduced to 1.02 per picosecond (ps). Therefore, in the output target diagram of the high-speed serial link up to 28Gbps, the jitter caused by the power supply noise is reduced by 80%, and the manufacturing cost of the package is not increased.
Finally, the above-described embodiments are not intended to limit the invention, and those skilled in the art should be able to make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the appended claims.
Claims (10)
1. An integrated circuit package device, comprising:
a chip element including a first driving unit and a second driving unit, the first driving unit being connected to the second driving unit; and
a package module connected to the chip device, comprising:
a first power supply wiring network electrically connected to the first driving unit for transmitting power to the first driving unit;
a second power supply wiring network electrically connected to the second driving unit for transmitting power to the second driving unit;
a ground shield structure completely interposed between the first power wiring network and the second power wiring network, electrically connected to the chip element, for blocking power noise coupling generated by the first power wiring network and the second power wiring network; and
and the grounding area is connected with the first power supply wiring network, the second power supply wiring network and the grounding shielding structure.
2. The integrated circuit package of claim 1, wherein the package module further comprises:
a carrier plate;
the first contacts are distributed on one surface of the carrier plate; and
a plurality of second contacts distributed on the other surface of the carrier,
the first power wiring network, the second power wiring network and the grounding shielding structure are respectively positioned in the carrier plate and are all connected with the plurality of first contacts and the plurality of second contacts, and the first power wiring network and the second power wiring network are respectively connected with the first driving unit and the second driving unit through the plurality of first contacts.
3. The device of claim 2, wherein the carrier comprises a plurality of layers stacked on top of each other, the first power routing network comprises at least a first through conduction portion, the second power routing network comprises at least a second through conduction portion, and the ground shield structure comprises at least a third through conduction portion,
the first through conductive part, the second through conductive part and the third through conductive part are all located in the same one of the layer bodies, and the third through conductive part is located between the first through conductive part and the second through conductive part.
4. The device of claim 1, wherein the first power routing network and the second power routing network are independent and electrically isolated from each other.
5. The device of claim 1, wherein the first power routing network and the second power routing network are both RF signal routing structures.
6. The device of claim 1, wherein the chip component has a serializer-deserializer, the first driving unit is a front-driving unit of the serializer-deserializer, the second driving unit is a rear-driving unit of the serializer-deserializer, and the first power routing network and the second power routing network are located in a same circuit block corresponding to the serializer-deserializer.
7. The device of claim 1, wherein the device is a ball grid array package.
8. A carrier for carrying chip devices, comprising:
the plate body is provided with a first surface and a second surface which are opposite;
a first power supply wiring network penetrating the board body, connecting the first surface and the second surface, and electrically connecting a driving unit of a chip element through the first surface;
a second power supply wiring network penetrating the board body, connecting the first surface and the second surface, and electrically connecting another driving unit of the chip element through the first surface;
a grounding shielding structure penetrating the board body, connecting the first surface and the second surface, and being between the first power supply wiring network and the second power supply wiring network, electrically connecting the chip element, for blocking the power supply noise coupling generated by the first power supply wiring network and the second power supply wiring network; and
and the grounding area is positioned on the plate body and is connected with the first power supply wiring network, the second power supply wiring network and the grounding shielding structure.
9. The carrier board of claim 8, wherein the board body further comprises a plurality of layers stacked on top of each other, the first power wiring network comprises at least a first through-connection portion, the second power wiring network comprises at least a second through-connection portion, and the ground shield structure comprises at least a third through-connection portion,
the first through conductive part, the second through conductive part and the third through conductive part are all located in the same one of the layer bodies, and the third through conductive part is located between the first through conductive part and the second through conductive part.
10. The carrier of claim 8, wherein the first power routing network and the second power routing network are independent and electrically isolated from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811507440.0A CN111312692A (en) | 2018-12-11 | 2018-12-11 | Integrated circuit packaging element and carrier plate thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811507440.0A CN111312692A (en) | 2018-12-11 | 2018-12-11 | Integrated circuit packaging element and carrier plate thereof |
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| US20070138614A1 (en) * | 2005-12-16 | 2007-06-21 | Sige Semiconductor (U.S.), Corp. | Methods for integrated circuit module packaging and integrated circuit module packages |
| CN103035536A (en) * | 2011-09-30 | 2013-04-10 | 台湾积体电路制造股份有限公司 | EMI package and method for making same |
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Application publication date: 20200619 |