CN111309642A

CN111309642A - Memory, control method thereof and memory system

Info

Publication number: CN111309642A
Application number: CN202010088755.7A
Authority: CN
Inventors: 林毅泓; 赵启鹏
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2020-02-12
Filing date: 2020-02-12
Publication date: 2020-06-19
Anticipated expiration: 2040-02-12
Also published as: CN111309642B

Abstract

The invention provides a memory, a control method thereof and a memory system, wherein the memory comprises a memory cell array, a first memory cell array and a second memory cell array, wherein the memory cell array comprises a plurality of first memory cells and a plurality of second memory cells; the controller is provided with a first erasing time table, a second erasing time table and a third erasing time table, the first erasing time table records the erasing times of each first storage unit, and the second erasing time table records the erasing times of each second storage unit; when the memory cell array stores data, a plurality of memory cells in the memory cell array are allowed to be used as the first memory cells and the second memory cells, and the controller forms a third erasure number table and uses the plurality of memory cells as the first memory cells or the second memory cells according to the third erasure number table. The memory provided by the invention has long service life.

Description

Memory, control method thereof and memory system

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a memory, a control method thereof, and a storage system.

Background

A mass storage device typically includes multiple memory devices. Memory devices are used to store data and can be divided into volatile memory devices and non-volatile memory devices. Flash memory devices are an example of Electrically Erasable Programmable Read Only Memory (EEPROM), in which multiple memory cells are erased or programmed in a single programming operation. A program or read operation is performed for each page, and an erase operation is performed for each block. A block may include multiple pages.

However, there is a limit to the number of erasures in a flash memory device, and when an erasure reaches a certain number, the flash memory device will no longer be usable. However, as the data contained in the block tends to increase with the development of the technology, the service life of the storage device is shortened, and the use cost is increased.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a memory and a control method thereof, so as to prolong the service life of the memory and improve the memory of the memory.

To achieve the above and other objects, the present invention provides a memory including:

a memory cell array including a plurality of first memory cells and a plurality of second memory cells;

the controller is provided with a first erasing time table, a second erasing time table and a third erasing time table, the first erasing time table records the erasing times of each first storage unit, and the second erasing time table records the erasing times of each second storage unit;

when the memory cell array stores data, a plurality of memory cells in the memory cell array are allowed to be used as the first memory cells and the second memory cells, and the controller forms a third erasure number table and uses the plurality of memory cells as the first memory cells or the second memory cells according to the third erasure number table.

Further, when the plurality of first storage units are subjected to the erasing step, the first erasing number table is formed, and the first erasing number table is arranged according to the sequence of the plurality of first storage units.

Further, when the plurality of second storage units are subjected to the erasing step, the second erasing number table is formed and arranged according to the sequence of the plurality of second storage units.

Further, when a plurality of memory cells in the memory cell array belong to the first memory cell and the second memory cell, the erase count of the plurality of memory cells is found in the first erase count table, and the erase count of the plurality of memory cells is found in the second erase count table.

Further, the third erasure number table is a ratio of the erasure number of the plurality of memory cells in the first erasure number table to the erasure number of the plurality of memory cells in the second erasure number table, and the third erasure number is arranged according to the sequence of the plurality of memory cells.

Further, when the minimum value in the third erasure number table is smaller than a threshold value, the plurality of memory cells are regarded as the first memory cells, the erasure number of the plurality of memory cells in the first erasure number table is increased, and the third erasure number table is updated.

Further, when the maximum value in the third erasure number table is greater than a threshold value, the plurality of memory cells are regarded as the second memory cells, the erasure number of the plurality of memory cells in the second erasure number table is increased, and the third erasure number table is updated.

Further, when all values in the third erasure number table are larger than a threshold value, the data in the first storage unit is moved into the second storage unit.

Further, the first memory cell comprises a single-layer memory cell, and the second memory cell comprises at least one of a multi-layer memory cell, a three-layer memory cell, and a four-layer memory cell.

Further, the present invention provides a method for controlling a memory, comprising,

forming a first erasing times table and a second erasing times table through a controller, wherein the first erasing times table records the erasing times of a plurality of first storage units, the second erasing times table records the erasing times of a plurality of second storage units, and the first storage units and the second storage units form a storage unit array;

forming a third erasure number table by the controller, and regarding a plurality of memory cells in the memory cell array as the first memory cells or the second memory cells according to the third erasure number table;

and the controller stores the received data in the first storage unit or the second storage unit.

Further, the present invention provides a storage system, comprising,

a host;

a memory connected to the host, wherein the memory comprises,

In summary, the invention provides a memory, a control method thereof and a storage system, wherein a third erasure count table is set according to the advantage of high read-write performance and large number of erasable times of a first storage unit and the advantage of large capacity of a second storage unit, and data is stored in the first storage unit or the second storage unit according to the number of erasure times in the third erasure count table, so as to prolong the service life of the memory and improve the memory of the memory.

Drawings

FIG. 1: a block diagram of a memory system in the present embodiment.

FIG. 2: the system block diagram of the NAND-type flash memory in this embodiment.

FIG. 3: a system block diagram of a NAND memory chip.

FIG. 4: a block diagram of a memory cell array.

FIG. 5: the composition diagram of the storage system in this embodiment.

FIG. 6: the structure of the system controller in this embodiment is schematically illustrated.

FIG. 7: the structure of the memory in this embodiment is schematically illustrated.

FIG. 8: the corresponding diagram of the erase block and the erase count table in this embodiment.

FIG. 9: in this embodiment, the erasure number table and the corresponding diagram of the erasure block set are shown.

FIG. 10: in this embodiment, the first erasure table, the second erasure number table, the third erasure number table and the corresponding diagram of the erasure block are shown.

FIG. 11: in this embodiment, the variation of the first erasure table, the second erasure number table, and the third erasure number table is shown.

FIG. 12: in this embodiment, the third erasure number table corresponds to the erasure block.

FIG. 13: the wear block diagram in this embodiment.

FIG. 14: in this embodiment, the third erasure number table corresponds to the erasure block.

FIG. 15: the control method of the memory in this embodiment is a flowchart.

FIG. 16: a block diagram of a memory system in the present embodiment.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The system described herein includes a novel architecture for controlling a mass storage module that includes flash memory chips. The entire system is shown in a highly schematic form in fig. 1. As with the other block diagrams herein, the elements shown in FIG. 1 are conceptual in nature, illustrating the nature of the interrelationship between these functional blocks and are not intended to represent an actual physical circuit level implementation.

As shown in fig. 1, the present embodiment proposes a memory system including a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device is a nonvolatile memory (non-transitory memory) that does not lose data even when power is turned off, and in this embodiment, the NAND flash memory 120 is illustrated as an example of the nonvolatile semiconductor memory device. In addition, as the storage system, a Solid State Drive (SSD) having a NAND-type flash memory is exemplified.

As shown in fig. 1, the solid state disk 100 is connected to a host device 170 (e.g., an information processing device) via an interface 171 and a power line 172. The host device 170 is configured by, for example, a personal computer, a CPU core, a server connected to a network, or the like. The host device 170 performs data access control on the solid state disk 100, for example, by sending a write request, a read request, and a delete request to the solid state disk 100, performs writing, reading, and deletion of data to the solid state disk 100.

As shown in fig. 1, the solid state disk 100 includes an SSD controller (storage device control unit) 110, a NAND flash memory 120, an interface controller (interface unit) 130, and a power supply unit 140. The SSD controller 110, the interface controller 130, and the NAND-type flash memory 120 are connected to each other by a bus 150.

As shown in fig. 1, the power supply unit 140 is connected to the host device 170 via a power line 172, and receives external power supplied from the host device 170. The power supply unit 140 and the NAND-type flash memory 120 are connected by a power line 161, the power supply unit 140 and the SSD controller 110 are connected by a power line 162, and the power supply unit 140 and the interface controller 130 are connected by a power line 163. The power supply unit 140 boosts and lowers the voltage of the external power supply, generates various voltages, and supplies the voltages to the SSD controller 110, the NAND flash memory 120, and the interface controller 130.

As shown in fig. 1, the interface controller 130 is connected to the host device 170 via the interface 171. The interface controller 130 performs an interface process with the host device 170. As the interface 171, SATA (Serial Advanced technology attachment), PCI Express (Peripheral Component interconnect Express), SAS (Serial Attached SCSI), USB (Universal Serial Bus), or the like can be employed. In one embodiment, the interface 171 is described by using an example of SATA.

As shown in fig. 1, the NAND-type flash memory 120 nonvolatilely stores data. In the physical address space of the NAND-type flash memory 120, an FW area 121 for storing Firmware (FW), a management information area 122 for storing management information, a user area 123 for storing user data, and a filter log area 125 for storing various logs at the time of, for example, a test procedure are secured.

As shown in fig. 1, the SSD controller 110 controls various operations of the solid state disk 100. The SSD controller 110 can realize its functions by a processor, various hardware circuits, and the like that execute firmware stored in the FW area 121 of the NAND-type flash memory 120, and executes data transfer control between the NAND-type flash memory 120 and the host device 170 for various commands such as a write request, a cache refresh request, and a read request from the host device 170, update and management of various management tables stored in the RAM111 and the NAND-type flash memory 120, and filtering processing. The SSD controller 110 receives power from the power supply line 172, reads out firmware from the FW area 121, and performs processing in accordance with the read firmware. The SSD controller 110 has a RAM111 as a buffer area and an operation area, and an ECC (Error Checking and Correcting) circuit 112.

As shown in fig. 1, the RAM111 is composed of a volatile RAM such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), or a nonvolatile RAM such as an MR AM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), a ReRAM (resistive Random Access Memory), or a PRAM (Phase-change Random Access Memory).

As shown in fig. 1, the ECC circuit 112 generates an error correction code for write data at the time of data writing, adds the error correction code to the write data, and transmits the write data to the NAND-type flash memory 120. In addition, the ECC circuit 112 performs error detection (error bit detection) and error correction on read data by using an error correction code included in the read data at the time of data reading. For ECC encoding and ECC decryption by the ECC circuit 112, for example, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Reed-Solomon (RS) code, and a Low-Densi type parity-check (LDPC) code are used. The circuit 112 may also be a Cyclic Redundancy Check (CRC) circuit 112 that uses a CRC code to detect errors.

As shown in fig. 2-3, fig. 2 shows a system block diagram of the NAND-type flash memory 120, and fig. 3 shows a system block diagram of the NAND memory chip 200, and the NAND-type flash memory 120 has more than one NAND memory chip 200.

As shown in fig. 3, the memory cell array 202 is configured by arranging memory cells in a matrix form, in which data can be electrically rewritten. A plurality of bit lines, a plurality of word lines, and a common source line are arranged in the memory cell array 202. Memory cells are arranged in the intersection regions of bit lines and word lines.

As shown in fig. 3, a word line control circuit 205 as a row decoder is connected to a plurality of word lines, and selects and drives the word lines when data is read, written, and erased. The bit line control circuit 203 is connected to a plurality of bit lines, and controls voltages of the bit lines at the time of reading, writing, and erasing of data. The bit line control circuit 203 detects data on the bit line at the time of data reading, and applies a voltage corresponding to the write data to the bit line at the time of data writing. The column decoder 204 generates a column selection signal for selecting a bit line in accordance with an address, and transmits the column selection signal to the bit line control circuit 203.

As shown in fig. 3, read data read from the memory cell array 202 is output to the outside from the data input/output terminal 208 via the bit line control circuit 203 and the data input/output buffer 209. Further, write data inputted from the outside to the data input/output terminal 208 is inputted to the bit line control circuit 203 via the data input/output buffer 209.

As shown in fig. 3, the memory cell array 202, the bit line control circuit 203, the column decoder 204, the data input/output buffer 209, and the word line control circuit 205 are connected to the control circuit 206. The control circuit 206 generates control signals and control voltages for controlling the memory cell array 202, the bit line control circuit 203, the column decoder 204, the data input/output buffer 209, and the word line control circuit 205, based on a control signal input from the outside to the control signal input terminal 207. The NAND memory chip 200 is called a memory cell array control unit (NAND controller) 201 together with a portion other than the memory cell array 202.

As shown in fig. 4, fig. 4 is a block diagram showing the structure of the memory cell array 202. The memory cell array 202 has one or more planes (or partitions). The memory cell array 202 in fig. 4 includes, for example, 2 planes (plane 0 and plane 1). Each plane has a plurality of BLOCKs (BLOCK), each BLOCK (BLOCK) is composed of a plurality of memory cells, and data is erased in units of the BLOCK (BLOCK).

As shown in fig. 5, the present embodiment provides a block diagram of another storage system 30, and the storage system 300 includes at least one controller 310 and a plurality of solid state disks 320. The controller 310 is connected to a host (not shown) through a Storage Area Network (SAN). The controller 310 may be a computing device such as a server, desktop computer, etc. An operating system and an application program are installed on the controller 310. The controller 310 may receive an input output (I/O) request from a host. Controller 310 may also store data carried in the I/O request (if any) and write the data to solid state disk 320. A Solid State Disk (SSD) is a memory with a flash memory chip as a medium, and is also called a Solid State Drive (SSD).

Fig. 5 is an exemplary illustration only, and in practical applications, the storage system may include two or more controllers, each of which has a similar physical structure and function as the controller 310, and the present embodiment does not limit the connection manner between the controllers and between any one of the controllers and the solid state disk 320. As long as the respective controllers, and the respective controllers and the solid state disk 320 can communicate with each other.

As shown in fig. 6, fig. 6 is a diagram illustrating an exemplary configuration of controller 310, and controller 310 includes an interface card 311, a processor 313, and an interface card 314. The interface card 311 is used to communicate with a host, and the controller 310 may receive an operation instruction of the host through the interface card 311. Processor 313 may be a Central Processing Unit (CPU). In an embodiment of the present invention, the processor 313 may be configured to receive an I/O request from a host and process the I/O request. The I/O request may be a write data request or a read data request, and the processor 313 may further send data in the write data request to the solid state disk 320. Processor 313 may also be used to perform system garbage collection operations. The interface card 314 is used for communicating with the solid state disk 320, and the controller 310 may send a request for writing data (including data and a lifecycle level of the data) to the solid state disk 320 through the interface card 314 for storage.

As shown in fig. 6, in the present embodiment, the controller 310 may further include a memory 312. Memory 312 is used to temporarily store data received from a host or read from solid state disk 320. When the controller 310 receives a plurality of write data requests transmitted by the host, data in the plurality of write data requests may be temporarily stored in the memory 312. When the capacity of the memory 312 reaches a certain threshold, the data stored in the memory 312 and the logical address allocated to the data are sent to the solid state disk 320. The solid state disk 320 stores the data. The memory 312 includes volatile memory, flash memory chips, or a combination thereof. Volatile memory is, for example, random-access memory (RAM). The flash memory chip may be a variety of machine-readable media that can store program codes, such as a floppy disk, a hard disk, a Solid State Disk (SSD), an optical disk, and so on. The memory 312 has a power-saving function, which means that when the system is powered off and powered on again, the data stored in the memory 312 will not be lost.

As shown in fig. 6, in the present embodiment, the controller 310 is responsible for identifying the life cycle of the data and dividing the data of different life cycles into several levels. In this embodiment, the data life cycle is related to the modification frequency of the data, and the shorter the data life cycle with the higher modification frequency, the longer the data life cycle with the lower modification frequency. Such as log writes that are large but soon deleted (the retention time in a solid state drive may be only a few minutes), such data is divided into a first level of life cycle. The metadata is stored in the solid state disk for a slightly longer time than the journal, and can be divided into a second level of life cycle. And hot data in the traffic data may be divided into a third level of lifecycle and cold data in the traffic data may be divided into a fourth level of lifecycle. Of course, the embodiment of the present invention does not limit the number of the lifecycle levels, and may only include two levels of lifecycle, or may include three or more levels of lifecycle. Specifically, the controller 310 may preset one or more lifecycle thresholds, and compare the lifecycle of the data to the lifecycle thresholds to determine the lifecycle level to which the data pertains. For example, a first life cycle threshold, a second life cycle threshold, and a third life cycle threshold are preset, wherein the second life cycle threshold is higher than the first life cycle threshold, and the third life cycle threshold is higher than the second life cycle threshold. The data belongs to a first level of lifecycle when its lifecycle is equal to or below a first lifecycle threshold, the data belongs to a second level of lifecycle when its lifecycle is between the first lifecycle threshold and a second lifecycle threshold, the data belongs to a third level of lifecycle when its lifecycle is between the second lifecycle threshold and a third lifecycle threshold, the data belongs to a fourth level of lifecycle when its lifecycle is above the third lifecycle threshold.

As shown in fig. 6, after identifying the lifecycle level of the data, the controller 310 transfers the identified lifecycle level to the solid state disk 320 in the NVMe protocol in a form of a parameter, so that the solid state disk 320 determines the lifecycle level according to the parameter of the lifecycle, and allocates different data storage mode erase blocks for the data of different lifecycle levels.

As shown in fig. 6, it should be noted that the controller 310 belongs to a system controller, and the system controller is a separate device, different from the control chip in the solid state disk. In this embodiment, the control chip of the solid state disk is referred to as a flash memory controller.

As shown in fig. 7, fig. 7 is a schematic structural diagram of a solid state disk. The solid state disk 320 includes a flash memory controller 321 and a plurality of flash memory chips 322. The flash controller 321 is used for executing operations such as a write data request or a read data request sent by the controller 310.

As shown in fig. 7, the flash memory controller 321 includes a Flash Translation Layer (FTL). The flash translation layer is used for storing the corresponding relation between the logical address and the actual address of the data. Therefore, the flash translation layer is used for converting the logical address in the write data request or the read data request sent by the system controller into the actual address of the data in the solid state disk. The logical address of the data is assigned by the system controller, a subset of the logical address intervals of a segment. The logical address of the data includes a start logical address indicating a position of the segment where the data is located and a length representing a size of the data. The actual address of the data may be a physical address of the data in the solid state disk, or may be an address that is visible only to the flash memory controller through virtualization based on the physical address. The virtualized real address is not visible to the system controller.

As shown in fig. 7, solid state disk 320 typically includes one or more flash memory chips 322. Each flash chip 322 includes a number of erase blocks, which may also be referred to as physical blocks or flash blocks. Solid state disk 320 is read or written on a page (page) basis, but an erase operation can only be on an erase block basis, which refers to setting all bits of the block to "1". Prior to erasure, the flash memory controller needs to copy the valid data in this erase block into the blank pages of another block. Valid data in an erase block refers to unmodified data stored in the block, which may be read. Invalid data in an erase block refers to data stored in the block that has been modified, and this portion of data cannot be read.

As shown in FIG. 7, each erase block contains multiple pages (pages). The solid state disk 320 writes data in units of pages when executing a write data request. For example, the controller 310 sends a write data request to the flash controller 321. The write data request includes a logical address of data. The flash controller 321, after receiving the write data request, writes the data into one or more erase blocks sequentially in the order of time of reception. The continuous writing of one or more erase blocks means that the flash controller 321 searches for a blank erase block, writes data into the blank erase block until the blank erase block is filled up, and when the size of the data exceeds the capacity of the erase block, the flash controller 321 searches for the next blank erase block again and continues writing. And the flash translation layer establishes and stores the corresponding relation between the logical address and the actual address of the page written with the data. When the controller 310 sends a read data request to the flash controller 321, requesting to read the data, the read data request includes the logical address. The flash controller 321 reads the data according to the logical address and the corresponding relationship between the logical address and the real address, and sends the data to the controller 310.

As shown in fig. 7, a memory cell (cell) is the minimum unit of operation of a page, and one memory cell corresponds to one floating gate transistor, which can store 1 bit (bit) or more bits of data, depending on the type of flash memory. Memory cells on a page share a word line. The memory cell includes a control gate and a floating gate, which is a cell that actually stores data. Data is stored in the memory cell in the form of an electrical charge (electric charge). How much charge is stored depends on the voltage applied to the control gate, which controls whether charge is pushed into or released from the floating gate. And the representation of the data is represented by whether the voltage of the stored charge exceeds a particular threshold. Writing data to the floating gate is accomplished by applying a voltage to the control gate such that sufficient charge is stored in the floating gate above a threshold value, indicating a 0. An erase operation on a flash memory is to discharge the floating gate so that the charge stored in the floating gate is below the threshold, indicating a 1.

As shown in fig. 7, a flash memory type storing one bit of data in each memory cell is called a Single-level cell (SLC), and a floating gate of the SLC has a voltage threshold, and thus has two states, i.e., 0 and 1, and can store one bit of data. Single layer cell flash memory has the advantages of high write speed, low power consumption, longer battery life, and therefore faster transfer speed and longer life. A Multi-level cell (MLC) is a memory cell that uses multiple voltage thresholds, allowing the same number of transistors to store more bits. In single-layer cell technology, each memory cell can only be in one of two states, while MLCs store four possible states in each memory cell (MLCs have four states 00, 01, 10, 11), and thus can store two bits per memory cell. Compared with the SLC, the MLC has higher error rate, shorter service life and lower cost. Some solid state drives use a portion of the dies in MLC flash to emulate single bit SLC flash, thereby providing higher write speeds. In addition, a flash memory storing three bits per cell is called a Triple-level cell (TLC), and the TLC has 8 states. The disadvantages of MLC are also present and more pronounced on TLC, but TLC also benefits from higher storage density and lower cost. In addition, the flash memory type also includes a four-level cell (QLC) and other multi-level cells, and the flash memory type is not limited in the embodiments of the present invention.

In order to compensate the defects of TLC in writing performance and service life, the present embodiment adopts a storage architecture of SLC and TLC dual mode. This embodiment refers to the erase blocks set to SLC mode as a first set of erase blocks and the erase blocks set to TLC mode as a second set of erase blocks. In various embodiments, the first set of erase blocks includes a fewer number of erase blocks than the second set of erase blocks.

In addition, the embodiment also supports a solid state disk comprising two or more flash memory types. For example, the solid state disk provided in this embodiment may include two types of memory cells set as MLC and TLC, may also include two types of memory cells set as MLC and QLC, may also include two types of memory cells set as QLC and TLC, may also include three types of memory cells set as MLC, TLC and QLC, or other combinations.

As shown in fig. 8, fig. 8 shows an erase record table formed in the memory chip 222 in the flash memory controller 321, where "0" in the erase count table indicates that the corresponding erase block is not erased, and "1" in the erase count table indicates that the corresponding erase block is not erased, and is erased once, for example, erase block 1 is erased, and erase block 3 is erased. In this embodiment, if the number of times of erasing the erase block 1 is larger, it indicates that the erase block 1 is used all the time, and those corresponding to the value 0 are not erased all the time, so that the wear of each erase block is unbalanced, and the service life of the memory is shortened.

As shown in fig. 9, in order to achieve wear leveling of each erase block, improve the service life of the memory, and simultaneously improve the total written byte amount of the memory, the embodiment first divides the erase blocks into a plurality of erase block sets, for example, erase blocks 0 to 5 are set as a first erase block set, erase blocks 6 to 11 are set as a second erase block set, and some erase blocks may also be set as a third erase block set. It should be noted that the first erase block set is set to be a Single-level cell (SLC), for example, and the second erase block set is set to be at least one of a Multi-level cell (MLC), a Triple-level cell (TLC), or a Quad-level cell (QLC), for example, and this embodiment will be described with the second erase block set to be a Triple-level cell as an example. When the flash memory chip is storing data, some of the erase blocks are used as single-layer units in the first use, and when the flash memory chip is storing data next time, the erase blocks are used as three-layer units, for example, the erase block 4 is a single-layer unit when the erase block 4 is storing data for the first time, and the erase block 4 is used as a three-layer unit when the erase block 4 is storing data for the second time, so that the erase block 4 can be set to be a layer-second erase block set. It should be noted that, when the number of times of erasing all the erase blocks is 0, the second erase block set does not exist, and when all the erase blocks are erased, the second erase block set is formed. When manufacturing the memory, the memory cell can be set to SLC mode or TLC mode by a set feature (set feature) command.

As shown in fig. 9, the flash memory chip includes a plurality of erase blocks, which may be set to SLC or MLC or TLC or QLC. The flash controller 321 may divide the plurality of erase blocks into at least two sets according to the data life cycle, and particularly, if the data life cycle has two levels, divide the plurality of erase blocks into two sets. If the data's lifecycle level has three levels, then the erase blocks are divided into three sets, and so on. In this embodiment, taking two lifecycle levels as an example, the erase blocks are divided into a first erase block set and a second erase block set. As shown in fig. 9, the erase blocks 0 to 5 are designed as a first set of erase blocks, the flash controller 321 sets, for example, the erase blocks in the first set of erase blocks to SLC mode, the erase blocks 6 to 11 are designed as a second set of erase blocks, and the flash controller 321 sets, for example, the erase blocks in the second set of erase blocks to TLC mode. The number of times that erase block 1 in the first set of erase blocks is erased is 1, indicating that erase block 1 was erased.

This embodiment provides a memory calculation method for calculating a solid state disk, assuming that the solid state disk includes M surfaces (Plan e), each surface includes N erase blocks (blocks), the number of erase times of each erase block is O, each erase block includes P pages (pages), each page includes L channels (channels), each channel (channel) includes K memory cells (cells), the page size of each page is H, the page size H is in units of bytes, and a write amplification factor (write amplification, WA) of the solid state disk is W, then a memory of the solid state disk is (the number of surfaces is the number of erase blocks, the number of erase times of erase blocks is the number of pages is the number of channels)/the write amplification factor.

For example, assume that the solid state disk includes 2 planes, including 1500 erase blocks, including 256 pages, each page having a page size of 16k, including 4 channels, including 1 memory cell, and a write amplification factor of 1.5, where 50 erase blocks are designed as a first set of erase blocks and 1450 erase blocks are designed as a second set of erase blocks. The erase count of the first erase block is 30000, the erase count of the second erase block is 3000, and the first erase block set is, for example, SLC mode, and the memory of the solid state disk is 16 × 2 × 256 × 4 × 50 × 30000/(1.5 × 1024) ═ 30.5T. The second erase block set is, for example, in a TLC mode, and the solid state disk is 16 × 2 × 256 × 4 × 5(1500-50) × 3000/(1.5 × 1024) ═ 265T. Namely, the memory of the solid state disk is 30.5T, which is the total byte writing amount of the solid state disk.

As shown in fig. 10, in the present embodiment, first, assuming that the flash memory chip includes 18 erase blocks, i.e., erase block 0 to erase block 17, the flash controller 321 first designs the erase block 0 to erase block 17 into a first erase block set, i.e., the first erase block set is designed to be SLC mode, as shown in fig. 10, the first erase count table gives the erase count of the erase blocks 0 to 17, for example, the erase count of the erase block 4 is 1, which indicates that the erase block 4 is erased 1 time, and the erase count of the erase block 6 is 2, which indicates that the erase block 6 is erased 2 times. Each erase block is erased once, the number of times of erasing the erase block is increased once, and the first erase number table is sequentially arranged according to the sequence of the erase blocks. In the next data storage, the flash controller 321 designs part of the erase blocks in the first erase block into a second erase block set, for example, the erase blocks 5 to 8 are designed into a second erase block set, which is designed into a TLC mode, in which the erase count of the erase block 5 is 1, which indicates that the erase block 5 has been erased 1 time, and the second erase count table is arranged in order of the erase blocks. After the first erasure count table and the second erasure count table are formed, the flash memory controller 321 forms a third erasure count table according to the first erasure count table and the second erasure count table. The third erasure number table is an erasure number ratio of the erasure block belonging to the first erasure block set and the second erasure block set, for example, the erasure blocks 5 to 8 belong to the first erasure block set and the second erasure block set, and then a third erasure number table is formed according to the erasure number of the erasure blocks 5 to 8 in the first erasure number table and the erasure number in the second erasure number table, for example, the value of the erasure block 5 in the third erasure number table is 2, and the value of the erasure block 7 is 3. The flash controller 321 may design the erase block to be SLC mode or TLC mode according to the number of the third erase count table.

As shown in fig. 11, assuming that the flash memory chip includes 12 erase blocks, i.e., erase block 0 to erase block 11, when the erase blocks are not written with data, the erase count table of each erase block is 0, i.e., the numbers in the first erase count table are all 0. When the erase blocks 0 to 11 store data, the erase blocks 0 to 11 are in SLC mode, for example, and when all the erase blocks are written with data, the values in the first erase count table are changed, for example, the erase count of the erase block 0 is changed to 1, the erase count of the erase block 4 is changed to 2, the erase of the erase blocks 6 to 11 is changed to 1, and each time the erase block is erased, the value of the erase block in the first erase count table is added with 1. When the erase blocks 4 to 5 are designed in the TLC mode, the numbers of the erase blocks 4 to 5 in the second erase count table are 1, the erase blocks 0 to 3, and the erase blocks 6 to 11 in the second erase count table are 0. And after the first erasure number table and the second erasure number table are formed, updating the third erasure number table in real time.

As shown in fig. 12, it can be seen from the third erase count table that erase block 0 to erase block 11 may belong to both the first erase block set and the second erase block set, i.e., erase block 0 to erase block 11 may be designed as SLC or TLC. If the flash controller 321 needs to store data in SLC, a minimum value smaller than the threshold value can be found in the third erasure number table, and a corresponding erasure block can be found according to the minimum value, and then the data can be stored in the erasure block. Assuming that the threshold of the erase count is 8, the minimum value in the third erase count table is 1, and the erase block with the minimum value of 1 is erase block 0, the flash memory controller may store the data in erase block 0, and the erase block 0 is regarded as SLC, and the erase count value of erase block 0 needs to be updated in the first erase count table. If the flash controller 321 needs to store data in TLC, it may find a maximum value greater than the threshold in the third erasure count table, find a corresponding erasure block according to the maximum value, and then store the data in the erasure block. Assuming that the threshold of the erase count is 8, the maximum value in the third erase count table is 11, and the erase block with the maximum value of 11 is the erase block 8, the flash memory controller may store the data in the erase block 8 while the erase block 8 is regarded as TLC, and update the erase count value of the erase block 8 in the second erase count table.

It should be noted that, in this embodiment, the range of the threshold is related to the total write amount of the storage device, for example, when the total write amount of the storage device is 64T, the first erase count in the first erase block set is, for example, 2097 times, the second erase count in the second erase block set is, for example, 903 times, the range of the threshold is, for example, 2094/903, that is, the range of the threshold is, for example, less than 3.

As shown in fig. 13-14, in this embodiment, when the flash controller 321 needs to store data, the flash controller 321 first checks the values in the third erasure number table, and if all the values in the third erasure number table are greater than the threshold, it means that the erasure blocks 0 to 11 are regarded as SLCs many times, so the flash controller stores the garbage collection function, i.e. the data in SLCs in TLC. As described in fig. 14, assuming that the threshold value of the number of times of erasing is 22, the number of times of erasing of the erase blocks 0 to 11 is larger than 22, and thus the data in the erase blocks 0 to 11 is stored in TLC by SLC.

As shown in fig. 13-14, in the embodiment, when the flash controller 321 checks that the value of the third erase count table is different from the threshold value of the erase count, the flash controller 321 needs to check the values of the erase blocks 0 to 11 in the first erase count table and the second erase count table, and if the values in the first erase count table are both greater than a threshold value, the flash controller 321 performs SLC wear leveling so that the value in the third erase count table is close to the threshold value of the erase count. If the values in the second erasure count table are all larger than a threshold value, the flash controller 321 performs TLC wear leveling so that the values in the third erasure count table are close to the threshold value of the erasure count. As shown in fig. 14, assuming that the threshold value in the third erasure number table is 27, the values of the erasure block 0, the erasure block 1, the erasure block 3 and the erasure block 7 in the third erasure number table are less than 27, therefore the flash controller 321 needs to check the erasure numbers of the erasure block 0, the erasure block 1, the erasure block 3 and the erasure block 7 in the first erasure number table, if the erasure numbers of the erasure block 0, the erasure block 1, the erasure block 3 and the erasure block 7 in the first erasure number table are greater than the threshold value, the flash controller 321 executes SLC wear leveling so that the values of the erasure block 0, the erasure block 1, the erasure block 3 and the erasure block 7 in the third erasure number table are close to the erasure 27. As shown in fig. 14, the values of the erase block 2, the erase block 4, the erase block 5, the erase block 6, the erase block 8 to the erase block 11 in the third erase count table are greater than 27, so that the flash memory 221 needs to check the number of times the erase block 2, the erase block 4, the erase block 5, the erase block 6, the erase block 8 to the erase block 11 in the second erase count table, and if the number of times the erase block 2, the erase block 4, the erase block 5, the erase block 6, the erase block 8 to the erase block 11 in the second erase count table is greater than a threshold value, the flash controller 321 performs TLC wear leveling so that the values of the erase block 2, the erase block 4, the erase block 5, the erase block 6, the erase block 8 to the erase block 11 in the third erase count table are close to 27. Through the two steps, the erase blocks 0 to 11 can be close to the threshold value in the third erasure number table. Meanwhile, by adjusting the threshold value, the memory of the flash memory chip can be set, namely the total byte writing amount of the flash memory chip is set.

It should be noted that, in this embodiment, assuming that the average of the erase counts of the erase blocks in the first erase block set is M, and the erase count of any erase block in the first erase block set is greater than (M + N) or less than (M-N), the flash memory controller 321 performs wear leveling on the erase block, where N is an integer greater than 0 and less than M. For example, assuming that the average value of the erase blocks in the first erase block set is M100 and N50, when the erase count of the k-th erase block in the first erase block set is greater than 150 or less than 50, the flash controller 321 performs wear leveling on the k-th erase block.

It should be noted that, in this embodiment, assuming that the average of the erase counts of the erase blocks in the second erase block set is P, and the erase count of any erase block in the second erase block set is greater than (P + Q) or less than (P-Q), the flash memory controller 321 performs wear leveling on the erase block, where Q is an integer greater than 0 and less than P. For example, assuming that the average value of the respective erase blocks in the second erase block set is P-80 and N-20, when the number of times of erasing the h-th erase block in the second erase block set is greater than 100 or less than 60, the flash controller 321 performs wear leveling on the h-th erase block.

As shown in fig. 15, the present embodiment further provides a method for controlling a memory, including,

s1: dividing the erasing blocks into a first erasing block set and a second erasing block set by a flash memory controller;

s2: the flash memory controller forms a first erasure order table, a second erasure order table and a third erasure order table;

s3: and the flash memory controller designs the erasing blocks to belong to the first erasing block set or the second erasing block set according to the values in the third erasing times table and stores the erasing blocks.

In step S1, the flash memory chip includes a plurality of erase blocks, which may be configured as a layer SLC or MLC or TLC or QLC, and the flash controller 321 may divide the plurality of erase blocks into at least two sets according to the data life cycle, specifically, if the data life cycle has two levels, the erase blocks are divided into two sets. If the data's lifecycle level has three levels, then the erase blocks are divided into three sets, and so on. In this embodiment, taking two lifecycle levels as an example, the erase blocks are divided into a first erase block set and a second erase block set. The erase blocks in the first set of erase blocks may be set to SLC mode and the erase blocks in the second set of erase blocks in combination may be set to TLC mode.

In step S2, after the first erase block set and the second erase block set are formed, the flash controller 321 forms a first erase count table, a second erase count table and a third erase count table. The first erasure number table is used for recording the erasure number of each erasure block in the first erasure block set and arranging the erasure number in sequence according to the sequence of each erasure block, and the second erasure number table is used for recording the erasure number of each erasure block in the second erasure block set and arranging the erasure number in sequence according to the sequence of each erasure block. When the plurality of erase blocks are set to SLC mode in the first storage and set to TLC mode in the second storage, the flash controller forms a third erase count table for recording the ratio of the number of times the plurality of erase blocks are erased in the first erase count table to the number of times the plurality of erase blocks are erased in the second erase count table, and the specific implementation steps can be seen in fig. 10.

In step S3, when the flash controller 321 receives the data, the flash controller 321 first determines whether the erase block belongs to the first erase block set or the second erase block set according to the value in the third erase count table and the value in the third erase count table, and if the erase block belongs to the first erase block set, the data is written into the target erase block by using a single-level cell (e.g. SLC) technique. If the erase block belongs to the second set of erase blocks, then data is written to the target erase block using multi-level cell technology (e.g., TLC).

According to the above method, assuming that the memory of the solid state disk is designed to be 64T, the erase count of the first erase block set is 64 × 1024 × 1.5/(16 × 2 × 256 × 4 × 1500) ═ 2097, that is, the erase count of the erase block in the first erase block set is 2097, and assuming that the erase count of the erase block in the second erase block set is 3000, the memory of the solid state disk is 16 × 2 × 256 × 3 × 4 × 1500 (3000-. Therefore, by the method, the erasing times of the second erasing block set are divided into the erasing times of the first erasing block set, so that the memory of the solid state disk can be improved.

As shown in fig. 16, the present embodiment provides a storage system 400, and the storage system 400 may include a host 410 and a data storage device 420 communicating commands and/or data with the host 410 through an interface 411. Storage system 400 may be implemented as a Personal Computer (PC), workstation, data center, internet data center, storage area network, Network Attached Storage (NAS), or mobile computing device, although the inventive concepts are not limited to these examples. The mobile computing device may be implemented as a laptop computer, a cellular phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), a digital still camera, a digital video camera, a Portable Multimedia Player (PMP), a personal navigation device or Portable Navigation Device (PND), a handheld game console, a Mobile Internet Device (MID), a wearable computer, an internet of things (IoT) device, an internet of things (IoE) device, a drone, or an electronic book, although the inventive concepts are not limited to these examples.

As shown in fig. 16, the interface 411 may be a Serial Advanced Technology Attachment (SATA) interface, a SATA express (SATA ae) interface, a SAS (serial attached Small Computer System Interface (SCSI)), a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an Advanced Host Controller Interface (AHCI), or a multimedia card (MMC) interface, but is not limited thereto. The interface 411 may transmit an electrical signal or an optical signal. The host 410 may control data processing operations (e.g., write operations or read operations) of the data storage device 420 via the interface 411. Host 410 may refer to a host controller.

As shown in fig. 16, the data storage device 420 may be a flash-based memory device, but is not limited thereto. The data storage device 420 may be implemented as an SSD, an embedded SSD (essd), a universal flash memory (UFS), an MMC, an embedded MMC (emmc), or a managed NAND, but the inventive concept is not limited to these examples. A flash-based memory device may include an array of memory cells. The memory cell array may include a plurality of memory cells. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. A three-dimensional memory cell array may be monolithically formed at one or more physical levels in a memory cell array having an active region disposed on or above a silicon substrate, and may include circuitry involved in the operation of the memory cells. The circuitry may be formed in, on, or over a silicon substrate. The term "monolithic" means that the layers of each level in the array are deposited directly on the layers of the lower levels in the array. A three-dimensional memory cell array can include vertical NAND strings oriented vertically such that at least one memory cell is placed on or over another memory cell. The at least one memory cell may include a charge trapping layer.

As shown in fig. 16, the data storage device 420 may include a controller 421, a buffer 422, and at least one memory cell array 423, and the controller 421 may control transmission or processing of commands and/or data between the host 410, the buffer 422, and the memory cell array 423. The controller 421 may be implemented in an Integrated Circuit (IC) or a system on a chip.

In some embodiments, a plurality of memory cell arrays 423 may also be included within the data storage device 420, and the plurality of memory cell arrays 423 may be collectively referred to as a memory cell cluster.

As shown in fig. 16, in the present embodiment, the data storage device 420 may be the memory described above, and a control method of the data storage device 420 is described with reference to corresponding contents in fig. 8 to fig. 15, which is not described herein.

The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.

Claims

1. A memory, comprising,

2. The memory according to claim 1, wherein when the plurality of first memory cells are subjected to the erasing step, the first erase count table is formed, and the first erase count table is arranged in an order of the plurality of first memory cells.

3. The memory according to claim 1, wherein when the plurality of second memory cells are subjected to the erasing step, the second erasure number table is formed, the second erasure number table being arranged in an order of the plurality of second memory cells.

4. The memory of claim 1, wherein when a plurality of memory cells in the memory cell array belong to the first memory cell and the second memory cell, the erase count of the plurality of memory cells is found in the first erase count table, and the erase count of the plurality of memory cells is found in the second erase count table.

5. The memory of claim 4, wherein the third erase count table is a ratio of the number of times the plurality of memory cells are erased in the first erase count table to the number of times the plurality of memory cells are erased in the second erase count table, and wherein the third erase count is arranged in the order of the plurality of memory cells.

6. The memory according to claim 1, wherein when the minimum value in the third erasure count table is smaller than a threshold value, the plurality of memory cells are treated as the first memory cells while increasing the number of times of erasure of the plurality of memory cells in the first erasure count table and updating the third erasure count table.

7. The memory according to claim 1, wherein when the maximum value in the third erasure number table is larger than a threshold value, the plurality of memory cells are treated as the second memory cells while increasing the number of times of erasure of the plurality of memory cells in the second erasure number table and updating the third erasure number table.

8. The memory of claim 1, wherein when all values in the third erasure count table are greater than a threshold value, the data in the first memory location is moved into the second memory location.

9. The memory of claim 1, wherein the first memory cell comprises a single layer memory cell and the second memory cell comprises at least one of a multi-layer memory cell, a tri-layer memory cell, and a quad-layer memory cell.

10. A method for controlling a memory includes,

11. A storage system, comprising,

a host;

a memory connected to the host, wherein the memory comprises,