CN111293080B - Display panel and preparation method thereof - Google Patents
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- CN111293080B CN111293080B CN202010099737.9A CN202010099737A CN111293080B CN 111293080 B CN111293080 B CN 111293080B CN 202010099737 A CN202010099737 A CN 202010099737A CN 111293080 B CN111293080 B CN 111293080B
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- 238000002360 preparation method Methods 0.000 title abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000005530 etching Methods 0.000 claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 139
- 239000011229 interlayer Substances 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 13
- 230000000295 complement effect Effects 0.000 claims description 12
- 238000004380 ashing Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000002834 transmittance Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000945 filler Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The application discloses a preparation method of a display panel and the display panel, wherein the preparation method is characterized in that a light resistance layer on a substrate is subjected to exposure treatment through a half-color light modulation cover so as to form a first area for preparing a first hole in a display area of the display panel and a second area for preparing a second hole in a non-display area of the display panel; after removing part of the photoresist of the first region and all of the photoresist of the second region, simultaneously etching the first residual photoresist of the first region and the second region by using an etching process to correspondingly obtain a second residual photoresist and a second main hole; after removing the second remaining photoresist; and etching the first region and the second region simultaneously, and correspondingly obtaining a first hole and a second slave hole. The second hole comprises a second main hole and a second auxiliary hole, and the depth of the second hole is larger than that of the first hole, so that the manufacturing process is simplified, the equipment investment is reduced, the production cost is reduced, the preparation requirements of holes in different areas of the display panel when the holes have different depths can be met, and the equipment utilization rate and the competitiveness of products are improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a preparation method of a display panel and the display panel.
Background
Polysilicon has a better electron migration rate, and is applied to the technical field of display by display technology developers, and in a backboard manufactured by adopting low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS) technology, the volume of a thin film transistor is smaller, and the resolution of a correspondingly obtained panel is higher. However, in the LTPS process, the source/drain holes of the display area and the deep holes of the non-display area are usually patterned by multiple masks, so that the number of masks used in the manufacturing process of the display panel is large.
Disclosure of Invention
The embodiment of the application provides a preparation method of a display panel and the display panel, which can reduce light covers used in the preparation process of the display panel.
The embodiment of the application provides a preparation method of a display panel, which comprises the following steps:
S10: providing a substrate with a first hole and a second hole to be formed, wherein the substrate comprises a first area corresponding to the first hole and a second area corresponding to the second hole, the first area is positioned in a display area of the display panel, and the second area is positioned in a non-display area of the display panel;
s20: forming a photoresist layer covering the substrate;
S30: providing a half-tone light modulation cover, and performing exposure treatment on the photoresist layer on the substrate by using the half-tone light modulation cover;
S40: developing the substrate to remove part of the photoresist corresponding to the first region to obtain first residual photoresist corresponding to the first region, and removing all the photoresist corresponding to the second region;
s50: removing part of the photoresist of the first residual photoresist to obtain second residual photoresist corresponding to the first region, and etching the second region to obtain a second main hole with etching depth of a first depth in the second region;
S60: removing the second residual photoresist;
S70: etching the first region and the second region to obtain the first hole in the first region and obtain a second slave hole with etching depth of a second depth in the second region;
Wherein the second hole comprises the second master hole and the second slave hole, and the depth of the second hole is larger than that of the first hole.
In some embodiments, the halftone mask includes a light-transmitting region, a semi-transmitting region and a light-shielding region, in the step S30, the light-transmitting region is aligned with a portion of the area in the non-display region to form the second region, the semi-transmitting region is aligned with a portion of the area in the display region to form the first region, and the light-shielding region is aligned with an area of the display region other than the first region and an area of the non-display region other than the second region.
In some embodiments, the substrate comprises:
A substrate;
An active layer formed in the display region and located on at least one side of the substrate;
the first metal layer is at least positioned on one side of the active layer, and comprises a grid electrode arranged corresponding to the active layer;
the grid insulation layer is formed in the display area and the non-display area and is positioned between the active layer and the first metal layer;
an interlayer dielectric layer covering the gate electrode and the gate insulating layer;
Wherein the first hole penetrates through the interlayer dielectric layer and the gate insulating layer and is communicated with the active layer, and the second hole penetrates through the interlayer dielectric layer and the gate insulating layer and is communicated with the substrate.
In some embodiments, the active layer includes a channel region and doped regions located on both sides of the channel region; the channel region is arranged in alignment with the gate, the first hole is communicated with the doped region of the active layer, and the depth of the first hole in the doped region is greater than or equal to 0nm and less than or equal to 50nm.
In some embodiments, the second hole has a depth of greater than or equal to 0nm and less than or equal to 500nm in the substrate.
In some embodiments, the depth of the second main hole is less than or equal to the sum of the thicknesses of the interlayer dielectric layer and the gate insulating layer.
In some embodiments, the difference between the width of the second master hole and the width of the second slave hole is less than or equal to 4 μm.
In some embodiments, the second main hole includes a main bottom wall and a main side wall connected to the main bottom wall, a first included angle is formed between the main bottom wall and the main side wall, a common edge between an adjacent complement angle of the first included angle and the first included angle is the main side wall, and the adjacent complement angle of the first included angle is greater than or equal to 30 ° and less than or equal to 70 °.
In some embodiments, the second slave aperture includes a slave bottom wall and a slave side wall connected to the slave bottom wall, the slave bottom wall and the slave side wall having a second included angle therebetween, a common edge between an adjacent complement angle of the second included angle and the second included angle being the slave side wall, the adjacent complement angle of the second included angle being greater than or equal to 30 ° and less than or equal to 70 °.
The embodiment of the application also provides a display panel manufactured by adopting the manufacturing method of the display panel.
The preparation method of the display panel and the display panel provided by the embodiment of the application comprise the following steps: providing a substrate with a first hole and a second hole to be formed, wherein the substrate comprises a first area corresponding to the first hole and a second area corresponding to the second hole, the first area is positioned in a display area of the display panel, and the second area is positioned in a non-display area of the display panel; forming a photoresist layer covering the substrate; providing a half-tone light modulation cover, and performing exposure treatment on the photoresist layer on the substrate by using the half-tone light modulation cover; developing the substrate to remove part of the photoresist corresponding to the first region to obtain first residual photoresist corresponding to the first region, and removing all the photoresist corresponding to the second region; removing part of the photoresist of the first residual photoresist to obtain second residual photoresist corresponding to the first region, and etching the second region to obtain a second main hole with etching depth of a first depth in the second region; removing the second residual photoresist; and etching the first region and the second region, obtaining the first hole in the first region, and obtaining a second slave hole with the etching depth of a second depth in the second region. Wherein the second hole comprises the second master hole and the second slave hole, and the depth of the second hole is larger than that of the first hole. By adopting the preparation method, the first holes positioned in the display area and the second holes positioned in the non-display area can be prepared through 1 photomask, so that the photomask used in the preparation process of the display panel is reduced.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1A is a flowchart of a preparation of a display panel according to an embodiment of the present application;
FIGS. 1B to 1H are schematic views illustrating a process of manufacturing a display panel using the manufacturing method shown in FIG. 1A;
FIG. 1I is an enlarged view of a portion of FIG. 1H at A;
FIGS. 1J to 1K are schematic views illustrating a process of preparing a second slave hole when a photoresist layer is backed up;
FIG. 2 is a schematic structural diagram of a substrate according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
Specifically, please refer to fig. 1A, which is a flowchart illustrating a preparation process of a display panel according to an embodiment of the present application; as shown in fig. 1B to 1H, a schematic process of preparing a display panel by the preparation method shown in fig. 1A is shown;
the preparation method of the display panel comprises the following steps:
S10: providing a substrate 100 with a first hole 101 and a second hole 102 to be formed, wherein the substrate 100 comprises a first area 101a corresponding to the first hole 101 and a second area 102a corresponding to the second hole 102, the first area 101a is positioned in a display area 100a of the display panel, and the second area 102a is positioned in a non-display area 100B of the display panel, as shown in fig. 1B;
S20: forming a photoresist layer 103 covering the substrate 100 as shown in fig. 1C;
S30: providing a half-tone light-adjusting mask 104, and performing exposure treatment on the photoresist layer 103 on the substrate 100 by using the half-tone light-adjusting mask 104, as shown in fig. 1D;
s40: developing the substrate 100 to remove a portion of the photoresist corresponding to the first region 101a to obtain a first remaining photoresist 1031 corresponding to the first region 101a, and removing all of the photoresist corresponding to the second region 102a, as shown in fig. 1E;
s50: removing a portion of the first remaining photoresist 1031 to obtain a second remaining photoresist 1032 corresponding to the first region 101a, etching the second region 102a to obtain a second main hole 1021 having an etching depth of a first depth h21 in the second region 102a, as shown in fig. 1F;
s60: removing the second remaining photoresist 1032 as shown in fig. 1G;
S70: etching the first region 101a and the second region 102a to obtain the first hole 101 in the first region 101a, and obtaining a second slave hole 1022 having an etching depth of a second depth H22 in the second region 102a, as shown in fig. 1H;
The second hole 102 includes the second master hole 1021 and the second slave hole 1022, and the depth h2 of the second hole 102 is greater than the depth h1 of the first hole 101, so as to reduce the number of photomasks used in the manufacturing process of the display panel, reduce the production cost, and improve the competitiveness of the product.
The structure of the halftone mask 104 may be different depending on the photoresist material used for the photoresist layer 103.
Specifically, referring to fig. 1D, if the photoresist layer 103 is a positive photoresist, the halftone mask 104 includes a transparent region 1041, a semi-transparent region 1042, and a light-shielding region 1043, in the step S30, the transparent region 1041 is aligned with a portion of the non-display region 100b to form the second region 102a, the semi-transparent region 1042 is aligned with a portion of the display region 100a to form the first region 101a, and the light-shielding region 1043 is aligned with a portion of the display region 100a except the first region 101a and a portion of the non-display region 100b except the second region 102 a.
If the photoresist layer 103 is a negative photoresist, the halftone mask 104 still includes a transparent region 1041, a semi-transparent region 1042, and a light-shielding region 1043, and in the step S30, the light-shielding region 1043 is aligned with a portion of the area in the non-display region 100b to form the second region 102a, the semi-transparent region 1042 is aligned with a portion of the area in the display region 100a to form the first region 101a, and the transparent region 1041 is aligned with an area of the display region 100a except the first region 101a and an area of the non-display region 100b except the second region 102 a.
The transmittance of the semi-transparent region 1042 of the semi-color light modulator 104 is 5% -50%; further, the transmittance of the semi-transparent region 1042 is 20% -40%, the transmittance of the semi-transparent region 1042 can be calculated according to parameters such as the exposure light source and the thickness of the photoresist film, and the like, and will not be described herein.
According to the preparation method of the display panel, the half-tone photomask 104 is adopted to expose the photoresist layer 103 of the substrate 100, and the etching process is matched to prepare the first hole 101 and the second hole 102, so that the original 3-photomask process is simplified into 1-photomask process, the production cost is reduced, the investment of an exposure machine and dry etching equipment is reduced, and the utilization rate of the equipment is improved.
With continued reference to fig. 1E and 1F, in the step S50, the thickness P2 of the second residual photoresist 1032 is equal to the difference between the thickness P of the first residual photoresist 1031 and the etching thickness P1 of the first residual photoresist 1031; further, the etching thickness P1 of the first residual photoresist 1031 is equal to a product of the etching rate E1 of the first residual photoresist 1031 and the first etching time t1 for etching the second region 102a to form the second main hole 1021; namely: p2=p-P1; p1=e1×t1.
In the step S50 and the step S70, the second region 102a and the first region 101a are etched by a dry etching process, and one or more of CxFy, SFx, cxHyFz, O, H2, and Ar are used as etching gases.
In the step S60, ashing is performed to remove the second residual photoresist 1032, and oxygen or a mixed gas containing oxygen is used as the ashing gas to perform the ashing on the second residual photoresist 1032, where the ashing time t3 is equal to the ratio of the thickness P2 of the second residual photoresist 1032 to the ashing rate E2 of the second residual photoresist 1032; namely: t3=p2/E2.
Referring to fig. 1I, which is a partial enlarged view of a portion a in fig. 1H, since the second hole 102 is etched in two steps, a step is formed between the second master hole 1021 and the second slave hole 1022, and in order to reduce the manufacturing defect, a difference between a width of the second master hole 1021 and a width of the second slave hole 1022 is less than or equal to 4 μm; further, a difference between a minimum width of the second master hole 1021 and a maximum width of the second slave hole 1022 is less than or equal to 4 μm, that is, a width w of the step is less than or equal to 2 μm.
Since the photoresist layer 103 is affected by factors such as etching gas or energy during etching, the photoresist may have a backward phenomenon, which affects etching accuracy and seriously affects production yield, so that to improve the phenomenon, the included angle between the bottom wall and the side wall of the second hole 102 is controlled; specifically, the second main hole 1021 includes a main bottom wall 1021a and a main side wall 1021b connected to the main bottom wall 1021a, a first included angle α is formed between the main bottom wall 1021a and the main side wall 1021b, a common side between an adjacent complement angle of the first included angle α and the first included angle α is the main side wall 1021b of the second main hole 1021, and the adjacent complement angle of the first included angle α is greater than or equal to 30 ° and less than or equal to 70 °; the second slave hole 1022 includes a slave bottom wall 1022a and a slave side wall 1022b connected to the slave bottom wall 1022a, the slave bottom wall 1022a and the slave side wall 1022b have a second included angle β therebetween, and a common edge between an adjacent complement angle of the second included angle β and the second included angle β is the slave side wall 1022b of the second slave hole 1022, and the adjacent complement angle of the second included angle β is greater than or equal to 30 ° and less than or equal to 70 °.
In addition, under the influence of the back-off phenomenon of the photoresist layer 103 during etching, when the second slave hole 1022 is formed, the second master hole 1021 forms an arc slope at the back-off position of the photoresist layer 103, that is, as shown in fig. 1J-1K, a schematic process of forming the second slave hole when the back-off phenomenon of the photoresist layer occurs, and when the second residual photoresist 1032 is removed from the first region 101a, the back-off phenomenon of the photoresist layer 103 at two sides of the second region 102a occurs, as shown in fig. 1J; in preparing the second main hole 1022, since the photoresist layer 103 is backed up, the second main hole 1021 forms an arc slope at the point where the photoresist layer 103 is backed up, as shown in fig. 1K.
With continued reference to fig. 1B to 1H, the substrate 100 includes:
a substrate 201;
an active layer 202 formed on the display region 100a and located on at least one side of the substrate 201;
a first metal layer 203 at least located at one side of the active layer 202, where the first metal layer 203 includes a gate electrode 2031 disposed corresponding to the active layer 202;
a gate insulating layer 204 formed in the display region 100a and the non-display region 100b and located between the active layer 202 and the first metal layer 203;
an interlayer dielectric layer 205 covering the gate electrode 2031 and the gate insulating layer 204;
Wherein the first hole 101 penetrates the interlayer dielectric layer 205 and the gate insulating layer 204 and communicates with the active layer 202, and the second hole 102 penetrates the interlayer dielectric layer 205 and the gate insulating layer 204 and communicates with the substrate 201, as shown in fig. 1H.
Specifically, the active layer 202 includes a channel region 202a and doped regions 202b located at two sides of the channel region 202 a; the channel region 202a and the gate 2031 are aligned, the first hole 101 is connected to the doped region 202b of the active layer 202, the depth of the first hole 101 in the doped region 202b is greater than or equal to 0nm and less than or equal to 50nm, and further, the depth of the first hole 101 in the doped region 202b is greater than or equal to 15nm and less than or equal to 45nm, so that the source and the drain can be overlapped to the active layer 202 when the source and the drain are subsequently prepared, and the electrical connection between the source and the drain and the active layer 202 is realized.
The depth of the second hole 102 in the substrate 201 is greater than or equal to 0nm and less than or equal to 500nm, and further, the depth of the second hole 102 in the substrate 201 is greater than or equal to 100nm and less than or equal to 500nm, so as to reduce preparation defects and improve the production yield.
TO ensure that the first hole 101 communicates with the active layer 202, the second hole 102 communicates with the substrate 201, and in the step S70, a second etching time t4=t2+to etch the second region 102a tO form the second slave hole 1022; where t2 is the time spent etching tO the surface of the substrate 201 when the second slave hole 1022 is etched in the second region 102a, tO is the overetch time, to= (20% -50%). T2; further, to=30% > t2.
The depth of the second main hole 1021 (i.e., the first depth h 21) is less than or equal to the sum of the thicknesses of the interlayer dielectric layer 205 and the gate insulating layer 204, so as to ensure that the first hole 101 is also in communication with the active layer 202 when the second hole 102 is in communication with the substrate 201 in the step S70.
In the step S50, a depth h21 of the second main hole 1021 is equal to a product of a first etching time t1 for etching the second region 102a to form the second main hole 1021 and a first etching rate E2; i.e. h21=e2×t1; if the depth h21 of the second main hole 1021 is smaller than or equal to the thickness of the interlayer dielectric layer 205, the first etching rate E2 is equal to the etching rate of the interlayer dielectric layer 205, and the depth h21 of the second main hole 1021 is equal to the product of the first etching time t1 and the etching rate of the interlayer dielectric layer 205; if the depth h21 of the second main hole 1021 is smaller than or equal to the sum of the thicknesses of the interlayer dielectric layer 205 and the gate insulating layer 204, the depth h21 of the second main hole 1021 is equal to the sum of the product of the etching rate E21 of the interlayer dielectric layer 205 and the etching time t11 for etching the interlayer dielectric layer 205 and the product of the etching rate E22 of the gate insulating layer 204 and the etching time t12 for etching the gate insulating layer 204; namely: h21 =e21×t11+e22×t12, where t1=t11+t12.
The depth of the second slave hole 1022 (i.e., the second depth h 22) is equal to the difference between the depth h2 of the second hole 102 and the depth of the second master hole 1021 (i.e., the first depth h 21); namely: h22 =h2-h 21. Further, if the depth h21 of the second master hole 1021 is equal tO the thickness of the interlayer dielectric layer 205, the depth h22 of the second slave hole 1022 is equal tO the sum of the thickness of the gate insulating layer 204 and the thickness of the substrate 201 etched within the overetch time tw.
In addition, the substrate 100 may further include a buffer layer 206 disposed on a side of the substrate 201 near the active layer 202 and the gate insulating layer 204, and the second hole 102 penetrates the interlayer dielectric layer 205, the gate insulating layer 204, and the buffer layer 206 and communicates with the substrate 201. If the depth h21 of the second master hole 1021 is equal tO the thickness of the interlayer dielectric layer 205, the depth h22 of the second slave hole 1022 is equal tO the sum of the thicknesses of the gate insulating layer 204, the buffer layer 206, and the substrate 201 etched within the over-etching time tO.
Referring to fig. 2, which is a schematic structural diagram of a substrate according to an embodiment of the present application, the substrate 100 further includes a second insulating layer 207 located between the gate 2031, the gate insulating layer 204 and the interlayer dielectric layer 205, and a capacitor upper substrate layer 208 disposed opposite to the gate 2031, wherein the capacitor upper substrate layer 208 is located on a side of the second insulating layer 207 away from the gate 2031.
The first hole 101 penetrates the interlayer dielectric layer 205, the second insulating layer 207, and the gate insulating layer 204 and communicates with the active layer 202; the second hole 102 penetrates the interlayer dielectric layer 205, the second insulating layer 207, the gate insulating layer 204, and the buffer layer 206 and communicates with the substrate 201. The depth (i.e., the first depth h 21) of the second main hole 1021 is smaller than or equal to the sum of the thicknesses of the interlayer dielectric layer 205, the gate insulating layer 204, and the second insulating layer 207, so as to ensure that the second hole 102 communicates with the substrate 201 and the first hole 101 communicates with the active layer 202 in the step S70.
The preparation method of the substrate in fig. 2 for preparing the first hole 101 and the second hole 102 is the same as that in fig. 1B to 1H, and a person skilled in the art can prepare the first hole 101 and the second hole 102 on the substrate in fig. 2 by using the preparation method in fig. 1A, which is not described herein again.
The embodiment of the application also provides a display panel manufactured by adopting the manufacturing method of the display panel shown in the figure 1A. Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the application, where the display panel includes the substrate 100.
Further, the display panel further includes a source electrode and a drain electrode disposed in the first hole 101, and a light emitting device 107 electrically connected to the source electrode or the drain electrode.
Specifically, the preparation method as shown in fig. 1A further includes the following steps after the step S70:
s80: removing the photoresist layer 103;
s81: preparing a flexible filler layer 105 within the second aperture 102 of the second region 102 a;
S82: preparing a second metal layer 106 on the surface of the substrate 100; the second metal layer 106 includes a first member 1061 located at the first hole 101 of the first region 101a and a second member 1062 located on the surface of the flexible filling layer 105, where the first member 1061 is a source electrode and a drain electrode electrically connected to the doped region 202 b;
S83: forming a planarization layer 108 covering the second metal layer 106, and the planarization layer 108 being provided with a via hole at a position corresponding to one of the source electrode or the drain electrode;
S84: the light emitting device 107 is prepared.
The light emitting device 107 further includes an anode 1071, a cathode 1072, and a light emitting layer 1073 disposed between the anode 1071 and the cathode 1072, wherein the anode 1071 is electrically connected to the source or the drain, and the light emitting layer 1073 is disposed in a defined region of the pixel defining layer 109.
The flexible filling layer 105 is made of an organic material to improve bending performance of the display panel when the display panel is bent.
The preparation method of the display panel and the display panel provided by the embodiment of the application comprise the following steps: providing a substrate 100 with a first hole 101 and a second hole 102 to be formed, wherein the substrate 100 comprises a first area 101a corresponding to the first hole 101 and a second area 102a corresponding to the second hole 102, the first area 101a is positioned in a display area 100a of the display panel, and the second area 102a is positioned in a non-display area 100b of the display panel; forming a photoresist layer 103 covering the substrate 100; providing a half-tone light modulation mask 104, and performing exposure treatment on the photoresist layer 103 on the substrate 100 by using the half-tone light modulation mask 104; developing the substrate 100 to remove a portion of the photoresist corresponding to the first region 101a to obtain a first remaining photoresist 1031 corresponding to the first region 101a, and removing all of the photoresist corresponding to the second region 102 a; removing a portion of the first remaining photoresist 1031 to obtain a second remaining photoresist 1032 corresponding to the first region 101a, etching the second region 102a to obtain a second main hole 1021 having an etching depth of a first depth h21 in the second region 102 a; removing the second remaining photoresist 1032; the first region 101a and the second region 102a are etched, the first hole 101 is obtained in the first region 101a, and the second slave hole 1022 having an etching depth of the second depth h22 is obtained in the second region 102 a. Wherein the second hole 102 includes the second master hole 1021 and the second slave hole 1022, and a depth h2 of the second hole 102 is greater than a depth h1 of the first hole 101. By adopting the preparation method, the first holes positioned in the display area and the second holes positioned in the non-display area can be prepared through 1 photomask, so that the photomask used in the preparation process of the display panel is reduced.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The above description is provided for the preparation method of the display panel and the display panel provided by the embodiment of the application, and specific examples are applied to describe the principle and implementation of the application, and the description of the above examples is only used for helping to understand the technical scheme and core idea of the application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (8)
1. A method for manufacturing a display panel, comprising the steps of:
S10: providing a substrate with a first hole and a second hole to be formed, wherein the substrate comprises a first area corresponding to the first hole and a second area corresponding to the second hole, the first area is positioned in a display area of the display panel, and the second area is positioned in a non-display area of the display panel;
s20: forming a photoresist layer covering the substrate;
S30: providing a half-tone light modulation cover, and performing exposure treatment on the photoresist layer on the substrate by using the half-tone light modulation cover;
S40: developing the substrate to remove part of the photoresist corresponding to the first region to obtain first residual photoresist corresponding to the first region, and removing all the photoresist corresponding to the second region;
s50: removing part of the photoresist of the first residual photoresist to obtain second residual photoresist corresponding to the first region, and etching the second region to obtain a second main hole with etching depth of a first depth in the second region;
s60: ashing is adopted to remove the second residual photoresist; the ashing gas adopts oxygen or mixed gas containing oxygen;
S70: etching the first region and the second region by adopting a dry etching process, obtaining the first hole in the first region, and obtaining a second slave hole with etching depth of a second depth in the second region; the etching gas comprises one or more of CxFy, SFx, cxHyFz, O 2、H2 and Ar;
Wherein the second hole comprises the second master hole and the second slave hole, and the depth of the second hole is larger than that of the first hole; the second main hole comprises a main bottom wall and a main side wall connected to the main bottom wall, a first included angle is formed between the main bottom wall and the main side wall, a public edge formed between an adjacent complementary angle of the first included angle and the first included angle is the main side wall, and the adjacent complementary angle of the first included angle is larger than or equal to 30 degrees and smaller than or equal to 70 degrees;
S80: removing the photoresist layer;
S81: preparing a flexible filler layer within the second aperture of the second region;
s82: preparing a second metal layer on the surface of the substrate; the second metal layer comprises a first component positioned at the first hole of the first region and a second component positioned on the surface of the flexible filling layer, and the first component is a source electrode and a drain electrode which are electrically connected with the doped region;
S83: forming a flat layer covering the second metal layer, wherein the flat layer is provided with a through hole at a position corresponding to one of the source electrode or the drain electrode;
S84: preparing a light emitting device;
The half-tone light modulation cover comprises a light transmission area, a semi-transmission area and a shading area, wherein the light transmission area is aligned with a part of areas in the non-display area to form a second area, the semi-transmission area is aligned with a part of areas in the display area to form a first area, and the shading area is aligned with an area except the first area on the display area and an area except the second area on the non-display area;
the light transmittance of the semi-transparent area is 20% -40%;
the thickness of the second residual photoresist is equal to the difference between the thickness of the first residual photoresist and the etching thickness of the first residual photoresist; the first remaining photoresist has an etch thickness equal to a product of an etch rate of the first remaining photoresist and a first etch time to etch the second region to form the second main hole.
2. The method of manufacturing according to claim 1, wherein the substrate comprises:
A substrate;
An active layer formed in the display region and located on at least one side of the substrate;
the first metal layer is at least positioned on one side of the active layer, and comprises a grid electrode arranged corresponding to the active layer;
the grid insulation layer is formed in the display area and the non-display area and is positioned between the active layer and the first metal layer;
an interlayer dielectric layer covering the gate electrode and the gate insulating layer;
Wherein the first hole penetrates through the interlayer dielectric layer and the gate insulating layer and is communicated with the active layer, and the second hole penetrates through the interlayer dielectric layer and the gate insulating layer and is communicated with the substrate.
3. The method of claim 2, wherein the active layer comprises a channel region and doped regions on both sides of the channel region; the channel region is arranged in alignment with the gate, the first hole is communicated with the doped region of the active layer, and the depth of the first hole in the doped region is greater than or equal to 0nm and less than or equal to 50nm.
4. The method of manufacturing according to claim 2, wherein the depth of the second hole in the substrate is greater than or equal to 0nm and less than or equal to 500nm.
5. The method of manufacturing according to claim 2, wherein a depth of the second main hole is less than or equal to a sum of thicknesses of the interlayer dielectric layer and the gate insulating layer.
6. The method of claim 1, wherein the difference between the width of the second master hole and the width of the second slave hole is less than or equal to 4 μm.
7. The method of claim 1, wherein the second slave hole comprises a slave bottom wall and a slave side wall connected to the slave bottom wall, the slave bottom wall and the slave side wall have a second included angle therebetween, a common edge between an adjacent complement angle of the second included angle and the second included angle is the slave side wall, and the adjacent complement angle of the second included angle is greater than or equal to 30 ° and less than or equal to 70 °.
8. A display panel produced by the method for producing a display panel according to any one of claims 1 to 6.
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| CN113053983A (en) * | 2021-03-17 | 2021-06-29 | 昆山国显光电有限公司 | Display panel manufacturing method and display panel |
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