CN111276401A - High electron mobility transistor and manufacturing method thereof - Google Patents
High electron mobility transistor and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 52
- 230000000149 penetrating effect Effects 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 55
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 14
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000000206 photolithography Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000005137 deposition process Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 11
- 230000008021 deposition Effects 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000609 electron-beam lithography Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 230000003749 cleanliness Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The embodiment of the application provides a high electron mobility transistor and a manufacturing method thereof. And finally, etching the first dielectric layer based on the through hole to form a groove penetrating through the first dielectric layer, and manufacturing and forming a gate electrode positioned on the groove, the through hole, the isolation layer and the second dielectric layer. The gate electrode with smaller width can be prepared and formed by common yellow light development and deposition processes in the semiconductor manufacturing process, the manufacturing process is simple, the manufacturing speed is high, and extra cost is not required to be introduced.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a high electron mobility transistor and a manufacturing method thereof.
Background
High Electron Mobility Transistors (HEMTs) are required for future 5G devices and future millimeter wave device fabrication. The width of the gate electrode of the HEMT directly affects the high frequency characteristics thereof, and the smaller the width of the gate electrode, the better the high frequency performance thereof, and therefore, how to obtain the HEMT having the gate electrode with a smaller width becomes a major research point.
At present, the commonly adopted method for defining the shape of the gate electrode is to directly define a region with a small line width on the photoresist layer by means of electron beam lithography, and then perform the subsequent gate electrode fabrication based on the defined region. Although the gate electrode with a smaller width can be obtained by the method in the prior art, the electron beam lithography has the problems of complicated process and slow manufacturing speed. Moreover, the equipment on which electron beam lithography is based is expensive. The scheme in the prior art has the problems of slow manufacturing process and higher cost.
Disclosure of Invention
The present disclosure provides a high electron mobility transistor and a method for fabricating the same, which can obtain a gate electrode with a smaller width based on a simple and fast process.
The embodiment of the application can be realized as follows:
in a first aspect, an embodiment provides a method for fabricating a high electron mobility transistor, the method including:
sequentially manufacturing and forming a first dielectric layer and a second dielectric layer on the basis of the provided substrate;
defining an etching area on the second dielectric layer through a yellow light developing process, and etching the second dielectric layer based on the etching area to form a through hole penetrating through the second dielectric layer;
manufacturing an isolation layer positioned on the hole wall of the through hole to reduce the width of the through hole to 0.07um-0.1 um;
etching the first dielectric layer based on the through hole to form a groove penetrating through the first dielectric layer;
and manufacturing and forming a gate electrode on the groove, the through hole, the isolation layer and the second dielectric layer.
In an alternative embodiment, the method further comprises:
and removing the second dielectric layer by adopting a wet etching process.
In an alternative embodiment, the step of forming the isolation layer on the wall of the through hole includes:
depositing and forming an isolation layer in the second dielectric layer and the through hole of the second dielectric layer;
and etching the deposited isolation layer, removing the isolation layers on the second dielectric layer and at the bottom of the hole of the through hole close to the first dielectric layer, and reserving the isolation layer on the wall of the through hole to reduce the width of the through hole.
In an optional embodiment, the step of defining an etching region on the second dielectric layer by a yellow light developing process, and etching the second dielectric layer based on the etching region to form a through hole therethrough includes:
forming a first photoresist layer on the second dielectric layer;
exposing and developing the first photoresist layer by utilizing a yellow light developing process to define an etching area with the width less than or equal to 0.2um on the second dielectric layer, etching the second dielectric layer on the basis of the etching area to cut off the surface of the first dielectric layer, and forming a through hole penetrating through the second dielectric layer;
and removing the first photoresist layer remained after exposure and development.
In an alternative embodiment, the step of forming a gate electrode on the recess, the via, the isolation layer and the second dielectric layer includes:
forming a second photoresist layer on the isolation layer and the second dielectric layer;
exposing and developing the second photoresist layer through a yellow light developing process to expose partial areas of the isolation layer and the second dielectric layer;
depositing gate metal in the second photoresist layer, the isolation layer, the exposed second dielectric layer, the groove and the through hole;
and removing the second photoresist layer and the gate metal on the second photoresist layer to form a gate electrode on the groove, the through hole, the isolation layer and the second dielectric layer.
In an alternative embodiment, the first dielectric layer and the spacer layer are made of silicon nitride and the second dielectric layer is made of silicon oxide.
In an alternative embodiment, the substrate is made of gallium arsenide.
In a second aspect, an embodiment provides a high electron mobility transistor, including:
a substrate;
the substrate comprises a first dielectric layer and an isolation layer which are sequentially formed on the substrate, wherein the isolation layer is provided with a through hole formed in an etching area defined by a yellow light developing process, the width of the through hole is 0.07-0.1 um, and the first dielectric layer is provided with a groove formed on the basis of the through hole;
and a gate electrode formed on the groove, the via hole and the isolation layer.
In an alternative embodiment, the first dielectric layer and the spacer layer are made of silicon nitride.
In an alternative embodiment, the substrate is made of gallium arsenide.
The beneficial effects of the embodiment of the application include, for example:
according to the high electron mobility transistor and the manufacturing method thereof provided by the embodiment of the application, the first dielectric layer and the second dielectric layer are sequentially formed on the provided substrate, the etching area is defined on the second dielectric layer through the yellow light developing process, and the second dielectric layer is etched on the basis of the etching area to form the through hole penetrating through the second dielectric layer. And finally, etching the first dielectric layer based on the through hole to form a groove penetrating through the first dielectric layer, and manufacturing and forming a gate electrode positioned on the groove, the through hole, the isolation layer and the second dielectric layer. The method comprises defining an etching region with small size by yellow light developing process to etch the via hole, and depositing an isolation layer on the wall of the via hole to further reduce the width of the via hole, so as to limit the width of the gate electrode formed in the via hole to a small width. The gate electrode with smaller width can be prepared and formed by the common yellow light development and deposition process in the semiconductor manufacturing process, the manufacturing process is simple, the manufacturing speed is high, and extra cost is not required to be introduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present disclosure;
fig. 3 to fig. 11 are schematic structural diagrams of devices formed in steps of a method for manufacturing a high electron mobility transistor according to an embodiment of the present disclosure.
Icon: 10-a substrate; 20-a first dielectric layer; 21-a groove; 30-an isolation layer; 31-a through hole; 40-a gate electrode; 50-a second dielectric layer; 60-a first photoresist layer; 61-a first mask; 70-a second photoresist layer; 71-a second mask; 80-gate metal.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer", etc. are used to indicate an orientation or positional relationship based on that shown in the drawings or that the application product is usually placed in use, the description is merely for convenience and simplicity, and it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore should not be construed as limiting the present application. Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Referring to fig. 1, a device structure diagram of a high electron mobility transistor according to an embodiment of the present disclosure is shown, the high electron mobility transistor includes a substrate 10, and a first dielectric layer 20 and an isolation layer 30 are sequentially deposited on the substrate 10. Wherein the substrate 10 may be a gallium arsenide substrate, the first dielectric layer 20 and the isolation layer 30 may be made of silicon nitride. The silicon nitride material has stable performance, and the first dielectric layer 20 which is formed by the silicon nitride material and is in contact with the gallium arsenide substrate 10 can guarantee the performance and reliability of the device.
In this embodiment, the isolation layer 30 has a through hole 31 formed in an etching region defined by a photolithography process, the width of the through hole 31 is 0.07um to 0.1um, and the first dielectric layer 20 has a groove 21 formed on the basis of the through hole 31. The via 31 formed on the isolation layer 30 corresponds to the groove 21 on the first dielectric layer 20 in position and has the same width in the longitudinal direction. In addition, the HEMT further includes a gate electrode 40 formed on the recess 21, the via 31 and the isolation layer 30.
The deposited gate electrode 40 is a T-shaped electrode including a gate foot portion located in the recess 21 and the via 31, and a gate head portion located on the isolation layer 30. Since the width of the through hole 31 formed in the etching region defined based on the photolithography process can be limited to 0.07um to 0.1um, the width of the groove 21 formed in the first dielectric layer 20 based on the through hole 31 can also be limited to 0.07um to 0.1 um. The gate foot of the T-shaped electrode in the groove 21 and the via 31 is limited in width by the groove 21 and the via 31, and the width of the gate foot of the T-shaped electrode is also limited to 0.07um-0.1 um.
The HEMT provided in this embodiment comprises a gate deposition region defined by photolithography, the width of the gate electrode 40 obtained finally can be 0.07um-0.1um, and the small size of the gate electrode 40 is beneficial to the high frequency characteristics of the HEMT.
Referring to fig. 2, the present disclosure also provides a method for fabricating a high electron mobility transistor, which can be used for fabricating the high electron mobility transistor, and the detailed process of the fabrication method will be described below.
Referring to fig. 3-10, in step S110, a first dielectric layer 20 and a second dielectric layer 50 are sequentially formed on the basis of the provided substrate 10.
Referring to fig. 3, the first dielectric layer 20 and the second dielectric layer 50 may be deposited by any one of Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and inductively coupled Plasma Enhanced Deposition (ICP-PECVD).
The substrate 10 may beFor a gallium arsenide substrate, the first dielectric layer 20 may be a silicon nitride (SiN) layer, the first dielectric layer 20 may be deposited to a thickness of 100A-500A, and the second dielectric layer 50 may be silicon oxide (SiO)2) The layer, as deposited, may have a thickness of 1000A to 4000A. Wherein, the silicon nitride material and the silicon oxide material are all general materials based on gallium arsenide substrate growth at present.
Step S120, defining an etching region on the second dielectric layer 50 by a yellow light developing process, and etching the second dielectric layer 50 based on the etching region to form a through hole 31 penetrating therethrough.
Step S130, forming an isolation layer 30 on the wall of the through hole 31 to reduce the width of the through hole 31 to 0.07um to 0.1 um.
Step S140, etching the first dielectric layer 20 based on the through hole 31 to form a groove 21 penetrating therethrough.
Step S150 is to fabricate and form the gate electrode 40 on the recess 21, the via 31, the isolation layer 30 and the second dielectric layer 50.
In this embodiment, the etching area with smaller size is defined by yellow light development to etch the via hole 31, and then the isolation layer 30 is deposited on the wall of the via hole 31 to further reduce the width of the via hole 31, so that the width of the gate electrode 40 formed in the via hole 31 is limited to a smaller width, for example, 0.07um to 0.1 um. Thus, the purpose of rapidly manufacturing the gate electrode 40 with small dimension and width is achieved. And the yellow light developing machine is a universal device in the gallium arsenide production process, and extra manufacturing cost is not required to be added.
The manufacturing method provided by the embodiment can prepare and form the gate electrode 40 with a smaller width by utilizing the common yellow light development and deposition processes in the semiconductor manufacturing process, and has the advantages of simple manufacturing process, high manufacturing speed and no need of introducing extra cost.
Referring to the step S120 and fig. 4, in the present embodiment, an etching region is defined on the second dielectric layer 50 by a photolithography process. Specifically, a first photoresist layer 60 may be formed on the second dielectric layer 50, and the first photoresist layer 60 may be formed using a positive photoresist or a negative photoresist. When a positive photoresist is used, the exposed areas undergo a decomposition or degradation reaction, causing a change in their properties to be preferentially dissolved in the positive developer, leaving the unexposed portions. When a negative photoresist is used, the unexposed areas are preferentially dissolved in a negative developer.
In this embodiment, the first photoresist layer 60 is exposed and developed by a photolithography process on the basis of coating the first photoresist layer 60, so as to expose a partial region of the second dielectric layer 50. The yellow light development process includes a yellow light process of performing ultraviolet light pattern exposure of the photoresist material based on the first photomask 61 in a yellow light environment and a development process of cleaning the photoresist material using a developing solution to remove the photoresist material that is not cured by exposure or the photoresist material in the exposed region.
In this embodiment, the first photoresist layer 60 may be made of a positive photoresist material, so that after the mask-based photolithography process, the photoresist material in the exposed region is removed using a positive developing solution to leave the unexposed portion.
The common exposure wavelength includes i-line (365nm), h-line (405nm) and g-line (436nm), and the minimum line width that can be achieved at the i-line exposure wavelength is equal to or less than 0.2 um. In this embodiment, the exposure wavelength is i-line (365nm), and an etching region with a width less than or equal to 0.2um can be defined on the second dielectric layer 50 by i-line yellow light development.
Referring to fig. 5, after an etching region is defined on the second dielectric layer 50, the second dielectric layer 50 is etched based on the formed etching region. The etching manner may be dry etching or wet etching, etc. The etching depth of the second dielectric layer 50 can be cut off from the surface of the first dielectric layer 20 to avoid damaging the first dielectric layer 20, thereby obtaining the via 31 penetrating the second dielectric layer 50. Alternatively, the selectivity of silicon nitride to silicon oxide may be used when etching the first dielectric layer 20, thereby stopping the etching at the surface of the first dielectric layer 20.
Next, the first photoresist layer 60 remaining after the exposure and development is removed, and the remaining first photoresist layer 60 may be removed using an organic solution. After the first photoresist layer 60 is removed, the obtained device can be cleaned and baked, and the polymer on the surface of the device can be removed through a cleaning process, so that the cleanliness of the surface of the device is ensured. And the moisture on the surface of the device can be removed through the baking process, so that the formed hierarchical structure can be better attached to the surface of the device in the subsequent process manufacturing.
Referring to step S130 and fig. 6, on the basis of the above, an isolation layer 30 is deposited and formed in the second dielectric layer 50 and the via hole 31 of the second dielectric layer 50. The isolation layer 30 may be a silicon nitride layer and the thickness of the deposited isolation layer 30 may be 500A-650A. The deposition method can adopt any one of PECVD, LPCVD and ICP-PECVD.
Referring to fig. 7, the deposited isolation layer 30 is then etched, which may be dry etching or wet etching.
Since the deposition-formed isolation layer 30 is distributed on the second dielectric layer 50 and in the via hole 31 of the second dielectric layer 50, the portion of the isolation layer 30 located in the via hole 31 will form a shape recessed downward. In the etching, the isolation layer 30 acting on the second dielectric layer 50 and the isolation layer 30 located at the bottom of the hole of the via hole 31 near the first dielectric layer 20 are etched.
The etching time can be controlled to etch away the isolation layer 30 covering the second dielectric layer 50 to expose the region of the second dielectric layer 50 covered by the deposited isolation layer 30. And, at the same time, the isolation layer 30 at the bottom of the via hole 31 is etched away to expose the first dielectric layer 20 at a position corresponding to the via hole 31. And, the isolation layer 30 deposited on the wall of the via hole 31 is retained.
The isolation layer 30 remaining on the wall of the hole reduces the width of the via hole 31. On the basis that the width of the through hole 31 formed by the yellow light development is less than or equal to 0.2um, the width of the through hole 31 can be further reduced to 0.07um to 0.1um by the isolation layer 30 formed on the wall of the through hole 31.
In view of the above, the thickness of the isolation layer 30 remaining on the wall of the via hole 31 after deposition and etching in the cross-sectional direction of the via hole 31 determines the width of the subsequent gate foot, and in this embodiment, the thickness of the isolation layer 30 formed on the wall of the via hole can be adjusted by controlling the deposition duration, deposition range, etc. of the isolation layer 30, so as to adjust the width of the defined gate foot region.
Referring to step S140, referring to fig. 8, on the basis of the reduced via 31, the first dielectric layer 20 is etched to form a recess 21 on the first dielectric layer 20. In this embodiment, the first dielectric layer 20 is etched in a direction perpendicular to the surface of the first dielectric layer 20 based on the through holes 31 in the isolation layer 30, and the first dielectric layer 20 may be etched by using an Inductively Coupled Plasma (ICP) etching method. The etching of the first dielectric layer 20 may etch through the first dielectric layer 20 and stop at the surface of the substrate 10, forming the recess 21 as a subsequent gate contact.
Referring to step S150 and fig. 9, the through hole 31 and the recess 21 formed by the above steps define the gate foot profile of the gate electrode 40, and further define the gate head profile of the gate electrode 40. Specifically, a second photoresist layer 70 is first formed on the isolation layer 30 and the second dielectric layer 50, and the second photoresist layer 70 may be made of a positive photoresist or a negative photoresist. The second photoresist layer 70 is exposed and developed by a photolithography process and a second mask 71 to expose partial regions of the isolation layer 30 and the second dielectric layer 50.
Wherein the exposed isolation layer 30 and a portion of the second dielectric layer 50 are the gate head feature of the gate electrode 40, and the sum of the widths of the exposed isolation layer 30 and the portion of the second dielectric layer 50 is defined as the width of the gate head formed by the subsequent deposition. Then, the gate foot feature defined by the via hole 31 and the groove 21 is combined to form a T-shaped gate feature, so as to form a T-shaped electrode.
Referring to fig. 10, a gate metal 80 is deposited on the second photoresist layer 70, the isolation layer 30, the exposed second dielectric layer 50, the recess 21, and the via 31. Then, the second photoresist layer 70 and the gate metal 80 on the second photoresist layer 70 are removed, so as to form a gate electrode 40 on the recess 21, the via hole 31, the isolation layer 30 and the second dielectric layer 50, wherein the gate electrode 40 is a T-shaped electrode, and the structure of the device is shown in fig. 11. Since the width of the via 31 and the groove 21 is limited to 0.07um-0.1um, the width of the gate foot formed by final deposition can be 0.07um-0.1 um.
In this embodiment, the second dielectric layer 50 is finally removed by a wet etching process, so as to finally obtain the device structure shown in fig. 1. In this embodiment, since the second dielectric layer 50 is a silicon oxide layer and the substrate 10 is a gallium arsenide layer, the characteristics of the silicon oxide layer are unstable, so as to avoid the influence on the gallium arsenide substrate 10, and therefore, after the gate electrode 40 is fabricated, the second dielectric layer 50 is removed, and only the isolation layer 30 and the first dielectric layer 20 with stable performance are remained.
Furthermore, the second dielectric layer 50 is removed, so as to avoid the limitation of the height of the gate head portion by the second dielectric layer 50.
In this embodiment, the gate electrode 40 with a width of 0.07um to 0.1um can be obtained by the i-line yellow development process commonly used in the current GaAs process and combining with conventional semiconductor processes such as deposition and etching. These processes are all gallium arsenide compatible processes, so that high-yield production of high-performance, small-linewidth, high-electron-mobility transistors can be achieved without adding additional cost.
In summary, according to the high electron mobility transistor and the manufacturing method thereof provided by the embodiment of the present application, the first dielectric layer 20 and the second dielectric layer 50 are sequentially formed on the provided substrate 10, the etching region is defined on the second dielectric layer 50 through the photolithography process, and the through hole 31 penetrating through the second dielectric layer 50 is formed by etching based on the etching region. Then, the isolation layer 30 formed on the wall of the via hole 31 is fabricated to reduce the width of the via hole 31 to 0.07um-0.1um, and finally, the first dielectric layer 20 is etched based on the via hole 31 to form a groove 21 penetrating therethrough, and a gate electrode 40 is fabricated on the groove 21, the via hole 31, the isolation layer 30 and the second dielectric layer 50.
The present scheme firstly utilizes the yellow light developing process to define the etching area with smaller size to etch the through hole 31, and then deposits the isolation layer 30 on the wall of the through hole 31 to further reduce the width of the through hole 31, thereby limiting the width of the gate electrode 40 formed in the through hole 31 in the following step to be smaller. The gate electrode 40 with a smaller width can be prepared and formed by the common yellow light development and deposition process in the semiconductor manufacturing process, the manufacturing process is simple, the manufacturing speed is high, and no extra cost is required to be introduced.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method for fabricating a high electron mobility transistor, the method comprising:
sequentially manufacturing and forming a first dielectric layer and a second dielectric layer on the basis of the provided substrate;
defining an etching area on the second dielectric layer through a yellow light developing process, and etching the second dielectric layer based on the etching area to form a through hole penetrating through the second dielectric layer;
manufacturing an isolation layer positioned on the hole wall of the through hole to reduce the width of the through hole to 0.07um-0.1 um;
etching the first dielectric layer based on the through hole to form a groove penetrating through the first dielectric layer;
and manufacturing and forming a gate electrode on the groove, the through hole, the isolation layer and the second dielectric layer.
2. The method of fabricating a high electron mobility transistor according to claim 1, further comprising:
and removing the second dielectric layer by adopting a wet etching process.
3. The method of claim 1, wherein the step of forming an isolation layer on the wall of the via hole comprises:
depositing and forming an isolation layer in the second dielectric layer and the through hole of the second dielectric layer;
and etching the deposited isolation layer, removing the isolation layers on the second dielectric layer and at the bottom of the hole of the through hole close to the first dielectric layer, and reserving the isolation layer on the wall of the through hole to reduce the width of the through hole.
4. The method of claim 1, wherein the step of defining an etched region on the second dielectric layer by a photolithography process, and etching the second dielectric layer based on the etched region to form a via hole therethrough comprises:
forming a first photoresist layer on the second dielectric layer;
exposing and developing the first photoresist layer by utilizing a yellow light developing process to define an etching area with the width less than or equal to 0.2um on the second dielectric layer, etching the second dielectric layer on the basis of the etching area to cut off the surface of the first dielectric layer, and forming a through hole penetrating through the second dielectric layer;
and removing the first photoresist layer remained after exposure and development.
5. The method of claim 1, wherein the step of forming the gate electrode over the recess, via, isolation layer and second dielectric layer comprises:
forming a second photoresist layer on the isolation layer and the second dielectric layer;
exposing and developing the second photoresist layer through a yellow light developing process to expose partial areas of the isolation layer and the second dielectric layer;
depositing gate metal in the second photoresist layer, the isolation layer, the exposed second dielectric layer, the groove and the through hole;
and removing the second photoresist layer and the gate metal on the second photoresist layer to form a gate electrode on the groove, the through hole, the isolation layer and the second dielectric layer.
6. The method of fabricating the hemt of any one of claims 1 to 5, wherein the first dielectric layer and the spacer are made of silicon nitride, and the second dielectric layer is made of silicon oxide.
7. The method of fabricating the hemt of any one of claims 1-5, wherein said substrate is made of gallium arsenide.
8. A high electron mobility transistor, comprising:
a substrate;
the substrate comprises a first dielectric layer and an isolation layer which are sequentially formed on the substrate, wherein the isolation layer is provided with a through hole formed in an etching area defined by a yellow light developing process, the width of the through hole is 0.07-0.1 um, and the first dielectric layer is provided with a groove formed on the basis of the through hole;
and a gate electrode formed on the groove, the via hole and the isolation layer.
9. The hemt of claim 8, wherein said first dielectric layer and spacer layer are made of silicon nitride.
10. The hemt of claim 8, wherein said substrate is made of gallium arsenide.
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| US20190189451A1 (en) * | 2017-12-20 | 2019-06-20 | Shaghai Huali Microelectronics Corporation | Semiconductor structure with metal gate, and method for manufacturing the same |
| CN110047744A (en) * | 2019-04-28 | 2019-07-23 | 苏州汉骅半导体有限公司 | T-type grid preparation method |
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| US20030096486A1 (en) * | 2001-09-04 | 2003-05-22 | United Microelectronics Corp. | Fabrication of self-aligned bipolar transistor |
| US20150235856A1 (en) * | 2014-02-20 | 2015-08-20 | Raytheon Company | Semiconductor structures having t-shaped electrodes |
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| US20190189451A1 (en) * | 2017-12-20 | 2019-06-20 | Shaghai Huali Microelectronics Corporation | Semiconductor structure with metal gate, and method for manufacturing the same |
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