CN111273941B

CN111273941B - Marine control system

Info

Publication number: CN111273941B
Application number: CN202010050904.0A
Authority: CN
Inventors: 孙征宇; 李丛林; 杨兆平
Original assignee: Sg Prosperous Technology Ltd
Current assignee: Sg Prosperous Technology Ltd
Priority date: 2020-01-17
Filing date: 2020-01-17
Publication date: 2023-06-16
Anticipated expiration: 2040-01-17
Also published as: CN111273941A

Abstract

The invention relates to a marine control system, which comprises a user program layer, a control layer and a control layer, wherein the user program layer is used for completing data receiving and transmitting, registering reading and writing and interrupt processing of a bottom hardware interface module, and hardware driving; the user interface layer is used for encapsulating the functions which can be directly called by the user with the bottom hardware interface functions, realizing the functions which the hardware interface needs to realize, and forming a set of API; the hardware driving layer integrates all hardware modules in the system to coordinate with each other to complete the system function through a certain scheduling mechanism; the invention combines each logic to finally complete the configuration management, peripheral configuration and peripheral monitoring of the whole marine control system according to the system requirements by completing the function call of the user interface layer.

Description

Marine control system

Technical Field

The invention relates to the technical field of control systems, in particular to a marine control system.

Background

Because more and more devices and more complicated parts on the ship are provided, the simple manual control or the independent control cannot meet the requirements, and a complete automatic control system is needed at the moment, so that the peripheral sensors are collected and controlled uniformly.

Disclosure of Invention

The invention aims to provide a marine control system.

The invention aims at realizing the following technical scheme: the system comprises a user program layer, a hardware driver and a control module, wherein the user program layer is used for completing data receiving and transmitting of a bottom hardware interface module, registering reading and writing and interrupt processing and the hardware driver;

the user interface layer is used for encapsulating the functions which can be directly called by the user with the bottom hardware interface functions, realizing the functions which the hardware interface needs to realize, and forming a set of API;

the hardware driving layer integrates all hardware modules in the system through a scheduling mechanism to coordinate with each other so as to complete the system function;

the user program layer is connected with the user interface layer, and the user interface layer is connected with the hardware driving layer.

In a preferred embodiment, the user program layer comprises a user program APP.

In a preferred embodiment, the user interface layer includes a system initialization interface, a UART data transceiver interface, FPGA interface management, DAC interface management, timer management interface, all connected to the user program layer.

In a preferred embodiment, the FPGA interface management is connected with a DI interface, a DO interface, a temperature sensor interface, an ADC interface, an alarm interface and an IGBT interface.

In a preferred embodiment, the hardware driving layer includes a DSP system hardware management module, an SPI interface management module, an EMIF interface management module, a UART interface management module, a PWM interface management module, and a GPIO interface management module, where the DSP system hardware management module, the EMIF interface management module, the PWM interface management module, and the GPIO interface management module are all connected with a system initialization interface, the DSP system hardware management module is connected with a DAC interface management, the EMIF interface management module is further connected with an FPGA interface management, the UART interface management module is connected with a UART data transceiver interface, the PWM interface management module is connected with a timer management interface, and the GPIO interface management module is connected with the FPGA interface management.

The beneficial effects of the invention are as follows: and through completing function call to the user interface layer, combining all logics to finally complete configuration management, peripheral configuration and peripheral monitoring of the whole marine control system according to the requirements of the system.

Drawings

The invention is described in further detail below with reference to the accompanying drawings.

FIG. 1 is a system diagram of a marine control system according to an embodiment of the present invention;

fig. 2 is a flow chart of operation of the marine control system according to an embodiment of the present invention.

In the figure:

1. a user program layer; 2. a user interface layer; 3. a hardware driving layer; 4. a user program APP; 5. a system initialization interface; 6. UART data receiving and transmitting interfaces; 7. managing an FPGA interface; 8. DAC interface management; 9. a timer management interface; 10. a DSP system hardware management module; 11. SPI interface management module; 12. EMIF interface management module; 13. UART interface management module; 14. a PWM interface management module; 15. a GPIO interface management module; 16. a DI interface; 17. a DO interface; 18. a temperature sensor interface; 19. an ADC interface; 20. an alarm interface; 21. IGBT interface.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.

The invention will be further described with reference to the drawings and specific examples.

As shown in FIG. 1, the marine control system of the embodiment of the invention comprises a user program layer 1, a control module and a control module, wherein the user program layer 1 is used for completing data transceiving, register read-write and interrupt processing of a bottom hardware interface module and hardware driving;

the user interface layer 2 is used for encapsulating the functions which can be directly called by a user with the bottom hardware interface functions, realizing the functions which the hardware interface needs to realize, and forming a whole set of API;

the hardware driving layer 3 integrates all hardware modules in the system to coordinate with each other to complete the system function through a certain scheduling mechanism;

the user program layer 1 is connected to the user interface layer 2, and the user interface layer 2 is connected to the hardware driver layer 3.

The user program layer 1 comprises a user program APP 4.

The user interface layer 2 comprises a system initialization interface 5, a UART data transceiver interface 6, an FPGA interface management 7, a DAC interface management 8 and a timer management interface 9 which are all connected with the user program layer 1.

The FPGA interface management 7 is connected with a DI interface 16, a DO interface 17, a temperature sensor interface 18, an ADC interface 19, an alarm interface 20 and an IGBT interface 21.

The hardware driving layer 3 comprises a DSP system hardware management module 10, an SPI interface management module 11, an EMIF interface management module 12, a UART interface management module 13, a PWM interface management module 14 and a GPIO interface management module 15, wherein the DSP system hardware management module 10, the EMIF interface management module 12, the PWM interface management module 14 and the GPIO interface management module 15 are all connected with the system initialization interface 5, the DSP system hardware management module 10 is connected with the DAC interface management 8, the EMIF interface management module 12 is also connected with the FPGA interface management 7, the UART interface management module 13 is connected with the UART data receiving and transmitting interface 6, the PWM interface management module 14 is connected with the timer management interface 9, and the GPIO interface management module 15 is connected with the FPGA interface management 7.

Hardware driving layer 3:

the hardware driver is the only interface for realizing the interaction between the application program and all peripheral equipment in the equipment, and can realize the control and state monitoring operation of various peripheral equipment in the marine control system through the hardware interface driver. The marine control system mainly comprises the following hardware interfaces:

DSP hardware management interface: the method is mainly responsible for basic initialization of a DSP (i.e. CPU), and completes the basic initialization of the DSP after the system is powered on, and comprises configuration of a system running clock, a system RAM and system interrupt. The most basic operation environment is built for the later system operation, so the DSP hardware management interface needs to provide the following function interfaces:

Dsp_system_init

Dsp_system_clk_init

Dsp_system_ram_init

Dsp_system_irq_init

SPI interface: and providing a group of SPI communication interfaces based on three wires, and realizing communication with peripheral equipment meeting SPI time sequence requirements by configuring the SPI interfaces, thereby meeting the requirements of data transmission. The SPI driving interface provides parameter configuration, data transmission and data receiving functions for SPI at the bottom layer. The configuration of parameters includes the configuration of parameters such as clock frequency, data phase, data bit width, interrupt, FIFO, etc., so the SPI interface driver needs to provide the following interface functions:

Dsp_spi_cfg

Dsp_spi_send

Dsp_spi_recv

Dsp_spi_reset

EMIF interface: the EMIF interface is a set of parallel data transfer interfaces based on data and address buses through which the data is passed. The data bus and associated control interface may enable high-speed data transfer with the peripheral devices. The marine control system is mainly used for realizing data communication of SRAM and FPGA, and the function package of the EMIF interface is as follows:

Dsp_emif_init

Dsp_emif_reset

Dsp_emif_read_reg

Dsp_emif_write_reg

UART interface: the UART interface mainly realizes data communication with external RS232 equipment, and realizes data transmission and information sharing with the external equipment through the UART interface by configuring the baud rate, the data bit width, the parity check bit and the stop bit parameters of the UART interface, so that the function package of the UART interface is as follows:

Dsp_uart_init

Dsp_uart_cfg

Dsp_uart_reset

Dsp_uart_read_char

Dsp_uart_send_char

PWM interface: the PWM interface mainly realizes the initialization of a PWM timer in the system and completes the configuration of a clock and an interrupt parameter in a PWM module. The function package for the PWM interface is as follows:

Dsp_pwm_init

Dsp_pwm_cfg

Dsp_pwm_enable

Dsp_pwm_disable

GPIO interface: the GPIO interface is a short term of the IO interface, and the GPIO interface program can output high and low levels in the input/output interface of the DSP, so as to achieve the function of controlling the state of the external device. Meanwhile, the GPIO is configured into an input mode, and the output information of the external equipment can be obtained through the interface, so that the running state of the external equipment is judged, and therefore, the functions of the GPIO interface are packaged as follows:

Dsp_gpio_init

Dsp_gpio_dir_set

Dsp_gpio_read

Dsp_gpio_write

user interface layer:

the user interface layer is a secondary package of the hardware driving layer, and the construction of external functional functions is completed by the secondary package of the hardware driving layer, so that the user program can conveniently carry out integral function call. The user interface layer mainly comprises the following:

system initialization interface 5

The system initialization interface 5 needs to complete the initialization operation of each module in the marine control system according to the requirement, wherein the initialization operation comprises the configuration of SPI interface, the configuration of UART interface, the initialization and the reset of FPGA. Configuration of the ethernet interface, etc., and these operations are all implemented by secondary encapsulation of the hardware layer interface.

UART data transceiver interface 6

The UART data transceiving interface 6 completes the block transmitting and block receiving operations of UART data through the secondary encapsulation of the UART interface.

FPGA management interface 7

The FPGA management interface 7 completes the operation on the peripheral devices hung on the FPGA mainly by secondary packaging of the GPIO interface function and the EMIF interface, and the peripheral devices mainly include: DI. DO, temperature sensor, ADC, alarm, IGBT interface and slave device status.

DAC management interface 8

And the DAC management interface 8 performs secondary packaging on the GPIO function and the SPI function to complete the control of the DAC chip.

Timer management interface 9

The timer management interface 9 is used as a scheduling basis of the system, and needs to complete timer initialization configuration and interrupt processing operation of the timer.

User program layer 1:

the user program is the core of the whole marine control system, and by completing function call to the user interface layer, each logic is combined to finally complete configuration management, peripheral configuration and peripheral monitoring of the whole marine control system according to the requirements of the system.

The user program takes PWM timing interruption as a scheduling basis, the acquisition of the states of all external sensors is completed in each interruption period, and the peripheral equipment needing to be operated at the moment comprises: DI. An ADC, a temperature sensor, a rotary encoder, etc. The user program obtains the output control parameters which should be output at this time according to the related algorithm in the whole operation period, and outputs the output control parameters through the related control interface, thereby achieving the purpose of controlling the whole system.

The operation flow of the whole marine control system is shown in fig. 2: initializing a system, outputting an abnormal warning if the system is abnormal, and ending; if the timer is not abnormal, initializing the timer, and if the timer is abnormal, outputting an abnormal warning and ending; if the timer is initialized and is not abnormal, external parameters, data processing and output control signals are sequentially acquired, the states of all external sensors are acquired in each interrupt period, and if any step is abnormal, the abnormal state is recorded.

Finally, it should be noted that: the embodiments described above are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A marine control system, control software operates in DSP operational environment, its characterized in that: the system comprises a user program layer, a hardware driver and a control module, wherein the user program layer is used for completing data receiving and transmitting of a bottom hardware interface module, registering reading and writing and interrupt processing and the hardware driver;

the user interface layer is used for packaging the bottom hardware interface function, and a function which can be directly called by a user can realize the function which the hardware interface needs to realize, so that a whole set of API is formed;

the user program layer is connected with the user interface layer, and the user interface layer is connected with the hardware driving layer;

the user interface layer comprises a system initialization interface, a UART data receiving and transmitting interface, an FPGA interface management interface, a DAC interface management interface and a timer management interface which are all connected with the user program layer; the user program is based on PWM timed interrupt scheduling, and comprises the following steps: a temperature sensor and a rotary encoder;

the control process of the control system is as follows:

initializing a system, outputting an abnormal warning if the system is abnormal, and ending; if the timer is not abnormal, initializing the timer, and if the timer is abnormal, outputting an abnormal warning and ending; if the timer is initialized and is not abnormal, external parameters, data processing and output control signals are sequentially acquired, the states of all external sensors are acquired in each interrupt period, and if any step is abnormal, the abnormal state is recorded.

2. The marine control system of claim 1, wherein: the user program layer comprises a user program APP.

3. The marine control system of claim 1, wherein: and the FPGA interface management is connected with a DI interface, a DO interface, a temperature sensor interface, an ADC interface, an alarm interface and an IGBT interface.

4. The marine control system of claim 1, wherein: the hardware driving layer comprises a DSP system hardware management module, an SPI interface management module, an EMIF interface management module, a UART interface management module, a PWM interface management module and a GPIO interface management module, wherein the DSP system hardware management module, the EMIF interface management module, the PWM interface management module and the GPIO interface management module are all connected with a system initialization interface, the DSP system hardware management module is connected with a DAC interface management, the EMIF interface management module is also connected with an FPGA interface management, the UART interface management module is connected with a UART data receiving and transmitting interface, the PWM interface management module is connected with a timer management interface, and the GPIO interface management module is connected with the FPGA interface management.