CN111273941A - Marine control system - Google Patents

Marine control system Download PDF

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Publication number
CN111273941A
CN111273941A CN202010050904.0A CN202010050904A CN111273941A CN 111273941 A CN111273941 A CN 111273941A CN 202010050904 A CN202010050904 A CN 202010050904A CN 111273941 A CN111273941 A CN 111273941A
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CN
China
Prior art keywords
interface
hardware
management module
layer
user
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Granted
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CN202010050904.0A
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Chinese (zh)
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CN111273941B (en
Inventor
孙征宇
李丛林
杨兆平
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Sg Prosperous Technology Ltd
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Sg Prosperous Technology Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The invention relates to a marine control system, which comprises a user program layer, a data processing layer and a hardware driver, wherein the user program layer is used for finishing data receiving and sending, registering, reading and writing and interrupt processing of a bottom hardware interface module; the user interface layer is used for packaging a function which can be directly called by a user by a bottom hardware interface function, realizing the function which needs to be realized by the hardware interface and forming a whole set of API; the hardware driving layer integrates the coordination of all hardware modules in the system to complete the system function through a certain scheduling mechanism; the invention completes the configuration management, the peripheral configuration and the peripheral monitoring of the whole marine control system according to the requirements of the system by completing the function call to the user interface layer and combining all logics.

Description

Marine control system
Technical Field
The invention relates to the technical field of control systems, in particular to a marine control system.
Background
As more and more equipment and more complex parts are arranged on the ship, and the requirement cannot be met by simple manual control or single control, a whole set of complete automatic control system is needed to uniformly collect and control the peripheral sensors.
Disclosure of Invention
The invention aims to provide a marine control system.
The purpose of the invention is realized by the following technical scheme: the system comprises a user program layer, a hardware driver and a hardware interface module, wherein the user program layer is used for completing data receiving and sending, registering, reading and interrupting processing and hardware driving of a bottom hardware interface module;
the user interface layer is used for packaging a function which can be directly called by a user by a bottom hardware interface function, realizing the function which needs to be realized by the hardware interface and forming a whole set of API;
the hardware driving layer integrates the coordination of all hardware modules in the system to complete the system function through a certain scheduling mechanism;
the user program layer is connected with the user interface layer, and the user interface layer is connected with the hardware drive layer.
In a preferred embodiment, the user program layer comprises a user program APP.
In a preferred embodiment, the user interface layer includes a system initialization interface, a UART data transceiving interface, an FPGA interface management, a DAC interface management, and a timer management interface, all of which are connected to the user program layer.
In the preferred embodiment, the FPGA interface is connected with a DI interface, a DO interface, a temperature sensor interface, an ADC interface, an alarm interface and an IGBT interface in management.
In a preferred embodiment, the hardware driving layer includes a DSP system hardware management module, an SPI interface management module, an EMIF interface management module, a UART interface management module, a PWM interface management module, and a GPIO interface management module, the DSP system hardware management module, the EMIF interface management module, the PWM interface management module, and the GPIO interface management module are all connected to a system initialization interface, the DSP system hardware management module is connected to a DAC interface management, the EMIF interface management module is further connected to an FPGA interface management, the UART interface management module is connected to a UART data transceiving interface, the PWM interface management module is connected to a timer management interface, and the GPIO interface management module is connected to the FPGA interface management.
The invention has the beneficial effects that: and finally, the configuration management, the peripheral configuration and the peripheral monitoring of the whole marine control system are completed according to the requirements of the system by completing the function call of the user interface layer and combining all logics.
Drawings
The invention is explained in further detail below with reference to the drawing.
FIG. 1 is a system diagram of a marine control system according to an embodiment of the present invention;
fig. 2 is a flow chart illustrating the operation of the marine control system according to the embodiment of the present invention.
In the figure:
1. a user program layer; 2. a user interface layer; 3. a hardware driver layer; 4. a user program APP; 5. a system initialization interface; 6. a UART data transceiving interface; 7. managing an FPGA interface; 8. DAC interface management; 9. a timer management interface; 10. a DSP system hardware management module; 11. an SPI interface management module; 12. an EMIF interface management module; 13. a UART interface management module; 14. a PWM interface management module; 15. a GPIO interface management module; 16. a DI interface; 17. a DO interface; 18. a temperature sensor interface; 19. an ADC interface; 20. an alarm interface; 21. and (4) an IGBT interface.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The invention will be further described with reference to the drawings and specific examples.
As shown in fig. 1, a marine control system according to an embodiment of the present invention includes a user program layer 1, configured to complete data transceiving, register reading, writing, and interrupt processing, and a hardware driver of a bottom hardware interface module;
the user interface layer 2 is used for packaging a function which can be directly called by a user into a bottom hardware interface function, realizing the function which needs to be realized by the hardware interface and forming a whole set of API;
the hardware driving layer 3 integrates the coordination of all hardware modules in the system to complete the system function through a certain scheduling mechanism;
the user program layer 1 is connected with the user interface layer 2, and the user interface layer 2 is connected with the hardware driving layer 3.
The user program layer 1 comprises a user program APP 4.
The user interface layer 2 comprises a system initialization interface 5, a UART data transceiving interface 6, an FPGA interface management 7, a DAC interface management 8 and a timer management interface 9 which are all connected with the user program layer 1.
The FPGA interface management 7 is connected with a DI interface 16, a DO interface 17, a temperature sensor interface 18, an ADC interface 19, an alarm interface 21 and an IGBT interface 21.
The hardware driving layer 3 comprises a DSP system hardware management module 10, an SPI interface management module 11, an EMIF interface management module 12, a UART interface management module 13, a PWM interface management module 14 and a GPIO interface management module 14, the DSP system hardware management module 10, the EMIF interface management module 12, the PWM interface management module 14 and the GPIO interface management module 15 are all connected with the system initialization interface 5, the DSP system hardware management module 10 is connected with the DAC interface management 8, the EMIF interface management module 12 is also connected with the FPGA interface management 7, the UART interface management module 13 is connected with the UART data transceiving interface 6, the PWM interface management module 14 is connected with the timer management interface 9, and the GPIO interface management module 15 is connected with the FPGA interface management 7.
Hardware driver layer 3:
the hardware drive is the only interface for realizing the interaction between the application program and all the peripherals in the equipment, and the control and state monitoring operation of various peripherals in the marine control system can be realized through the hardware interface drive. The marine control system mainly comprises the following hardware interfaces:
DSP hardware management interface: the system is mainly responsible for basic initialization of a DSP (namely a CPU), and the basic initialization of the DSP is completed after the system is powered on, and comprises configuration of a system operation clock, a system RAM and system interrupt. The most basic operation environment is constructed for the later system operation, so the DSP hardware management interface needs to provide the following function interfaces:
Dsp_system_init
Dsp_system_clk_init
Dsp_system_ram_init
Dsp_system_irq_init
SPI interface: a set of SPI communication interface based on three-wire is provided, and peripheral equipment which can realize and meet SPI time sequence requirements is configured to carry out communication, namely, the requirement of data transmission. The SPI driving interface provides parameter configuration, data sending and data receiving functions for the SPI at the bottom layer. The parameter configuration includes configuration of parameters such as clock frequency, data phase, data bit width, interrupt, FIFO, and the like, so the SPI interface driver needs to provide the following interface functions:
Dsp_spi_cfg
Dsp_spi_send
Dsp_spi_recv
Dsp_spi_reset
EMIF interface: the EMIF interface is a set of parallel data transfer interfaces based on data and address buses, through which address buses pass. The data bus and associated control interface enable high-speed data transfer with the peripheral devices. The marine control system is mainly used for realizing data communication of SRAM and FPGA, and the function package of an EMIF interface is as follows:
Dsp_emif_init
Dsp_emif_reset
Dsp_emif_read_reg
Dsp_emif_write_reg
a UART interface: the UART interface mainly realizes data communication with external RS232 equipment, and realizes data transmission and information sharing with the external equipment through the UART interface by configuring the configuration of parameters of baud rate, data bit width, parity check bit and stop bit of the UART interface, so the function package of the UART interface is as follows:
Dsp_uart_init
Dsp_uart_cfg
Dsp_uart_reset
Dsp_uart_read_char
Dsp_uart_send_char
PWM interface: the PWM interface mainly realizes the initialization of a PWM timer in the system and completes the configuration of clock and interrupt parameters in the PWM module. The function for the PWM interface is therefore packaged as follows:
Dsp_pwm_init
Dsp_pwm_cfg
Dsp_pwm_enable
Dsp_pwm_disable
GPIO interface: the GPIO interface is a short form of IO interface, and high and low levels can be output in the input and output interface of the DSP through a GPIO interface program, so that the function of controlling the state of external equipment is achieved. Meanwhile, if the GPIO is configured to be in the input mode, the output information of the external device can be obtained through the interface, so as to determine the operating state of the external device, and therefore, the function package of the GPIO interface is as follows:
Dsp_gpio_init
Dsp_gpio_dir_set
Dsp_gpio_read
Dsp_gpio_write
user interface layer:
the user interface layer is used for secondarily packaging the hardware driving layer, and external functional functions are constructed by packaging the two layers of the hardware driving layer, so that the user program can conveniently carry out integral function calling. The user interface layer mainly comprises the following components:
system initialization interface 5
The system initialization interface 5 needs to complete initialization operations of each module in the marine control system as required, including configuration of an SPI interface, configuration of a UART interface, and initialization and reset of an FPGA. And configuring an Ethernet interface and the like, wherein the operations are realized by secondary packaging of a hardware layer interface.
UART data transceiving interface 6
The UART data transceiving interface 6 completes block transmission and block reception operations of UART data through secondary packaging of the UART interface.
FPGA management interface 7
The FPGA management interface 7 completes the operation of peripheral equipment hung on the FPGA mainly by secondary packaging of GPIO interface functions and EMIF interfaces, and the peripheral equipment mainly comprises: DI. DO, temperature sensor, ADC, alarm, IGBT interface and slave status.
DAC management interface 8
And the DAC management interface 8 carries out secondary packaging on the GPIO function and the SPI function to complete control of the DAC chip.
Timer management interface 9
The timer management interface 9 serves as a scheduling basis of the system, and needs to complete timer initialization configuration and interrupt processing operation of the timer.
User program layer 1:
the user program is the core of the whole ship control system, and the configuration management, the peripheral configuration and the peripheral monitoring of the whole ship control system are completed by combining all logics and finally completing the function call to a user interface layer according to the requirements of the system.
The user program finishes the acquisition of the states of all external sensors in each interrupt period on the basis of PWM timed interrupt serving as a scheduling basis, and the peripheral equipment needing to be operated at the moment comprises: DI. ADC, temperature sensor, rotary encoder and other input sensing devices. In the whole operation period, the user program obtains the output control parameters which should be output at the moment according to the related algorithm, and outputs the output control parameters through the related control interface so as to achieve the purpose of controlling the whole system.
The overall marine control system operation flow is shown in fig. 2: initializing the system, outputting an abnormal warning if the system is abnormal, and ending; if the timer is not abnormal, initializing the timer, if the timer is abnormal, outputting an abnormal warning, and ending; if the timer is initialized and is not abnormal, the external parameters, the data processing and the output control signals are sequentially obtained, the state acquisition of all the external sensors is completed in each interrupt period, and if any step is abnormal, the abnormal state is recorded.
Finally, it should be noted that: the above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (5)

1. A ship control system, in a control software operation and DSP operation environment, is characterized in that: the system comprises a user program layer, a hardware driver and a hardware interface module, wherein the user program layer is used for completing data receiving and sending, registering, reading and interrupting processing and hardware driving of a bottom hardware interface module;
the user interface layer is used for packaging the bottom hardware interface function, and the function which can be directly called by a user can realize the function which needs to be realized by the hardware interface to form a whole set of API;
the hardware driving layer integrates the coordination of all hardware modules in the system to complete the system function through a certain scheduling mechanism;
the user program layer is connected with the user interface layer, and the user interface layer is connected with the hardware drive layer.
2. The marine control system of claim 1, wherein: the user program layer comprises a user program APP.
3. The marine control system of claim 1, wherein: the user interface layer comprises a system initialization interface, a UART data transceiving interface, FPGA interface management, DAC interface management and a timer management interface which are all connected with the user program layer.
4. The marine control system of claim 3, wherein: the FPGA interface management is connected with a DI interface, a DO interface, a temperature sensor interface, an ADC interface, an alarm interface and an IGBT interface.
5. The marine control system of claim 3, wherein: the hardware driving layer comprises a DSP system hardware management module, an SPI interface management module, an EMIF interface management module, a UART interface management module, a PWM interface management module and a GPIO interface management module, the DSP system hardware management module, the EMIF interface management module, the PWM interface management module and the GPIO interface management module are all connected with a system initialization interface, the DSP system hardware management module is connected with a DAC interface management, the EMIF interface management module is also connected with an FPGA interface management, the UART interface management module is connected with a UART data receiving and transmitting interface, the PWM interface management module is connected with a timer management interface, and the GPIO interface management module is connected with the FPGA interface management.
CN202010050904.0A 2020-01-17 2020-01-17 Marine control system Active CN111273941B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100097357A1 (en) * 2008-10-22 2010-04-22 Asustek Computer Inc. Computer and method for controlling external display device
CN104750475A (en) * 2013-12-31 2015-07-01 深圳航天东方红海特卫星有限公司 Micro satellite on-orbit reconstruction frame system and method
CN110413264A (en) * 2019-07-30 2019-11-05 南京市晨枭软件技术有限公司 A kind of software application framework and its configuration unit
CN110515593A (en) * 2019-07-11 2019-11-29 北京机电工程研究所 A kind of aircraft avionics system framework

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100097357A1 (en) * 2008-10-22 2010-04-22 Asustek Computer Inc. Computer and method for controlling external display device
CN104750475A (en) * 2013-12-31 2015-07-01 深圳航天东方红海特卫星有限公司 Micro satellite on-orbit reconstruction frame system and method
CN110515593A (en) * 2019-07-11 2019-11-29 北京机电工程研究所 A kind of aircraft avionics system framework
CN110413264A (en) * 2019-07-30 2019-11-05 南京市晨枭软件技术有限公司 A kind of software application framework and its configuration unit

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