CN1112716A

CN1112716A - Semiconductor memory device

Info

Publication number: CN1112716A
Application number: CN94119568A
Authority: CN
Inventors: 竹内干; 堀口真志; 青木正和; 松野胜己; 阪田健; 卫藤润
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1993-12-22
Filing date: 1994-12-21
Publication date: 1995-11-29
Anticipated expiration: 2014-12-21
Also published as: TW271008B; JPH07182872A; KR950020705A; KR100343646B1; CN1047249C; JP3279025B2

Abstract

The invention relates to a ferroelectric semiconductor memory, in particular to a non-volatile memory which can obtain the nonexistent speed reduction caused by polarization reversion fatigue and can carry out the same treatment with a DRAM. The non-volatile memory, namely the DRAM, is used for reading-out and writing-in generally in the memory provided with a plurality of memory units which are at least composed of a transistor and a ferroelectric capacitor. On the other hand, the polarization direction of the ferroelectric capacitor is checked and the action of the conversion of a node potential of the capacitor is carried out when a power supply is switched on only.

Description

Semiconductor memory device

The present invention relates to the semiconductor memory that adopts ferroelectrics to make, this semiconductor memory can not make speed deterioration and DRAM carry out same processing owing to polarization reversal is tired, be again nonvolatile memory simultaneously.

The storer, the ferroelectric RAM (FERAM: claim ferroelectric memory later on) that use ferroelectrics to make are the nonvolatile memories that utilizes ferroelectric polarised direction to store.But fashionable when reading and writing, along with polarization reversal fatigue takes place after the polarization reversal, speed also can slow down.

On the other hand, had ferroelectric memory and DRAM(dynamic RAM in the past) shared device.This is to be FERAM in the moment of power connection, is DRAM at interlude, then, is the storer of FERAM in the moment of dump.When using as DRAM, do not carry out polarization reversal owing to read to write, so, fatigue can not take place, after using end, return to the FERAM state again, become nonvolatile memory.But in this device, if power supply is cut off etc. and can not reverts to FERAM when just finishing in the process of using as DRAM, then canned data will all disappear, and this is its shortcoming.

Fig. 1 is old example of the dual-purpose storer of ferroelectrics, DRAM.

For example, the spy opens the array structure of the dual-purpose storer of FERAM/DRAM of flat 3-283176 communique record, is exactly structure shown in Figure 1.This array structure is the same with DRAM, and storage unit is made of 1 transistor and 1 capacitor.In order to write non-volatile information to desirable unit, make transistor select conducting state, make electrode and data line conducting of desirable capacitor after, can make data line become 0V or Vcc.

On the other hand, as shown in Figure 1, when using as ferroelectric memory, because plate-line is in the current potential of Vcc/2, thus by selection mode, electric field is applied on the desirable ferroelectric condenser, thus produce and the corresponding polarization of non-volatile information.Polarised direction is ferroelectric characteristic, also can not lose even cut off the electricity supply.At this moment, in the process of the non-volatile information of reading this unit, data line just is in suspended state after being charged to 0V, then, makes transistor pass through the selection mode conducting.As a result, because plate-line is in the current potential of Vcc/2, so, apply electric field to chosen ferroelectric condenser thus.The direction of this electric field is always certain, and ferroelectric polarised direction is corresponding with non-volatile information, keeps original polarised direction constant sometimes, and reversal of poles takes place sometimes.And, when counter-rotating takes place polarised direction, have big electric current to flow into storage unit.As long as utilize, for example, the described method of above-mentioned communique detects this inflow current, just can read non-volatile information.

As shown in the above description, during each reading non-volatile information, because ferroelectric polarised direction all is in same direction, so, must carry out writing again of information.And when being in the store status of reverse polarization, each action of reading all must be through 2 polarization reversals.On the other hand, when carrying out each polarization reversal, deterioration all takes place in ferroelectric capacitor, just can not keep in the time of to the last can not making alive and polarize.Therefore, become the high nonvolatile memory of reliability, preferably reduce the number of times of polarization reversal as far as possible in order to make ferroelectric memory.In addition, another problem is exactly that the counter-rotating that polarizes needs the regular hour, and reading speed is corresponding to slow down so also can make.

As solving, open in the flat 3-283176 communique above-mentioned spy and proposed following method along with the deterioration of polarization reversal ferroelectric film and the problem of reading speed reduction.That is, when being in usual duty, make plate-line become for example Vcc, and using, before cutting off the electricity supply, in the storage of carrying out non-volatile information under the manner of execution of reading of above-mentioned ferroelectric memory as DRAM.If make plate-line become Vcc, no matter the current potential of storage area is 0V or Vcc, information is not reversed, and therefore, can avoid the deterioration problem of ferroelectric condenser, thereby reading speed can not reduce yet.Then, when energized,, just can bring into play the function of nonvolatile memory conscientiously as long as utilize the action of above-mentioned ferroelectric memory to read non-volatile information.

But, in above-mentioned old DRAM, the dual-purpose mode of ferroelectric memory, be when power connection, to become ferroelectric memory, become DRAM then, read and write, read and write after the end, must revert to ferroelectric memory once more, so,, must carry out the mode switch of DRAM and ferroelectric memory consciously for the user of storer, and, aspect the configuration of pin, redundant F/D pin etc. also must be arranged, the result can make complex system.The user is got on very well, the obvious storer that preferably needn't worry about for inner complicated mode switch, this storer has allocation problem and non-volatile surcharge of the using method identical with DRAM, plug.

Purpose of the present invention proposes in order to solve above-mentioned old problem, and purpose aims to provide a kind of semiconductor memory, and this semiconductor memory can have the using method identical with DRAM, pin arrangement and non-volatile.

In addition, another object of the present invention is that a kind of semiconductor memory will be provided, with the structural detail of ferroelectric condenser as storage unit, the degradation of the film of reversal of poles, reduction ferroelectric condenser does not take place, thereby reading speed can not reduce yet with polarization reversal when the information of carrying out is read.

The 3rd purpose of the present invention is to provide a kind of nonvolatile semiconductor memory, the reliability height and the quick action of this semiconductor memory.Running into when cutting off the electricity supply owing to mishap, up-to-date information still can be used as non-volatile information and preserves.

In order to reach above-mentioned each purpose, semiconductor memory of the present invention usually, is that DRAM reads and write activity as volatile memory in the storer that has a plurality of storage unit that are made of 1 transistor and 1 ferroelectric capacitor at least.But plate potential is Vcc/2 at ordinary times not only, and the data line precharge potential when reading is Vcc/2 too.On the other hand, only when power connection, detect the polarised direction of ferroelectric capacitor, be transformed to the action of the current potential of capacitor node.That is, as from non-volatile information to the pattern conversion (ferroelectric memory pattern) of volatile information and move.The switching of DRAM pattern and ferroelectric memory pattern is to utilize the ferroelectric memory-DRAM switching signal that generates in inside to carry out.That is, when power connection, just making above-mentioned switching signal become the level of expression ferroelectric memory pattern when detecting power connection, for example is low level.On the other hand, when from non-volatile information when the conversion of volatile information action has all finished to all storage unit, when detecting this state, just make above-mentioned switching signal become the level of expression DRAM pattern, for example be high level.

In other words, in the present invention, the configuration of pin is the same with DRAM, does not need the F/D pin.In power connection, become ferroelectric memory, under this state, read and write fashionablely, polarization reversal takes place, still, under the control of the switching signal generation circuit of inside, just be transformed to the DRAM pattern automatically.When the DRAM pattern, polarization reversal does not take place in reading course of action, and in the write activity process polarization reversal takes place.And, in the use of DRAM pattern,, also can keep non-volatile information with this moment corresponding 0V of ferroelectric capacitor film polarised direction or Vcc if power supply is cut off.

In the present invention, move with the DRAM pattern usually.So, the polarization reversal when not having information to read, the result does not exist the deterioration of ferroelectric film and the problem that reading speed reduces.Particularly, because plate potential and data line precharge potential are set at Vcc/2, so, when reading, information can obtain above-mentioned effect, on the other hand, when changing the information write state into, rewrite with the corresponding volatile information of capacitor node current potential with as the corresponding non-volatile information of the polarised direction of ferroelectric film with regard to conduct.As a result, the user of this storer needn't worry about for the switching of ferroelectric memory pattern and DRAM pattern, and the signal can be with dump the time is kept in the storer.In addition, when power connection, utilize the inner signal that takes place earlier with the starting of ferroelectric memory pattern, automatically carry out from the conversion of non-volatile information to volatile information, after the conversion release, utilize the inner signal that takes place to make it be converted to the DRAM pattern again.Therefore, the user also needn't worry about for the switching of two kinds of patterns when power connection.That is, according to the present invention, the configuration that can obtain disposal route and pin is identical with DRAM, information read-around number, reading speed and DRAM substantially the same and be non-volatile storer.In other words, the present invention can provide integrated level height, reliability height, quick action and use nonvolatile memory extremely easily.When rewriting action, though with polarization reversal,, the restriction of rewriting number of times is far longer than the restriction of for example being considered 10 in EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) ⁶Inferior, expectation can be greater than 10 ¹¹Inferior, so, in most systems, can use without a doubt.

Fig. 1 is the brief configuration figure of the old dual-purpose storer of ferroelectric memory-DRAM.

Fig. 2 is the wiring diagram of ferroelectric memory pattern/DRAM mode switching signal generation circuit of the present invention the 1st embodiment.

Fig. 3 is the wiring diagram of ferroelectric memory pattern/DRAM mode switching signal generation circuit of the present invention the 2nd embodiment.

Fig. 4 is the wiring diagram of ferroelectric memory pattern/DRAM mode switching signal generation circuit of the present invention the 3rd embodiment.

Fig. 5 is the wiring diagram of ferroelectric memory pattern/DRAM mode switching signal generation circuit of the present invention the 4th embodiment.

Fig. 6 specifies from the time diagram of non-volatile information to an example of the external signal of volatile information conversion when power connection among the present invention.

Fig. 7 is the structural drawing of the ferroelectric memory pattern/DRAM mode switching signal generation circuit of one embodiment of the invention.

Fig. 8 is the output characteristics figure of the voltage detection circuit among Fig. 7.

Fig. 9 is an example of the voltage detection circuit of Fig. 8.

Figure 10 is the structural drawing of the pre-charge circuit of one embodiment of the invention, utilizes the switching mode of ferroelectric memory pattern/DRAM pattern of F/Dsig shown in the figure.

Figure 11 is the structural drawing of the pre-charge circuit of another embodiment of the present invention, utilizes the switching mode of ferroelectric memory pattern/DRAM pattern of F/Dsig shown in the figure.

Figure 12 is the working waveform figure of the memory array of Figure 10 or Figure 11 ferroelectric memory pattern when being listed in power connection.

Figure 13 be the memory cell array of Figure 10 or Figure 11 when retrieval actions finishes from the working waveform figure of ferroelectric memory pattern when the DRAM mode switch.

Figure 14 is the DRAM pattern working waveform figure of the memory array of Figure 10 or Figure 11.

Figure 15 is the working waveform figure of another embodiment of the present invention, shown in the figure from volatile information to the regular mapping mode of non-volatile information.

Below, with reference to the description of drawings embodiments of the invention.

Fig. 2 is the 1st embodiment of ferroelectric memory pattern of the present invention/DRAM mode switching signal method for generation.

As shown in Figure 2, when power connection, ferroelectric memory pattern/DRAM mode switching signal generation circuit F/Dsig.GEN makes mode switching signal F/Dsig become for example low level, and expression is moved with the ferroelectric memory pattern.

At this moment, order conducts interviews to the storage unit of the dual-purpose storer of ferroelectric memory/DRAM, carry out from as the polarised direction of ferroelectric capacitor film and the non-volatile information of storing to conversion as the volatile information of capacitor node current potential, promptly carry out retrieval actions.When above-mentioned retrieval actions finishes, mode switching signal F/Dsig is become, for example, and high level, expression is to carry out work as the DRAM pattern.To the conversion of DRAM pattern, corresponding with the end of retrieval actions, the signal that is taken place by internal control circuit carries out.According to present embodiment, the user of this storer needn't worry about for the switching of ferroelectric memory pattern/DRAM pattern, can obtain to carry out same processing with DRAM, and be non-volatile storer.And, owing to normally use as DRAM, so, there are not the deterioration of ferroelectric film and the problem that read out speed reduces, thereby can obtain reliability height, fireballing nonvolatile memory.

Fig. 3 is the 2nd embodiment of ferroelectric memory pattern of the present invention/DRAM mode switching signal method for generation.

Basically identical with Fig. 2, still, in Fig. 3, show the mode of the part generation of use DRAM control part to the transfer signal of DRAM pattern.Promptly, carrying out the access mode of above-mentioned retrieval actions and for example with the pattern of ferroelectric memory to storage unit, the mode of carrying out automatic more new element with the DRAM pattern is identical, be clock, carry out timing according to the order that makes progress by low order address by utilizing internal address counting device AC according to clock signal generator CLKG.The usefulness of used address counter during the automatic refresh activity of address counter AC in can double as DRAM pattern.When retrieval actions finishes because from the most significant digit output carry signal of AC, so, after above-mentioned commutation circuit receives this carry signal, promptly with this as mode switching signal F/Dsig, the output signal of expression DRAM pattern action takes place, for example high level signal.Also can adopt another kind of mode, promptly when detecting address counter AC and reach maximal value, promptly carry out action to the DRAM mode switch.

In order to prevent from when the retrieval actions to all storage unit does not finish as yet just to take place misoperation to the DRAM mode switch, self-evident, in power connection, address counter to be set at 0, so that the start address of retrieval actions is the address of lowest order.

According to present embodiment, the user of this storer needn't worry about for the ferroelectric memory pattern of inside and the switching of DRAM pattern, thereby can obtain non-volatile and can carry out the storer of the processing mode identical with DRAM.And, owing to normally move with the DRAM pattern, so, and the situation of counter-rotating takes place unlike the polarization that always makes the ferroelectric capacitor film as the ferroelectric memory pattern when the each sense information, so the degree of fatigue of ferroelectric capacitor film very I to obtain the high storer of reliability.

Fig. 4 is the 3rd embodiment of ferroelectric memory pattern of the present invention/DRAM mode switching signal method for generation.

In Fig. 4, whether indication directly exports indicator signal from address counter AC to the signal generating method of the DRAM mode switch place different with Fig. 3, but from the code translator Dec that understands this counting indicator signal is defeated by switching signal generation circuit.For example, new empty low order address DRA is set, after the last low order address of the same retrieval actions of carrying out with Fig. 3, this void low order address DRA takes place when being set in advance in power connection.For example, when carrying out retrieval actions,, make address counter AC action by utilizing the clock of clock signal generator CLKG, utilize low order address code translator RADec from counter output, to read low order address, thereby will activate with corresponding one or more word drivers of this low order address WD.But when occurring already in the empty low order address DRA, promptly to F/Dsig output, the notice retrieval actions finishes.

Usually, read as the DRAM information of carrying out and to write fashionablely, change-over switch is carried out change action, thereby reads in the external address from low order address impact damper RAB.

According to present embodiment, the user of this storer needn't worry about for the ferroelectric memory pattern of inside and the switching of DRAM pattern, can obtain storer non-volatile and that can carry out the processing identical with DRAM.And, because normally as DRAM pattern action, so, the situation that counter-rotating takes place for the polarization of ferroelectric capacitor film is compared, the fatigue of ferroelectric capacitor film is very little, can obtain the high storer of reliability.

Fig. 5 is the 4th embodiment of ferroelectric storage pattern of the present invention/DRAM mode switching signal occurring mode.

In Fig. 5, indication is to occurring mode and Fig. 3 of DRAM mode switch signal, Fig. 4 difference.At first, the same with Fig. 2 when detecting power connection, make the signal of F/Dsig become the ferroelectric memory pattern.Meanwhile, make the timer action of being adorned in the storer.This timer can use the identical circuit used with for example simulating static RAM (SRAM) to constitute.Because the prior needed time of known retrieval actions, so, after the time of adding surplus through this time, utilize the signalisation F/Dsig.GEN retrieval actions of timer output to finish already.The signal of expression DRAM pattern takes place in F/Dsig.GEN after receiving this signal.The user in time, utilize by the decision of this timer signal RFSH as specificator end of input retrieval actions and in this time not the information of carrying out read and write activity.Signal RFSH also can generate in inside in advance automatically, at this moment, because the needed time of retrieval actions determines when carrying out circuit design, so it is irrelevant with user's intention, therefore can determine to take place the timing of DRAM mode designating signal in view of the above by timer, according to embodiments of the invention, can obtain and Fig. 3 and the described identical effect of Fig. 4.

Fig. 6 is in the embodiments of figure 3 in order to carry out from the conversion of non-volatile information to volatile information when the power connection, i.e. retrieval actions, and should be from the time diagram of external input signal.

During power connection, making chip non-select signal CE liner is high level.Behind the power connection, be in holding state reach the time T (Wait) of steady state (SS) at memory inside voltage during.During this period, F/Dsig stably becomes low level, promptly becomes the state that switches to the ferroelectric storage pattern, and plate potential, word line potential, data line current potential etc. become the original state that is determined respectively.When having passed through time T (Wait), just N(row) the inferior renewal actuating signal RFSH that imported.But to be in low level state corresponding with F/Dsig, and RFSH moves as the retrieval actions signal.Among the figure, be N(row) to all storage unit needed number of times that conducts interviews.RFSH can import from the outside, also can be produced by inside.N(row) the back edge of inferior RFSH signal makes address counter return 0 from maximal value, and carry signal takes place.As illustrated in fig. 3, this carry signal becomes the signal that the expression retrieval actions finishes, and makes F/Dsig become high level.Afterwards through the needed time T of this a series of retrieval actions (Start), make the CE liner become low level, allow that it carries out reading and writing of information according to the identical method of DRAM.

The time T of reading and writing (start) of prohibition information also can be used as explanation and is provided by the user, and still, when F/Dsig only limited to represent the DRAM pattern, the user also can carry out access to this storer.That is, in the ferroelectric memory pattern, for example can ban use of the identifier of storer from certain pin output of this storer.On the other hand, the same with common DRAM during power connection, must carry out more new element.This action is undertaken by importing above-mentioned RFSH signal, and to be in high level state corresponding with F/Dsig, and RFSH acts on as update signal.SRAM is the same with simulation, carries out new element at regular intervals in memory inside, and the user can treat it fully as nonvolatile memory.In addition, F/Dsig is from the variation of low level to high level, also can with N(row)+1 time RFSH signal carries out accordingly.

In addition, as another kind of method,, can use timer behind certain hour, to change F/Dsig automatically as illustrated in fig. 5.According to present embodiment, the user of this storer only when power connection, carry out with DRAM in the signal that automatically more new element is identical input, can obtain carrying out the nonvolatile memory of the processing mode identical with DRAM.In addition, because can be with the RFSH signal as using with the corresponding renewal actuating signal of F/Dsig signal and two kinds of purposes of retrieval actions signal of memory inside generation, so, can obtain the nonvolatile memory that the pin arrangement mode is identical with DRAM and disposal route is identical with DRAM.In addition, when the information of carrying out is read, the polarization of ferroelectric capacitor film is reversed at every turn, thereby can obtain film degree of fatigue nonvolatile memory very little, that reliability is high.

Fig. 7 is the structural drawing of the ferroelectric memory pattern/DRAM mode switch circuit of one embodiment of the invention, and Fig. 8 is the output characteristics figure of the voltage detection circuit among Fig. 7, and Fig. 9 is the detailed structure view of the voltage detection circuit among Fig. 7.

Mode switch circuit F/Dsig.GEN among Fig. 7 comprises voltage detection circuit VccDet, and in addition, voltage detection circuit VccDet has output characteristics shown in Figure 8.The output of voltage detection circuit VccDet was almost 0 before supply voltage reaches certain value, consistent with supply voltage after greater than certain value, the needed minimum voltage of this certain value access to memory operating stably.

In Fig. 9, illustrate by the fixed resistance that is connected with the lower end of power source voltage Vcc and node VN8 and 3 N type tunnel field-effect transistors that are connected in series and 3 phase inverter INVA being connected in series, B, the voltage detection circuit that C constitutes.

When power connection, the current potential of node VN8 rises gradually, and when about 3 times of the threshold voltage vt h that reaches 3 N type tunnel field-effect transistors that are connected in series, they begin conducting.Compare with the resistance of Vcc one side, design very for a short time by the conducting resistance with these 3 N type tunnel field-effect transistors, the amount of boost of the current potential of the node VN8 that the Vcc power supply causes reduces rapidly when above reaching 3 * Vth, presents saturated trend.

Therefore, supply voltage began to rise to above 6 * Vth from 0V near, the output of phase inverter INVA was reversed to high level from low level.By with 3 phase inverter INVA, INVB, INVC connect into tunnel width and arrive the wide more state of back level more, just can realize running through the voltage detection circuit that electric current is little, driving force is big.By such voltage detection circuit is set, corresponding with power connection as shown below, stably emergence pattern switches the F/Dsig signal.

In Fig. 7, when supply voltage surpasses above-mentioned certain value, VccDet output rises to supply voltage, reach cut-off state with the N type tunnel field-effect transistor that Vcc is connected with delay circuit, the node on one side of trigger circuit (1) boosts by capacitor C6A, so the node (2) of a side of output F/Dsig signal is locked as 0V.As the effect that voltage detection circuit VccDet is set, after trigger circuit reach the voltage of operating stably, the trigger circuit conducting, the boosting of node (1) on the one side by capacitor carried out rapidly, so the node (2) of a side of output F/Dsig signal is stabilized in 0V.

On the other hand, when retrieval actions finishes, become low level from the DRAM mode designating signal of control circuit output, trigger circuit are locked as the node (1) of a side of Vcc current potential owing to 0V is reduced in the conducting of N type tunnel field-effect transistor.As a result, the F/Dsig signal becomes high level, and storer becomes the DRAM pattern.When trigger circuit node (1) on one side boosted by capacitor C6A when power connection, DRAM mode designating signal line was suppressed by capacitor C6B, can not cause that current potential raises owing to stray capacitance coupling etc.Like this, during making that trigger circuit node (1) on one side boosts, can prevent that DRAM mode designating signal line current potential mistake from rising and cause that the conducting of N type tunnel field-effect transistor produces misoperation.The F/Dsig signal becomes after the high level, and soon, DRAM mode designating signal line just drops to 0V.Like this, just, the residual current potential higher than 0V causes misoperation on can preventing when power connection next time owing to DRAM mode designating signal line.

According to the embodiment of Fig. 7～Fig. 9, corresponding with power connection, the ferroelectric memory mode signal can take place in inside, corresponding with the retrieval actions end, the DRAM mode signal can take place.Therefore, the user of this storer needn't need to distinguish that memory inside is to use or use as the DRAM pattern as the ferroelectric memory pattern, thereby can use as the nonvolatile memory with the signalizing activity identical with DRAM at an easy rate.And, because usually with DRAM pattern action,, thereby can obtain the high storer of reliability so accompanying information is read and the film degree of fatigue of the ferroelectric capacitor that causes is very little.

Figure 10 is the structural drawing of the memory array of one embodiment of the invention.

In Figure 10, be respectively equipped with the Vcc/2 pre-charge circuit and the Vss pre-charge circuit of same structure at the data line that is connected with storage unit and the two ends of the sensing circuit of the signal that amplifies these data lines, be connected by utilizing the F/Dsig signal to switch to, simply the pattern of switchable memory with some pre-charge circuits.As shown in figure 10, array structure and common DRAM are substantially the same.But the capacitor films of storage unit is to be made of ferroelectrics, when power connection, preserves non-volatile information with the direction of ferroelectrics spontaneous polarization.After power connection, this non-volatile information is transformed to the node SN9(i as data line one side of capacitor, and the j) volatile information of the current potential of Denging then, is carried out the action identical with DRAM.In Figure 10, constitute 1 storage unit by 2 transistors and 2 capacitors, set the polarised direction and the node potential of 2 capacitors, utilize differential reading-out amplifying SA9(j auxiliaryly) etc. detection.Certainly, also can equally with DRAM constitute storage unit by 1 capacitor and 1 transistor.At this moment, owing to only when the ferroelectric memory pattern, need imaginary unit, so, utilize F/Dsig to switch, so that become activated state, when the DRAM pattern, become inactive state at ferroelectric memory pattern imaginary unit.

In Figure 10, when F/Dsig is low level, promptly when being in the ferroelectric memory pattern, sensor amplifier SA9(j) etc. drive wire and data line DL9(j etc. drive wire and data line DL9(j)) etc. pre-charge level is 0V.On the other hand, etc. drive wire and data line DL9(j when F/Dsig is high level, promptly when being in the DRAM pattern, sensor amplifier SA9(j)) etc. pre-charge level is Vcc/2.

Above-mentioned action is the level according to F/Dsig, by with precharging signal line PCL9 and 0V pre-charge circuit PCVS9(j) etc. or Vcc/2 pre-charge circuit PCHD9(j) wait a circuit among both to carry out after being connected.If use this memory array organization, then as described later shown in the action waveforms of Figure 12 and Figure 14 like that, in the ferroelectric memory pattern,, can carry out according to moving identical action with DRAM common in the DRAM pattern from the conversion of non-volatile information to volatile information.

That is, according to present embodiment, the pattern of utilizing very simple circuit configuration and circuit operation just can carry out F/Dsig is switched.And, usually, as carrying out precharge DRAM action effect with Vcc/2 pole plate, Vcc/2 data line, accompanying information is read, polarization reversal does not take place in the ferroelectric capacitor film, so, can avoid following polarization reversal and the film that causes is tired and the problem of reading speed reduction.In addition; because the current potential of capacitor node and the polarised direction of ferroelectric capacitor film are in state in correspondence with each other always; so; needn't be for take to protect the measure of action to the non-volatile information conversion from volatile information; even dump also can keep information, thereby can obtain the strong storer of anti-power supply accidental amputation ability.

Figure 11 is can be the same with Figure 10, utilizes the F/Dsig signal to change the memory array organization figure of the pattern of storer simply.

In Figure 11 and Figure 10 difference be: pre-charge circuit PC9(j) when 0V precharge and public in the Vcc/2 precharge, utilize F/Dsig will provide the power lead of pre-charge level to switch to 0V(Vss) or Vcc/2.

According to present embodiment, except having the effect identical with Figure 10 since with pre-charge circuit as public, so, can make memory array realize higher densityization.In Figure 10 and Figure 11, when the ferroelectric memory pattern, can certainly carry out Vcc precharge.

Figure 12 be in the memory array of Figure 10 or Figure 11 during power connection in the ferroelectric memory pattern from the time diagram of non-volatile information to the action waveforms of volatile information conversion.

At first, the same with common DRAM when power connection, plate potential PL9 becomes the Vcc/2 level.During this period, because word line WL9(o) etc. current potential be suppressed to OV, so, follow the rising of PL9, the node SN9(o of data line one side of ferroelectric capacitor, j), SN9(o, j) current potential of B etc. also rises near Vcc/2.

Because SN9(o, j), SN9(o, j) B etc. is in suspended state, so ferroelectric capacitor can not rise and apply bigger voltage along with PL9, therefore, can be not destroyed as the non-volatile information of the polarised direction of film.

On the other hand, become high level with precharging signal line PCL9, F/Dsig becomes the corresponding sensor amplifier SA9(j of low level) etc. drive wire and data line DL9(j) etc. be pre-charged to 0V.Address counter is initially set O, and each signal wire, power lead and address counter begin retrieval actions shown in Figure 6 being stabilized in the moment t1 of above-mentioned original state.

That is, be under the state of high level at chip non-select signal CE liner, make signal RF-SH become high level.After receiving this signal, signal wire PCL9 becomes low level, and data line becomes the suspended state of 0V.Then, with word line, WL9(o for example), be set at the current potential Vch higher than Vcc.

Because data line DL9(j), DL9(j) current potential of B etc. is 0V, capacitor node SN9(o, j), SN9(o, j) B etc. is in the current potential near Vcc/2, so, according to the ratio of electric capacity with the electric capacity of data line stray capacitance of capacitor, the data line current potential rises to the intermediate value of 0V and Vcc/2.At this moment, because the polarised direction of 2 complementary electrical containers is opposite, so data line is to DL9(j), DL9(j) difference appears in the current potential of B etc.Its reason is Vcc/2 with regard to the current potential that is pole plate PL9, and it is identical to be added in 2 directions of an electric field on the capacitor, and polarised direction tends to same direction at last.For the capacitor that polarization reversal takes place, will flow into unnecessary, in order to compensating the electric charge of this polarization charge, thereby the effective capacitance amount will increase.Therefore, the current potential of the data line that is connected with the capacitor that polarization reversal takes place just more is connected to Vcc/2.When the current potential generation small electric potential difference of complementary data line, just can utilize differential reading-out amplifying SA9(j) etc. detect.That is, drive wire SAP9 is driven to Vcc, the data line current potential is enlarged into 0V and Vcc.Make word line WL9(o if amplify the back) current potential get back to 0V, at capacitor node SN9(o, j), SN9(o, just j) B etc. locate to keep with power connection before the corresponding 0V of capacitor films polarised direction or the volatile information of Vcc.

At last, make the current potential of sensor amplifier drive wire SAP9 etc. get back to 0V.Like this, to 1 word line WL9(o) retrieval actions of the storage unit that is connected just finishes at moment t2.When RFSH got back to low level, address counter was finished counting.Then, when making RFSH become high level, with among the DRAM more new element is the same automatically, select next word line WL9(1), carry out and WL9(1) retrieval actions of the storage unit that is connected.Like this, as long as all storage unit were all carried out retrieval actions, promptly come to an end from the conversion of non-volatile information to volatile information.Produce leakage current owing to carry out the current potential of capacitor node of the storage unit of retrieval actions at last, the result is from reducing gradually near the Vcc/2, but, the needed time of retrieval actions with automatically the more needed time of new element roughly the same, less than DRAM do not carry out new element more can keep information time 1/100, because the time is very short, so, no problem in the action.

According to the present invention, owing to only carry out behind the power connection just can finishing retrieval actions with the step that more new element is identical automatically of DRAM, so, nonvolatile memory very easy to use can be obtained.

Figure 13 is from the time diagram of ferroelectric memory pattern to the conversion regime of DRAM pattern when retrieval actions finishes in the memory array of Figure 10 or Figure 11.

When to last 1 word line WL9(n) when the retrieval actions of the storage unit that is connected finishes, WL9(n) get back to low level.Then, precharging signal line PCL9 becomes high level.At this moment because storer also is in the ferroelectric memory pattern, so, to sensor amplifier drive wire SAP9, SAN9 and data line to DL9(j), DL9(j) B is pre-charged to 0V(Vss).When making RFSH get back to low level after retrieval actions finishes, address counter AC returns 0 from maximal value.As a result, after receiving the carry signal of generation, F/Dsig becomes high level from low level, and storer is the DRAM pattern from the ferroelectric memory mode shifts.And sensor amplifier drive wire SAP9, SAN9 and data line are to DL9(j), DL9(j) B is pre-charged to Vcc/2 once more.Then, carry out action, make the CE liner become low level, allow reading and writing of the information of carrying out as DRAM.

According to present embodiment, owing to can carry out automatically from of the switching of ferroelectric memory pattern to the DRAM pattern, so, for the user of this storer in fact, can obtain nonvolatile memory very easy to use.

Figure 14 is the time diagram of the action waveforms of the DRAM pattern when conduct is moved usually in the memory array of Figure 10 or Figure 11.

The high level that is expressed as the DRAM pattern with F/Dsig is corresponding, and drive wire SAP9, the SAN9 of sensor amplifier and data line are to DL9(j), DL9(j) B etc. is pre-charged to Vcc/2.For the information of carrying out is read action, at first make pre-charge line PCL become low level, make SAP9, SAN9 and DL9(j), DL9(j) B etc. becomes suspended state.Then, make word line, for example WL9(i), become the current potential Vch higher than Vcc.As a result, with capacitor node SN9(i, j), SN9(i, j) current potential that keeps such as B accordingly, the right current potential of data line produces the small electric potential difference.By making switch S APW9, SANW9 conducting drive sensor amplifier SA9(j) etc., this potential difference (PD) is enlarged into Vcc and 0V.Then, by making Y selecting line YS9(j) etc. conducting, can be from output line IO9, IO9B sense information.In addition, in order to carry out information rewriting,, utilize the input of IO9, IO9B that sensor amplifier is reversed in this stage.Like this, the capacitor node current potential just carries out consistent counter-rotating simultaneously with the capacitor films polarised direction.In order to make release, make word line WL9(i) get back to low level after, make precharging signal line PCL9 get back to high level, make drive wire SAP9, the SAN9 of sensor amplifier and data line to DL9(j), DL9(j) B etc. gets back to the level of Vcc/2.

By above-mentioned a series of action waveforms as can be known, except F/Dsig became high level, the situation of the ferroelectric memory pattern of the input of signal and Figure 12 was identical.Automatically refresh activity also only makes RFSH become high level automatically when F/Dsig becomes high level.According to above Figure 10～various embodiments of the present invention shown in Figure 14, only be provided with the internal circuit of corresponding generation ferroelectric memory pattern/DRAM mode switching signal F/Dsig such as power connection and with so very simple circuit such as on-off circuit of the pre-charge level of the corresponding change data line of F/Dsig etc., so, user for this storer gets on very well, and can obtain carrying out the nonvolatile memory of the processing mode identical with DRAM.And, usually, as the effect of moving with Vcc/2 pole plate, the precharge DRAM of Vcc/2 data line, ferroelectric capacitor film not accompanying information is read and polarization reversal is taken place, and therefore can avoid following polarization reversal and problem that the film deterioration that causes and reading speed reduce.In addition, because the polarised direction of the current potential of capacitor node and ferroelectric capacitor film always in correspondence with each other, so, need be for adopting other actions in addition to the non-volatile information conversion from volatile information, even dump also can be preserved information, thereby can obtain the strong storer of anti-power supply accidental amputation ability.That is,, can obtain designing easy, reliability nonvolatile memory high, easy to use according to embodiment, in Figure 10～Figure 14, the method that data line etc. is pre-charged to OV when the ferroelectric memory pattern has been described, still, also can have adopted the method that is pre-charged to Vcc.In addition, though be the explanation of adopting the mode make pole plate become Vcc/2 to carry out in Figure 10～Figure 14.But, when in the ferroelectric memory pattern, using the old mode of driving stage printed line or in the DRAM pattern, making pole plate become the old mode of Vcc or Vss, adopt among the present invention with power connection etc. corresponding in internal circuit the method for generation ferroelectric memory pattern/DRAM mode switching signal F/Dsig also be effective.

Figure 15 is the action time figure of another embodiment of the present invention, is by separately using ferroelectric memory pattern and DRAM pattern can obtain the method for the high nonvolatile memory of reliability.That is, between as the DRAM pattern operating period, for example when carrying out more new element etc.,, only in the of short duration time, become the ferroelectric memory pattern every a certain certain cycle.Like this, just, can reduce the number of times of polarization reversal.

As shown in figure 15, when using, make plate-line PL14(i as the DRAM pattern) voltage be Vcc or Vss.As a result,, also can only rewrite volatile information, not change as the non-volatile information of the polarised direction of ferroelectric capacitor as node potential even carry out information rewriting.Therefore, there is not the film deterioration problem of following the polarization reversal when rewriting to cause.But like this, volatile information just can not be corresponding one by one with non-volatile information, so, periodically carry out from the conversion of volatile information to non-volatile information.That is, when in the DRAM pattern, carrying out refresh activity, with data line DL14(j) etc. current potential amplify, carry out stage of rewriting again of volatile information, make plate-line PL14(i) current potential from Vcc(or Vss) become Vcc/2.Perhaps also can make PL14(i) become Vss from Vcc.Like this, just direction and the corresponding electric field of volatile information can be applied on the ferroelectric capacitor, non-volatile information just is stored with polarised direction.Like this from the conversion of volatile information to non-volatile information, not necessarily when carrying out refresh activity, all must carry out at every turn, also can be undertaken by the suitable cycle.In order to prevent that volatile information from following plate-line to drive and destroyed, plate-line is not public to all storage unit, is separated into word line unit.According to embodiments of the invention, can reduce the polarization reversal number of times, thereby can obtain the higher nonvolatile memory of reliability.

As mentioned above, according to the present invention, the configuration mode restriction also identical, the information read-around number that can obtain carrying out the processing identical with DRAM, pin is all identical with DRAM with read out speed, and is non-volatile storer.

Claims

1, semiconductor memory, it is characterized in that: have at least 1 to be to be the capacitor of dielectric film and the storage unit that field effect transistor constitutes with the ferroelectrics in the memory cell matrix that on the intersection point of data line and word line, is configured to, said memory cells has the ferroelectric memory pattern of the polarised direction canned data of utilizing ferroelectric film and utilizes the dynamic RAM pattern (DRAM) of capacitor node potential canned data on one side, and the commutation circuit that comprises the switching signal of above-mentioned 2 patterns that are used to switch, this commutation circuit detects after storer begins supply power, above-mentioned switching signal is set at the 1st state of expression ferroelectric memory pattern, then, above-mentioned switching signal is set at the 2nd state of the expression DRAM pattern different with above-mentioned the 1st state.

2, the described semiconductor memory of claim 1, it is characterized in that: in above-mentioned ferroelectric memory pattern, the signal that utilizes inner control circuit to take place, desirable storage unit is retrieved, by retrieval actions, make it be transformed to volatile information automatically as capacitor node potential on one side by non-volatile information as the polarised direction of ferroelectric film.

3, the described semiconductor memory of claim 1, it is characterized in that: in above-mentioned ferroelectric memory pattern, with corresponding from the input signal of outside input, at least a portion storage unit is retrieved, according to retrieval, make it be transformed to volatile information as capacitor node potential on one side by non-volatile information as the polarised direction of ferroelectric film.

4, the described semiconductor memory of claim 2, it is characterized in that: the ferroelectric memory pattern described in the claim 1 is in basis begins from the power supply supply, carries out automatically through the signal that utilizes timer internal to send behind the certain hour to the switching of DRAM pattern.

5, claim 2 or 3 described semiconductor memories is characterized in that: the ferroelectric memory pattern described in the claim 1 is to have entered specified states according to the counter that detects inside to carry out afterwards to the switching of DRAM pattern.

6, the described semiconductor memory of claim 5 is characterized in that: the described ferroelectric memory pattern of claim 1 is carried out after most significant digit is carried out carry according to detecting above-mentioned internal counter to the switching of DRAM pattern.

7, the described semiconductor memory of claim 3 is characterized in that: utilize the outside signal of supplying with, when making above-mentioned switching signal be in above-mentioned the 1st state, carry out and the corresponding above-mentioned retrieval actions of said external signal; When being in above-mentioned the 2nd state, carry out new element more with the corresponding common DRAM of said external signal.

8, the described semiconductor memory of claim 1, it is characterized in that: have pre-charging device, in above-mentioned DRAM pattern, data line is carried out precharge, make its reach with corresponding 2 current potentials of 2 value canned datas of storage unit roughly in the middle of current potential, and in above-mentioned ferroelectric memory pattern, data line is carried out precharge, make it reach the current potential different with above-mentioned intermediate potential.

9, the described semiconductor memory of claim 8, it is characterized in that: the plate potential of above-mentioned capacitor is fixed as above-mentioned intermediate potential at least in the DRAM pattern.

10, the described semiconductor memory of claim 8 is characterized in that: have device from above-mentioned intermediate potential to the pole plate of above-mentioned capacitor that supply with.

11, the described semiconductor memory of claim 1 is characterized in that: make imaginary unit be in the activate state in above-mentioned ferroelectric memory pattern, in above-mentioned DRAM unit, make imaginary unit return to the deactivation state.

12, semiconductor memory, it is characterized in that: on the intersection point of data line and word line, be configured to have at least in the storage unit of matrix 1 to be to be capacitor and 1 storage unit that field effect transistor constitutes of dielectric film with the ferroelectrics, said memory cells has the ferroelectric memory pattern of the polarised direction canned data of utilizing ferroelectric film and utilizes the DRAM pattern of capacitor node potential canned data on one side, in this DRAM pattern, for pole plate at the above-mentioned node opposite side of ferroelectric capacitor, usually supply with 2 current potentials that are worth in corresponding 2 current potentials of canned datas with storage unit, during certain, supply with the roughly intermediate potential of above-mentioned 2 current potentials.