CN111246130B - Memory cell array, quantization circuit array and read control method thereof - Google Patents
Memory cell array, quantization circuit array and read control method thereof Download PDFInfo
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- CN111246130B CN111246130B CN202010049523.0A CN202010049523A CN111246130B CN 111246130 B CN111246130 B CN 111246130B CN 202010049523 A CN202010049523 A CN 202010049523A CN 111246130 B CN111246130 B CN 111246130B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
A memory cell array, a quantization circuit array and a read control method thereof, the memory cell array includes: the pixel unit groups are arranged in rows and columns, each pixel unit group comprises a single column of 4n rows of pixel units, and n is a positive integer greater than or equal to 1; each pixel unit group is coupled with 2n pixel signal lines, the 2n pixel signal lines are respectively and sequentially coupled with pixel units in each row in the pixel unit group, and the pixel unit groups comprising the same row of pixel units are coupled with the same 2n pixel signal lines; each pixel cell group includes: and 2n merging control switches, each merging control switch being coupled to the storage nodes of the 2 x-th row of pixel units and the storage nodes of the 2x + 1-th row of pixel units in the pixel unit group, wherein x is an integer greater than or equal to 0 and less than 2 n. The technical scheme of the invention can realize the merging and reading of the pixel signals.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a memory cell array, a quantization circuit array, and a read control method thereof.
Background
A Complementary Metal Oxide Semiconductor (CMOS) image sensor usually has only one pixel signal line in each column, and each row of pixels is connected to the signal line in each column through a row selection MOS transistor, and when reading, the signal lines in each row are sequentially gated for analog-to-digital conversion and read.
In order to increase the frame rate and increase the readout speed, a plurality of pixel signal lines may be integrated in one column while performing quantization readout on a plurality of rows of pixels.
However, under specific application requirements, two-row merged read-out is required. At present, no solution for cache multi-signal line merging and reading exists.
Disclosure of Invention
The technical problem solved by the invention is how to realize the merging and reading of pixel signals.
To solve the above technical problem, an embodiment of the present invention provides a memory cell array, including: the pixel unit groups are arranged in rows and columns, each pixel unit group comprises a single column of 4n rows of pixel units, and n is a positive integer greater than or equal to 1; each pixel unit group is coupled with 2n pixel signal lines, the 2n pixel signal lines are respectively and sequentially coupled with pixel units in each row in the pixel unit group, and the pixel unit groups comprising the same row of pixel units are coupled with the same 2n pixel signal lines; each pixel cell group includes: and 2n merging control switches, each merging control switch being coupled to the storage nodes of the 2 x-th row of pixel units and the storage nodes of the 2x + 1-th row of pixel units in the pixel unit group, wherein x is an integer greater than or equal to 0 and less than 2 n.
Optionally, the merge control switch includes: and the source electrode and the drain electrode of the MOS tube are respectively coupled with the storage node of the 2x row pixel unit and the storage node of the 2x +1 row pixel unit in the pixel unit group, and the grid electrode of the MOS tube is connected with a merging control signal.
Optionally, each pixel unit group further includes: one end of each row selecting switch is coupled with one row of pixel units, the other end of each row selecting switch coupled with the m-th row or the m +2 n-th row of pixel units is coupled with the m-th pixel signal line, and m is an integer which is more than or equal to 0 and less than 2 n.
In order to solve the above technical problem, an embodiment of the present invention further discloses a quantization circuit array based on the memory cell array, where the quantization circuit array includes: each pixel signal line blp (y) is coupled to the p + y × 2n row quantization circuit, each quantization circuit is used for gating the pixel signal line coupled thereto, blp (y) represents the p pixel signal line coupled to the y row pixel unit, y is an integer greater than or equal to 0, and p is an integer greater than or equal to 0 and less than 2 n.
In order to solve the above technical problem, an embodiment of the present invention further discloses a read control method based on the quantization circuit array, where the read control method includes: receiving a column address strobe signal; and controlling the multi-column quantization circuit to gate each pixel signal line in sequence according to the column address gating signal so as to output pixels formed by combining the 2x row pixel units and the 2x +1 row pixel units.
Optionally, the controlling, according to the column address gating signal, the multiple columns of quantization circuits to gate the pixel signal lines in sequence includes: and controlling the multi-column quantization circuit to gate 2q + yx 2n pixel signal lines in sequence according to the column address gating signal, and then gating 2q +1+ yx 2n in sequence, wherein q is a positive integer which is greater than or equal to 0 and less than n.
Optionally, the controlling, according to the column address strobe signal, the multiple columns of quantization circuits to sequentially strobe 2q + y × 2n pixel signal lines includes: selecting a q value according to the low-to-high value of q, and controlling the multi-column quantization circuit to gate pixel signal lines according to the low-to-high value of y under the selected q value according to the column address gating signal.
The embodiment of the invention also discloses a storage medium, wherein a computer instruction is stored on the storage medium, and the steps of the reading control method are executed when the computer instruction runs.
The embodiment of the invention also discloses an image sensor which comprises the storage unit array or the quantization circuit array.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the technical solution of the present invention, each pixel unit group in the memory cell array includes a single row of 4n rows of pixel units, each pixel unit group is coupled to 2n pixel signal lines, and each pixel unit group includes: each merging control switch is coupled with the storage node of the 2x row pixel unit and the storage node of the 2x +1 row pixel unit in the pixel unit group, the merging control switches can control the storage nodes of the 2x row pixel unit and the storage nodes of the 2x +1 row pixel unit in the pixel unit group to be merged, pixel signals can be read out after merging by controlling and gating corresponding pixel signal lines, the frame rate is doubled when merging and reading compared with non-merging reading, the frame rate of pixel reading is improved, and the reading speed of the image sensor is improved.
Further, receiving a column address strobe signal; and controlling the multi-column quantization circuit to sequentially gate and output the pixels formed by combining the 2x row pixel unit and the 2x +1 row pixel unit according to the column address gating signal. According to the technical scheme, data sequence rearrangement can be realized without an additional buffer, so that the pixel signals of multiple lines are read out in the line sequence, and the subsequent image system can conveniently read the signals.
Drawings
FIG. 1 is a schematic structural diagram of a memory cell array according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory cell array according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a quantization circuit array according to an embodiment of the present invention;
FIG. 4 is a flowchart of a read control method for a quantized circuit array according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating timing control signals according to an embodiment of the invention.
Detailed Description
As described in the background, under certain application requirements, a two-row merged read-out is required. At present, no solution for cache multi-signal line merging and reading exists.
In the technical solution of the present invention, each pixel unit group in the memory cell array includes a single row of 4n rows of pixel units, each pixel unit group is coupled to 2n pixel signal lines, and each pixel unit group includes: each merging control switch is coupled with the storage node of the 2x row pixel unit and the storage node of the 2x +1 row pixel unit in the pixel unit group, the merging control switches can control the storage nodes of the 2x row pixel unit and the storage nodes of the 2x +1 row pixel unit in the pixel unit group to be merged, pixel signals can be read out after merging by controlling and gating corresponding pixel signal lines, the frame rate is doubled when merging and reading compared with non-merging reading, the frame rate of pixel reading is improved, and the reading speed of the image sensor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic structural diagram of a memory cell array according to an embodiment of the invention.
Referring to fig. 1, the memory cell array may include a plurality of pixel cell groups 101 arranged in rows and columns, where each pixel cell group 101 includes a single column of 4n rows of pixel cells 1011. Fig. 1 shows a case where n is 2, that is, the pixel unit group 101 includes a single column of 8 rows of pixel units 1011, and so on, which is not limited by the embodiment of the present invention.
In this embodiment, x has a value ranging from 0 to 2 n-1.
The memory cell array shown in fig. 1 further includes a plurality of pixel signal lines BL, wherein each pixel unit group 101 is coupled to 2n pixel signal lines, the 2n pixel signal lines are respectively coupled to the pixel units 1011 in each row of the pixel unit group 101 in sequence, and a plurality of pixel unit groups 101 including the pixel units 1011 in the same row are coupled to the same 2n pixel signal lines.
Specifically, the number of pixel signal lines in the memory cell array is determined by the number y of columns of pixel units included in the memory cell, that is, the number of pixel signal lines in the memory cell array is 2n × y, and y is a positive integer greater than or equal to 1.
Fig. 1 shows a case where n is 2, that is, each pixel cell group 101 in the memory cell array is coupled to 4 pixel signal lines, which are BL0, BL1, BL2, and BL 3; the pixel unit group 101 including the 0 th column of pixel units 1011 is coupled to the same 4 pixel signal lines BL0, BL1, BL2 and BL3, and the pixel unit group 101 including the 1 st column of pixel units 1011 is coupled to the same 4 pixel signal lines BL0, BL1, BL2 and BL3 (not shown) ….
Each pixel cell group 101 shown in fig. 1 includes 2n binning control switches 1012, and each binning control switch 1012 couples the storage nodes of the 2x row of pixel cells and the storage nodes of the 2x +1 row of pixel cells in the pixel cell group 101. Since the storage node of each row of pixel units is used for outputting the pixel signals of the row of pixels, the combination of the pixel signals of two rows of pixels can be realized by the combination control switch 1012.
Specifically, when the binning readout is required, the binning control switch 1012 is turned on, so that the pixel signals of the two rows of pixels are binned.
According to the embodiment of the invention, the merging control switch can control the pixel signals at the storage nodes of the 2x row pixel units and the storage nodes of the 2x +1 row pixel units in the pixel unit group to be merged, and the reading of the pixels after merging is realized by controlling and gating the corresponding pixel signal lines, the frame rate during merging reading is doubled compared with that during non-merging reading, the frame rate of pixel reading is improved, and the reading speed of the image sensor is improved.
In a non-limiting embodiment of the present invention, referring to fig. 2, the merge control switch 1012 may comprise: one of a source and a drain of the MOS transistor M1 is coupled to a storage node of a 2 x-th row of pixel units in the pixel unit group, and the other is coupled to a storage node of a 2x + 1-th row of pixel units in the pixel unit group 101, and a gate of the MOS transistor M1 is connected to a combining control signal Binning.
It should be noted that fig. 2 only shows the merge control switch 1012 between the 0 th row and the 1 st row of pixel units, and the other merge control switches are not shown. The MOS transistor may be a PMOS or an NMOS, which is not limited in this embodiment of the present invention.
Specifically, when the merged reading is needed, the merging control signal Binning controls the MOS transistor M1 to be turned on. After the MOS transistor M1 is turned on, the storage nodes of the 2x row pixel units and the storage nodes of the 2x +1 row pixel units are turned on, for example, the storage node FD <0> of the 0 th row pixel unit and the storage node FD <1> of the 1 st row pixel unit are turned on, and the combined pixel signal can be output through the pixel signal line BL0 or BL 1.
It should be noted that the combination control switch 1012 may also be implemented by any other implementable switching element, and the embodiment of the present invention is not limited thereto.
In one non-limiting embodiment of the present invention, with continued reference to FIG. 2, each pixel cell group 101 further includes: the pixel array comprises 4n row selection switches Rsel, one end of the x row selection switch Rsel is coupled to the x row pixel units, the other end of the m row or the m +2n row selection switches Rsel is coupled to the m pixel signal line, and m is an integer greater than or equal to 0 and less than 2 n.
Specifically, one end of a row selection switch Rsel <0> is coupled with a 0 th pixel signal line, the other end of the row selection switch Rsel <0> is coupled with a 0 th pixel signal line, and the other end of the row selection switch Rsel <4> is coupled with a 4 th pixel signal line; similarly, one end of a row selection switch Rsel <1> is coupled to the 1 st pixel signal line, the other end of the row selection switch Rsel <5> is coupled to the 5 th pixel unit, and the rest of the row selection switches are repeated herein.
Referring to fig. 3, fig. 3 discloses a quantization circuit array. The quantization circuit array may include a plurality of columns of quantization circuits 301, each pixel signal line blp (y) is coupled to the p + y × 2n column of quantization circuits 301, each quantization circuit 301 is configured to gate the pixel signal line coupled thereto, and the pixel signal of the gated pixel signal line is output through a Data Bus.
Blp (y) represents the p-th pixel signal line to which the y-th pixel unit is coupled. y denotes a column identification of the pixel unit.
In specific implementation, each column of quantization circuits can access an Address gating signal Address, and each pixel signal line can be selectively conducted through the Address gating signal Address quantization circuit, so that the pixel signals on the pixel signal line can be output. Specifically, in combination with the binning control switches in the memory cell array, the pixel signal lines are capable of outputting two rows of binned pixel signals.
Referring to fig. 2 and 3 together, the 0 th pixel signal line BL0(0) coupled to the 0 th pixel unit is coupled to the 0 th quantization circuit 301, the 1 st pixel signal line BL1(0) coupled to the 0 th pixel unit is coupled to the 1 st quantization circuit 301, the 2 nd pixel signal line BL2(0) coupled to the 0 th pixel unit is coupled to the 2 nd quantization circuit 301, and the 3 rd pixel signal line BL3(0) coupled to the 0 th pixel unit is coupled to the 3 rd quantization circuit 301; the 0 th pixel signal line BL0(1) coupled to the 1 st pixel unit is coupled to the 4 th quantization circuit 301, the 1 st pixel signal line BL1(1) coupled to the 1 st pixel unit is coupled to the 5 th quantization circuit 301, the 2 nd pixel signal line BL2(1) coupled to the 1 st pixel unit is coupled to the 6 th quantization circuit 301, and the 3 rd pixel signal line BL3(1) coupled to the 1 st pixel unit is coupled to the 7 th quantization circuit 301.
When the 0 th column quantization circuit 301 is turned on, pixel signals of the 0 th row and the 1 st row of pixels can be selectively output; when the 2 nd column quantization circuit 301 is turned on, pixel signals of the 2 nd row and 3 rd row pixels can be selectively output; when the 1 st column quantization circuit 301 is turned on, pixel signals of the 4 th row and the 5 th row pixels can be selectively output; when the 3 rd column quantization circuit 301 is turned on, pixel signals of the pixels in the 6 th and 7 th rows can be selectively output.
Referring to fig. 4, fig. 4 discloses a read control method of a quantization circuit array. The read control method of the quantization circuit array may include the steps of:
step S401: receiving a column address strobe signal;
step S402: and controlling the multi-column quantization circuit to gate each pixel signal line in sequence according to the column address gating signal so as to output pixels formed by combining the 2x row pixel units and the 2x +1 row pixel units.
In specific implementation, when the combined pixels are output, the combined pixel signals are sequentially output according to the row sequence; that is, the pixels combined by the 2 x-th row pixel units and the 2x + 1-th row pixel units are output in the order from small to large of the row sequence number x. For example, the pixels combined by the pixel unit of the 0 th row and the pixel unit of the 1 st row, the pixels combined by the pixel unit of the 2 nd row and the pixel unit of the 3 rd row, the pixels combined by the pixel unit of the 4 th row and the pixel unit of the 5 th row, the pixels combined by the pixel unit of the 6 th row and the pixel unit of the 7 th row, and the like are sequentially output.
The embodiment of the invention can realize data sequence rearrangement without an additional buffer, so that the pixel signals of a plurality of lines can be read out according to the line sequence, and the subsequent image system can conveniently read the signals.
In one non-limiting embodiment of the present invention, step S402 shown in fig. 4 may include the following steps: and controlling the multi-column quantization circuit to gate 2q + yx 2n pixel signal lines in sequence according to the column address gating signal, and then gate 2q +1+ yx 2n pixel signal lines in sequence, wherein q is a positive integer which is greater than or equal to 0 and less than n.
In specific implementation, when gating 2q + y × 2n pixel signal lines in sequence or gating 2q +1+ y × 2n pixel signal lines in sequence, selecting a q value from low to high according to a q value, and then controlling the multi-column quantization circuit to gate the pixel signal lines according to a y value from low to high under the selected q value according to the column address gating signal.
That is, q has a higher priority than y, and the pixel signal line is selected by selecting the value of q first and then selecting the value of y on the basis of the selected value of q, and then selecting both the value of q and the value of y.
Referring to fig. 3, the memory cell array including 3 rows of pixel cells will be described as an example.
The 0 th column, the 4 th column and the 8 th column quantization circuits 301 are controlled to be turned on simultaneously to selectively output pixel signals of the 0 th row and the 1 st row of pixels; when the 2 nd column quantization circuit 301, the 6 th column quantization circuit 301 and the 10 th column quantization circuit 301 are simultaneously controlled to be conducted, pixel signals of the 2 nd row pixels and the 3 rd row pixels are selectively output; when the quantization circuits 301 in the 1 st column, the 5 th column and the 9 th column are simultaneously controlled to be turned on, pixel signals of pixels in the 4 th row and the 5 th row are selectively output; when the 3 rd column, 7 th column and 10 th column quantization circuits 301 are simultaneously controlled to be turned on, pixel signals of the 6 th row and 7 th row pixels can be selectively output.
In a specific application scenario of the present invention, referring to fig. 3, fig. 4 and fig. 5 together, n is 2, that is, a single pixel unit group includes 8 rows of pixel units. Wherein Rsel < > represents a control signal of a row selection switch Rsel; binning represents combining control signals; rst < represents a reset control signal; tx represents < > transmission control signal; address denotes an Address strobe signal.
In the merged readout mode, at the stage T1-T5, the row selection switches Rsel of the pixel cells of the 0 th, 2 th, 5 th and 7 th rows are turned on, and the row selection switches Rsel of the pixel cells of the 1 st, 3 th, 4 th and 6 th rows are turned off. And the combined control signal Binning controls the conduction of the MOS tube M1.
At stage T2, the 0 th-7 th rows of pixel cells simultaneously perform a reset operation.
At stage T4, the pixel cells of rows 0-7 simultaneously perform a transfer operation. Thus, the pixel signals after the 0 th and 1 st, 2 and 3 rd, 4 th and 5 th, 6 th and 7 th rows are combined are output via the row selection switches Rsel of the pixel units of the 0 th, 2 th, 5 th and 7 th rows, respectively.
In stage T6, the quantization circuit is controlled by the Address strobe signal Address to select the value of q first, then select the value of y based on the selected value of q, and then sequentially strobe the 2q + yx 2n pixel signal lines, and then sequentially strobe the 2q +1+ yx 2n pixel signal lines. For example, when the quantization circuits of the 0 th, 4 th and 8 th columns are simultaneously controlled to be turned on, and the quantization circuits of the 2 nd, 6 th and 10 th columns are simultaneously controlled to be turned on; simultaneously controlling the 1 st column quantization circuit, the 5 th column quantization circuit and the 9 th column quantization circuit to be conducted; and simultaneously controlling the 3 rd column quantization circuit, the 7 th column quantization circuit and the 11 th column quantization circuit to be conducted.
Therefore, the reading of the pixel signals of multiple lines according to the line sequence can be realized, and the reading of the signals by a subsequent image system is convenient.
The embodiment of the invention also discloses a storage medium, which is a computer-readable storage medium and stores computer instructions, and the computer instructions can execute the steps of the reading control method shown in fig. 4 when running. The storage medium may include ROM, RAM, magnetic or optical disks, etc. The storage medium may further include a non-volatile memory (non-volatile) or a non-transitory memory (non-transient), and the like.
The embodiment of the invention also discloses an image sensor which can comprise the memory cell array shown in figure 1 or figure 2; or may comprise an array of quantization circuits as shown in figure 3.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. An array of memory cells, comprising:
the pixel unit groups are arranged in rows and columns, each pixel unit group comprises a single column of 4n rows of pixel units, and n is a positive integer greater than or equal to 1;
each pixel unit group is coupled with 2n pixel signal lines, the 2n pixel signal lines are respectively and sequentially coupled with pixel units in each row in the pixel unit group, and the pixel unit groups comprising the same row of pixel units are coupled with the same 2n pixel signal lines;
each pixel cell group includes:
and 2n merging control switches, each merging control switch being coupled to the storage nodes of the 2 x-th row of pixel units and the storage nodes of the 2x + 1-th row of pixel units in the pixel unit group, wherein x is an integer greater than or equal to 0 and less than 2 n.
2. The memory cell array of claim 1, wherein the merge control switch comprises:
one of a source electrode and a drain electrode of the MOS tube is coupled with the storage node of the 2x row pixel unit in the pixel unit group, the other one of the source electrode and the drain electrode of the MOS tube is coupled with the storage node of the 2x +1 row pixel unit in the pixel unit group, and a grid electrode of the MOS tube is connected with a merging control signal.
3. The memory cell array of claim 1, wherein each pixel cell group further comprises:
one end of the x row selecting switch is coupled with the x row pixel units, the other ends of the m row selecting switch and the m +2n row selecting switch are coupled with the m pixel signal line, and m is an integer which is more than or equal to 0 and less than 2 n.
4. The quantization circuit array of the memory cell array of any of claims 1 to 3, comprising:
each pixel signal line blp (y) is coupled to the p + y × 2n row quantization circuit, each quantization circuit is used for gating the pixel signal line coupled thereto, blp (y) represents the p pixel signal line coupled to the y row pixel unit, y is an integer greater than or equal to 0, and p is an integer greater than or equal to 0 and less than 2 n.
5. The method for controlling reading of the quantization circuit array according to claim 4, comprising:
receiving a column address strobe signal;
and controlling the multi-column quantization circuit to gate each pixel signal line in sequence according to the column address gating signal so as to output pixels formed by combining the 2x row pixel units and the 2x +1 row pixel units.
6. The read control method according to claim 5, wherein the controlling the plurality of columns of quantization circuits to gate the respective pixel signal lines in turn according to the column address gate signal comprises:
and controlling the multi-column quantization circuit to gate 2q + yx 2n pixel signal lines in sequence according to the column address gating signal, and then gate 2q +1+ yx 2n pixel signal lines in sequence, wherein q is a positive integer which is greater than or equal to 0 and less than n.
7. The read control method according to claim 6, wherein the controlling the multi-column quantization circuit to sequentially gate 2q + yx 2n pixel signal lines according to the column address gate signal comprises: selecting a q value according to the low-to-high value of q, and controlling the multi-column quantization circuit to gate pixel signal lines according to the low-to-high value of y under the selected q value according to the column address gating signal.
8. A storage medium having stored thereon computer instructions, wherein the computer instructions are operable to perform the steps of the read control method of any of claims 5 to 7.
9. An image sensor comprising the memory cell array of any one of claims 1 to 3, or comprising the quantization circuit array of claim 4.
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