CN111244071A - Semiconductor device with a plurality of transistors - Google Patents

Abstract

The invention discloses a semiconductor device, comprising: a first base structure including a first semiconductor element and a first dielectric layer on the first semiconductor element; a second base structure comprising a second semiconductor element and a second dielectric layer on the second semiconductor element; the multifunctional conducting layer is positioned between the first substrate structure and the second substrate structure, two sides of the multifunctional conducting layer are respectively connected with the first dielectric layer and the second dielectric layer, projections of the first semiconductor element and the second semiconductor element on a set plane fall into the projection of the multifunctional conducting layer on the set plane, and the set plane is perpendicular to the thickness direction of the first dielectric layer; and the lead-out structure is used for receiving/outputting an electric signal, penetrates through the first substrate structure along the thickness direction and extends to be in local contact with the multifunctional conductive layer.

Description

Semiconductor device

technical field

The present invention relates to the technical field of semiconductor devices, and in particular to a three-dimensional stacked semiconductor device comprising a plurality of semiconductor devices.

Background technique

In the electronics industry, three-dimensional (3D) stacking techniques significantly contribute to the integration of semiconductor devices. To form a 3D stack, two or more chips are arranged one on top of the other and bonded.

3D stacking technology offers many potential advantages, including such as improved form factor, lower cost, enhanced performance, and greater integration through system-on-chip (SOC) solutions. The SOC architecture formed by 3D stacking enables high bandwidth connectivity of stacked semiconductor devices such as logic circuits and dynamic random access memory (DRAM).

However, the above-mentioned 3D stacking technology still has many shortcomings, such as the problem of external connection and interference between the semiconductor devices in the stacked chip, which is not conducive to the integration and improvement of the overall performance of the 3D integrated circuit. Therefore, in order to solve the above technical problems, it is necessary to propose a new three-dimensional integrated circuit semiconductor device.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the present invention provides a semiconductor device of a three-dimensional integrated circuit, so as to solve the problems of external connection and interference of the semiconductor device in the stacked wafer in the current 3D stacking technology.

The semiconductor device of the present invention includes:

A semiconductor device is characterized by comprising a first base structure, the first base structure including a first semiconductor element and a first dielectric layer on the first semiconductor element; a second base structure, the first base structure Two base structures include a second semiconductor element and a second dielectric layer located on the second semiconductor element; a multifunctional conductive layer located between the first base structure and the second base structure, the multifunctional conductive layer The two sides are respectively connected with the first dielectric layer and the second dielectric layer, and the projections of the first semiconductor element and the second semiconductor element on the set plane fall into the multifunctional conductive layer on the set plane. In the projection on, the setting plane is perpendicular to the thickness direction of the first dielectric layer; and a lead-out structure for receiving/outputting electrical signals, the lead-out structure passing through the first dielectric layer along the thickness direction The base structure extends to the local contact with the multifunctional conductive layer.

In one embodiment, the second base structure further includes an interconnect structure, and the second dielectric layer is located between the multifunctional conductive layer and the interconnect structure; the semiconductor device further includes an interconnect structure located on the first base structure. An electrical connection structure inside the electrical connection structure passes through the multifunctional conductive layer and is electrically connected with the interconnection structure.

In one embodiment, the first base structure further includes a third dielectric layer, the third dielectric layer is connected to the multifunctional conductive layer, and the second dielectric layer is connected to the third dielectric layer. electrical connection.

In one embodiment, the first semiconductor element and the second semiconductor element include at least one of an image sensor, a diode, a power device, a memory device, a logic device, and a metal-oxide-semiconductor device.

In one embodiment, one of the first semiconductor element and the second semiconductor element is an image sensor or a logic device.

In one embodiment, the first dielectric layer and the multifunctional conductive layer are connected by bonding, or the second dielectric layer and the multifunctional conductive layer are connected by bonding.

In one embodiment, the outer edges of the multifunctional conductive layer are aligned with the outer edges of the first dielectric layer and the second conductive layer.

In one embodiment, the multifunctional conductive layer is a film layer covering the entire first dielectric layer and the second dielectric layer.

In one embodiment, the multifunctional conductive layer includes aluminum or tantalum.

In one embodiment, the first dielectric layer and the second dielectric layer comprise silicon oxide, silicon nitride, silicon oxycarbide or silicon carbonitride.

In one embodiment, the lead-out structure includes a pad electrically connected to the multifunctional conductive layer and an insulating layer surrounding at least part of the pad.

In the semiconductor device of the present invention, the metal layer at the bonding interface can be used as an insulating layer for light, heat and/or electromagnetic waves through the properties of the multifunctional conductive layer, such as opacity, good thermal conductor and/or electromagnetic wave shielding, etc. Therefore, it is not necessary to use additional photolithography and masking processes to create an isolation layer that isolates light, heat and/or electromagnetic wave interference in the internal film layers of the semiconductor devices of each integrated circuit chip. The manufacturing process of the stacking wafer interference and other problems and the technical effect of reducing the manufacturing cost of the 3D wafer stacking. In addition, through the arrangement of the lead-out structure and the multifunctional conductive layer, an external connection scheme of the semiconductor element located below in the semiconductor device is also provided.

Description of drawings

In order to more clearly illustrate the technical solutions in the technology of the present invention, the following will briefly introduce the embodiments of the present invention by using the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, which are not suitable for those skilled in the art. In other words, on the premise of no creative work, other drawings can also be obtained based on these drawings.

FIG. 1 is an exploded view of a three-dimensional integrated circuit in accordance with the present invention.

2 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a first embodiment of the present invention.

3 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a second embodiment of the present invention.

4 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a third embodiment of the present invention.

5 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a fourth embodiment of the present invention.

Detailed ways

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [upper], [lower], [top], [bottom], [left], [right], [inner], [outer], [side], etc., are only for reference Additional schema orientation. Therefore, the directional terms used are for describing and understanding the present invention, not for limiting the present invention. In the figures, similar elements are denoted by the same reference numerals.

FIG. 1 is an exploded view of a three-dimensional integrated circuit 10 of the present invention. Please refer to FIG. 1 , a three-dimensional integrated circuit 10 is formed by stacking a first IC wafer (IC wafer) P and a second IC wafer Q. The first integrated circuit chip P and the second integrated circuit chip Q may include silicon, gallium arsenide, or other semiconductor materials. The stacked first integrated circuit wafer P in the illustrated embodiment includes a plurality of semiconductor chips 300, while the stacked second integrated circuit wafer Q includes a corresponding plurality of semiconductor chips.

2 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a first embodiment of the present invention. Referring to FIG. 2 , the semiconductor device includes a first base structure 100 , a second base structure 200 and a multifunctional conductive layer 700 disposed between the first base structure 100 and the second base structure 200 . The multifunctional conductive layer 700 is a film layer covering the entire first dielectric layer 106 and the second dielectric layer 206 , and the outer edge of the multifunctional conductive layer 700 is aligned with the outer edge of the first dielectric layer 106 or the second dielectric layer 206 . In this embodiment, the multifunctional conductive layer 700 is a film layer formed on the second base structure 200, and is connected to the first dielectric layer 106 of the first base structure 100 and the multifunctional conductive layer through a bonding connection. 700, and a bonding surface 500' is formed therebetween. The first base structure 100 includes a first semiconductor layer 102 , a first interconnect layer 104 , and a first dielectric layer 106 . The second base structure 200 includes a second semiconductor layer 202 , a second interconnect layer 204 and a second dielectric layer 206 . In addition, three separate regions are defined on the semiconductor device, namely a first region X, a second region Y, and a third region Z located between the first region X and the second region Y. For example, the first region X is a functional device region, the second region Y is a lead pad region, and the third region Z is a device interconnect region.

In the first region X, the first semiconductor layer 102 in the first base structure 100 includes the first semiconductor element 120 formed in the front side A of the semiconductor layer 102, the first interconnect layer 104 includes the first insulating layer 103 and the A first metal interconnection structure in the insulating layer 103. The first metal interconnection structure includes a plurality of conductive layers. In this embodiment, the first metal interconnection structure includes a conductive layer M2 and a conductive layer M1 on the conductive layer M2. . The first semiconductor element 120 is electrically connected to the metal interconnection structure within the first base structure 100 . A first dielectric layer 106 is disposed adjacent to the first interconnect layer 104 for passivation. In addition, the second semiconductor layer 202 includes a second semiconductor element 220 formed in the front side C of the semiconductor layer 202 , and the second interconnect layer 204 includes a second insulating layer 203 and a second metal interconnection within the second insulating layer 203 structure, the second metal interconnect structure includes a plurality of conductive layers. In this embodiment, the second metal interconnect structure includes a conductive layer M3 and a conductive layer M4 located on the conductive layer M3. A second dielectric layer 206 is disposed adjacent to the second interconnect layer 204 for passivation.

As shown in FIG. 2 , the first semiconductor element 120 of the first base structure 100 in the first region X is formed in the front side A of the semiconductor layer 102 , which is electrically connected to the first metal interconnect structure in the first base structure 100 , and the second semiconductor element 220 of the second integrated circuit chip 200 is electrically connected to the second interconnect structure in the second base structure 200 . In one embodiment, the first semiconductor element 120 includes an image sensing device and includes peripheral circuitry associated with a photosensitive region (eg, a photodiode region), such as readout circuitry, control circuitry, or circuitry included in the image sensing device. Other functional circuits (all not shown). As such, the first semiconductor element 120 formed in the front side A receives light 600 from the back side B of the semiconductor layer 102 . The second semiconductor element 220 may include a logic device to control the image sensing device of the semiconductor device 120 . Therefore, the first base structure 100 of the first integrated circuit chip 100 and the second base structure 200 of the second integrated circuit chip 200 can be connected to form a semiconductor device of the three-dimensional integrated circuit 10 , for example, including on the first integrated circuit chip 100 . A three-dimensional stacked semiconductor device of the image sensing device and the logic device on the second integrated circuit wafer 200 . Before connecting the first integrated circuit chip 100 and the second integrated circuit chip 200 together, the first semiconductor element 120 and the second semiconductor element 220 may each be formed in their semiconductor layers. The multifunctional conductive layer 700 in the first region X is electrically and physically completely isolated from the first metal interconnection structure in the first base structure 100 through the first dielectric layer 106, and through the second dielectric layer, respectively. Layer 206 is completely isolated from the second metal interconnect structure within second base structure 200 .

During the operation of the three-dimensional integrated circuit shown in FIG. 2 , with the operation of the second semiconductor element 220 as a logic device, a certain amount of heat energy and radiation will be generated. The base structure 200 reflects irregular light back to the first base structure 100 , which will cause heat and light interference to the first semiconductor element 120 . Therefore, in this embodiment, through the arrangement of the multifunctional conductive layer 700 , the projection of the image sensing device 120 in the first base structure 100 on a predetermined plane falls into the projection of the multifunctional conductive layer 700 on the predetermined plane Inside, the setting plane is perpendicular to the thickness direction of the first dielectric layer 106 . The light and heat interference caused by the operation of the second semiconductor element 220 to the first semiconductor element 120 can be isolated through the properties of the conductive material of the multifunctional conductive layer 110 , such as being opaque to light and being a good conductor of heat.

In one embodiment, the multifunctional conductive layer 700 includes a metal material such as aluminum or tantalum, and the first dielectric layer 106 includes silicon oxide (SixOy), silicon nitride (SixNy), silicon oxycarbide (SixCyOz) or silicon Carbon nitrogen (SixCyNz) compounds, x, y and z are numbers not less than 1. The surface of the first dielectric layer 106 facing the multifunctional conductive layer 700 has undergone surface treatment such as plasma treatment or chemical treatment. In this way, the surface-treated first dielectric layer 106 forms a covalent bond with the multifunctional conductive layer 700, so that the first base structure 100 and the second base structure 200 can be bonded together to form a structure for three-dimensional integration circuit of semiconductor devices. The multifunctional conductive layer 700 only needs to be prepared after the material is deposited, and there is no need to prepare additional processes such as photolithography and masking.

In this embodiment, in the second region Y, the second base structure 200 does not include any semiconductor devices, the second interconnection layer 204 includes a metal layer 420 , and is disposed on the second dielectric layer 410 and the second interconnection layer 204 A plurality of conductive plugs 410 within a portion. The conductive plug 410 is disposed between the multifunctional conductive layer 700 and the conductive layer 420 to electrically connect the above-mentioned components, and forms a pad structure 400 with the conductive layer 420, and the pad structure 400 is connected to the pad structure 400 through a suitable circuit (not shown). The second semiconductor element 220 in the first region X is electrically coupled. The first base structure 100 does not include any semiconductor device, and the first interconnect layer 104 does not include any metal layer disposed in the insulating layer. An opening 800 is formed in a portion of the first base structure 100 . The opening 800 penetrates the first base structure 102 , the first interconnect layer 104 and the first dielectric layer 106 to expose a part of the multifunctional conductive layer 700 in the second region Y, which is the multifunctional conductive layer 700 exposed by the opening 800 It can be used as a lead pad to connect the bonding pad between the internal circuit and the external circuit. A pad 860 electrically connected to the multifunctional conductive layer 700 and an insulating layer 850 surrounding at least part of the pad 860 are formed in the opening 800 . The pads electrically connected to the multifunctional conductive layer 700 and the insulating layer surrounding at least a part of the pads are formed along the thickness direction of the first base structure through the first base structure and extend to the part with the multifunctional conductive layer 700 The contact lead-out structure is used for receiving/outputting the electrical signal from the pad structure 400 in the second base structure 200 transmitted through the multifunctional conductive layer 700 of the second region Y, so as to provide a semiconductor device located at the bottom of the semiconductor device. External connection scheme of the second semiconductor element 220 within the structure.

In this embodiment, the first base structure 100 in the third region X further includes an electrical connection structure 900 , and the electrical connection structure 900 sequentially passes through the first base structure 100 , the multifunctional conductive layer 700 and the second base structure 200 to be electrically connected to the second interconnect structure in the second base structure 200 . The electrical connection structure 900 can be formed by a “Through Silicon Vias (TSV)” process after the first base structure 100 , the multifunctional conductive layer 700 and the second base structure 200 are connected, and includes a conductive layer 910 and a conductive layer 910 . A conductive diffusion barrier layer 920 between the conductive layer 910 and the adjacent film layers. The conductive diffusion barrier layer 920 surrounds the bottom surface and the side surface of the conductive layer 910 , and the electrical connection structure 900 and the multifunctional conductive layer 700 are electrically separated by the first dielectric layer 106 and the second dielectric layer 206 .

3 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a second embodiment of the present invention. The semiconductor device shown in FIG. 3 is generally similar to the semiconductor device shown in FIG. 2 , and the differences between the two semiconductor devices are mainly disclosed below.

Referring to FIG. 3 , in this embodiment, the multifunctional conductive layer 700 is a film layer formed on the first base structure 100 and is connected to the second dielectric layer 206 of the second base structure 200 by bonding connection. and the multifunctional conductive layer 700, and a bonding interface 500" is formed therebetween.

4 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a third embodiment of the present invention. The semiconductor device shown in FIG. 4 is generally similar to the semiconductor device shown in FIG. 2 , and the differences between the two semiconductor devices are mainly disclosed below.

Referring to FIG. 4 , in this embodiment, the semiconductor device includes a first base structure 100 , a second base structure 200 , a multifunctional conductive layer 700 and a third interlayer disposed between the first base structure 100 and the second base structure 200 . Electrical layer 1000. The third dielectric layer 1000 and the multifunctional conductive layer 700 are film layers formed on the second base structure 200 . The third dielectric layer 1000 is connected to the multifunctional conductive layer 700 and is connected to the first conductive layer by bonding The first dielectric layer 106 and the third dielectric layer 1000 of the base structure 100 form a bonding interface 500"' therebetween.

5 is a partial cross-sectional schematic diagram of a semiconductor device in a three-dimensional integrated circuit according to a fourth embodiment of the present invention. The semiconductor device shown in FIG. 5 is generally similar to the semiconductor device shown in FIG. 4 , and the differences between the two semiconductor devices are mainly disclosed below.

Referring to FIG. 5 , in this embodiment, the third dielectric layer 1000 and the multifunctional conductive layer 700 are film layers formed on the second base structure 200 , and the third dielectric layer 1000 is connected to the multifunctional conductive layer 700 . The second dielectric layer 206 and the third dielectric layer 1000 of the second base structure 200 are connected by bonding connection, and a bonding interface 500 ″″ is formed therebetween.

Therefore, the present invention provides various embodiments of the semiconductor device in the three-dimensional integrated circuit as shown in FIGS. 2-5 to provide better resistance to light, heat and/or electromagnetic interference than the semiconductor device in the conventional three-dimensional integrated circuit. and lower fabrication cost of semiconductor devices.

It is worth noting that the semiconductor devices in the three-dimensional integrated circuit shown in the foregoing embodiments of the present invention are not limited to the image sensing devices of the first base structure and the logic devices of the second base structure. Depending on the actual functional requirements of the 3D integrated circuit, the same type of semiconductor devices or different types of semiconductor devices are arranged in the respective base structures of the 3D integrated circuit, and between the semiconductor devices of the first base structure and the semiconductor devices of the second base structure The multifunctional conductive layer can be used as an insulating layer for light, heat and/or electromagnetic waves between adjacent semiconductor devices. The above-mentioned semiconductor device may be selected from one of an image sensing device, a diode device, a power device, a logic device and a metal oxide semiconductor device. In addition, in the semiconductor device in the three-dimensional integrated circuit shown in the foregoing embodiments of the present invention, the multifunctional conductive layer 700 in the first region X is not intended to cover the entire area between the first base structure 100 and the second base structure 200 It only needs to cover the area that needs to be isolated between the first semiconductor element 120 in the first base structure 100' and the second semiconductor element 220 in the second base structure 200'.

In view of the above, in the semiconductor device of the three-dimensional integrated circuit disclosed in the embodiment of the present invention, the metal layer at the bonding interface can be used for the properties of opacity, good thermal conductor and/or electromagnetic wave shielding of the multifunctional conductive layer. It is used as an insulating layer for light, heat and/or electromagnetic waves, so it is not necessary to use additional photolithography and masking processes in the inner film layer of the semiconductor device of each integrated circuit chip to make the insulating layer of light, heat and/or electromagnetic waves. The isolation layer has the technical effect of solving the problem of stacking wafer interference in the current 3D wafer stacking technology and the technical effect of reducing the fabrication cost of the 3D wafer stacking. In addition, through the arrangement of the lead-out structure and the multifunctional conductive layer, an external connection scheme of the semiconductor element located below in the semiconductor device is also provided.

It is worth noting that the arrangement positions of the first base structure and the second base structure included in the three-dimensional integrated circuit of the embodiment shown in FIGS. 2-5 of the present invention are interchangeable, rather than limiting the present invention to the situation shown in FIGS. 2-5 .

Although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims (12)

1. A semiconductor device, comprising:

a first base structure including a first semiconductor element and a first dielectric layer on the first semiconductor element;

a second base structure comprising a second semiconductor element and a second dielectric layer on the second semiconductor element;

the multifunctional conducting layer is positioned between the first substrate structure and the second substrate structure, two sides of the multifunctional conducting layer are respectively connected with the first dielectric layer and the second dielectric layer, projections of the first semiconductor element and the second semiconductor element on a set plane fall into the projection of the multifunctional conducting layer on the set plane, and the set plane is perpendicular to the thickness direction of the first dielectric layer; and

and the lead-out structure is used for receiving/outputting an electric signal, penetrates through the first substrate structure along the thickness direction and extends to be locally contacted with the multifunctional conductive layer.

2. The semiconductor device of claim 1, wherein the second base structure further comprises an interconnect structure, the second dielectric layer being between the multifunctional conductive layer and the interconnect structure;

the semiconductor device further includes an electrical connection structure within the first base structure, the electrical connection structure passing through the multifunctional conductive layer and electrically connected to the interconnect structure.

3. The semiconductor device of claim 1, wherein the first base structure further comprises a third dielectric layer, the third dielectric layer being connected to the multifunctional conductive layer, and the second dielectric layer being connected to the third dielectric layer.

4. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element comprise at least one of an image sensor, a diode, a power device, a memory device, a logic device, and a metal oxide semiconductor device.

5. The semiconductor device according to claim 4, wherein one of the first semiconductor element and the second semiconductor element is an image sensor or a logic device.

6. The semiconductor device according to claim 1, wherein the first dielectric layer and the multifunctional conductive layer are connected by bonding, or wherein the second dielectric layer and the multifunctional conductive layer are connected by bonding.

7. The semiconductor device according to claim 1, wherein outer edges of the multifunctional conductive layer are aligned with outer edges of the first dielectric layer and the second conductive layer.

8. The semiconductor device according to claim 7, wherein the multifunctional conductive layer is a film layer covering the entire first and second dielectric layers.

9. The semiconductor device according to claim 1, wherein the multifunctional conductive layer comprises aluminum or tantalum.

10. The semiconductor device of claim 1, wherein the first and second dielectric layers comprise silicon oxide, silicon nitride, a silicon oxy-carbon compound, or a silicon oxy-carbon compound.

11. The semiconductor device according to claim 1, wherein the lead-out structure comprises a pad electrically connected to the multifunctional conductive layer and an insulating layer surrounding at least a part of the pad.

12. The semiconductor device according to claim 1, wherein the multifunctional conductive layer is an opaque conductive layer.

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