CN111244071A - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN111244071A CN111244071A CN202010080913.4A CN202010080913A CN111244071A CN 111244071 A CN111244071 A CN 111244071A CN 202010080913 A CN202010080913 A CN 202010080913A CN 111244071 A CN111244071 A CN 111244071A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 239000000758 substrate Substances 0.000 claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
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- 230000004888 barrier function Effects 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- 229910020781 SixOy Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- 239000007769 metal material Substances 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a semiconductor device, comprising: a first base structure including a first semiconductor element and a first dielectric layer on the first semiconductor element; a second base structure comprising a second semiconductor element and a second dielectric layer on the second semiconductor element; the multifunctional conducting layer is positioned between the first substrate structure and the second substrate structure, two sides of the multifunctional conducting layer are respectively connected with the first dielectric layer and the second dielectric layer, projections of the first semiconductor element and the second semiconductor element on a set plane fall into the projection of the multifunctional conducting layer on the set plane, and the set plane is perpendicular to the thickness direction of the first dielectric layer; and the lead-out structure is used for receiving/outputting an electric signal, penetrates through the first substrate structure along the thickness direction and extends to be in local contact with the multifunctional conductive layer.
Description
Technical Field
The present invention relates to the field of semiconductor device technology, and in particular to a three-dimensional stacked semiconductor device containing a plurality of semiconductor devices.
Background
In the electronics industry, three-dimensional (3D) stacking technology has significantly contributed to the integration of semiconductor devices. To form a 3D stack, two or more chips are arranged one on top of the other and bonded.
The 3D stacking technique provides a number of potential advantages, including, for example, improved form factor, lower cost, enhanced performance, and greater integration through a system on a chip (SOC) solution. The SOC architecture formed by the 3D stack enables high bandwidth connectivity of the stacked semiconductor devices, such as logic circuits and Dynamic Random Access Memory (DRAM).
However, the 3D stacking technique still has many disadvantages, such as the interference between external connections of semiconductor devices in stacked chips, which is not favorable for the integration and improvement of the overall performance of the 3D integrated circuit. Therefore, in order to solve the above technical problems, it is necessary to provide a new semiconductor device of a three-dimensional integrated circuit.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a semiconductor device of a three-dimensional integrated circuit to solve the external connection and interference problems of the semiconductor device in the stacked wafer in the current 3D stacking technology.
The semiconductor device of the present invention includes:
a semiconductor device comprising a first base structure including a first semiconductor element and a first dielectric layer on the first semiconductor element; a second base structure comprising a second semiconductor element and a second dielectric layer on the second semiconductor element; the multifunctional conducting layer is positioned between the first substrate structure and the second substrate structure, two sides of the multifunctional conducting layer are respectively connected with the first dielectric layer and the second dielectric layer, projections of the first semiconductor element and the second semiconductor element on a set plane fall into the projection of the multifunctional conducting layer on the set plane, and the set plane is perpendicular to the thickness direction of the first dielectric layer; and the lead-out structure is used for receiving/outputting an electric signal, penetrates through the first substrate structure along the thickness direction and extends to be in local contact with the multifunctional conductive layer.
In one embodiment, the second substrate structure further comprises an interconnect structure, and the second dielectric layer is located between the multifunctional conductive layer and the interconnect structure; the semiconductor device further includes an electrical connection structure within the first base structure, the electrical connection structure passing through the multifunctional conductive layer and electrically connected to the interconnect structure.
In one embodiment, the first substrate structure further includes a third dielectric layer, the third dielectric layer is connected to the multifunctional conductive layer, and the second dielectric layer is connected to the third dielectric layer.
In one embodiment, the first semiconductor element and the second semiconductor element include at least one of an image sensor, a diode, a power device, a memory device, a logic device, and a metal oxide semiconductor device.
In an embodiment, one of the first semiconductor device and the second semiconductor device is an image sensor or a logic device.
In an embodiment, the first dielectric layer and the multifunctional conductive layer are connected in a bonding manner, or the second dielectric layer and the multifunctional conductive layer are connected in a bonding manner.
In one embodiment, the outer edge of the multifunctional conductive layer is aligned with the outer edges of the first dielectric layer and the second conductive layer.
In one embodiment, the multifunctional conductive layer is a film layer covering the entire first and second dielectric layers.
In one embodiment, the multifunctional conductive layer comprises aluminum or tantalum.
In one embodiment, the first dielectric layer and the second dielectric layer comprise silicon oxide, silicon nitride, silicon oxycarbide, or silicon carbonitride.
In an embodiment, the lead-out structure includes a pad electrically connected to the multifunctional conductive layer and an insulating layer surrounding at least a portion of the pad.
In the semiconductor device of the present invention, through the characteristics of the multifunctional conductive layer, such as good light-proof and heat-proof conductors and/or electromagnetic wave shielding, the metal layer of the bonding interface can be used as an isolation layer for light, heat and/or electromagnetic waves, so that the isolation layer for isolating light, heat and/or electromagnetic wave interference is not required to be manufactured in the inner film layer of the semiconductor device of each integrated circuit chip by adopting the processes of additional photoetching, masking and the like, and the semiconductor device has the technical effects of solving the problems of stacked chip interference and the like in the current 3D chip stacking technology, and reducing the manufacturing cost of 3D chip stacking. In addition, by the arrangement of the lead-out structure and the multifunctional conductive layer, an external connection scheme of a semiconductor element positioned below the semiconductor device is also provided.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following embodiments of the present invention will be briefly described with reference to the accompanying drawings, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained from the drawings without any inventive effort.
Fig. 1 is an exploded view of a three-dimensional integrated circuit according to the present invention.
Fig. 2 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a first embodiment of the present invention.
Fig. 3 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a second embodiment of the present invention.
Fig. 4 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a third embodiment of the present invention.
Fig. 5 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a fourth embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. Directional phrases used in the present invention, such as [ upper ], [ lower ], [ top ], [ bottom ], [ left ], [ right ], [ inner ], [ outer ], [ side ], refer to the directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, like elements are represented by like reference numerals.
Fig. 1 is an exploded view of a three-dimensional integrated circuit 10 of the present invention. Referring to fig. 1, a three-dimensional integrated circuit 10 is formed by stacking a first integrated circuit wafer (IC wafer) P and a second integrated circuit wafer Q. The first integrated circuit wafer P and the second integrated circuit wafer Q may comprise silicon, gallium arsenide, or other semiconductor materials. The stacked first integrated circuit wafer P in the illustrated embodiment includes a plurality of semiconductor chips (semiconductor chips) 300, while the stacked second integrated circuit wafer Q includes a corresponding plurality of semiconductor chips.
Fig. 2 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a first embodiment of the present invention. Referring to fig. 2, the semiconductor device includes a first substrate structure 100, a second substrate structure 200, and a multifunctional conductive layer 700 disposed between the first substrate structure 100 and the second substrate structure 200. The multifunctional conductive layer 700 is a film that covers the entire first dielectric layer 106 and the second dielectric layer 206, and has an outer edge that is aligned with an outer edge of the first dielectric layer 106 or the second dielectric layer 206. In the present embodiment, the multifunctional conductive layer 700 is a film formed on the second substrate structure 200, and is connected to the first dielectric layer 106 of the first substrate structure 100 and the multifunctional conductive layer 700 by bonding, and a bonding junction 500' is formed therebetween. The first base structure 100 includes a first semiconductor layer 102, a first interconnect layer 104, and a first dielectric layer 106. The second base structure 200 includes a second semiconductor layer 202, a second interconnect layer 204, and a second dielectric layer 206. In addition, three separate regions are defined on the semiconductor device, namely a first region X, a second region Y and a third region Z located between the first region X and the second region Y. For example, the first region X is a functional device region, the second region Y is a wire pad region, and the third region Z is a device interconnect region.
In the first region X, the first semiconductor layer 102 in the first substrate structure 100 includes a first semiconductor device 120 formed in the front side a of the semiconductor layer 102, the first interconnection layer 104 includes a first insulating layer 103 and a first metal interconnection structure located in the first insulating layer 103, the first metal interconnection structure includes a plurality of conductive layers, and in this embodiment, the first metal interconnection structure includes a conductive layer M2 and a conductive layer M1 located on the conductive layer M2. The first semiconductor element 120 is electrically connected to a metal interconnect structure within the first base structure 100. A first dielectric layer 106 is disposed adjacent the first interconnect layer 104 for passivation. In addition, the second semiconductor layer 202 includes a second semiconductor element 220 formed in the front side C of the semiconductor layer 202, and the second interconnection layer 204 includes a second insulating layer 203 and a second metal interconnection structure located in the second insulating layer 203, the second metal interconnection structure includes several conductive layers, and in this embodiment, the second metal interconnection structure includes a conductive layer M3 and a conductive layer M4 located on the conductive layer M3. A second dielectric layer 206 is disposed adjacent the second interconnect layer 204 for passivation.
As shown in fig. 2, the first semiconductor element 120 of the first substrate structure 100 in the first region X is formed in the front side a of the semiconductor layer 102, which is electrically connected to the first metal interconnect structure in the first substrate structure 100, and the second semiconductor element 220 of the second integrated circuit die 200, which is electrically connected to the second interconnect structure in the second substrate structure 200. In one embodiment, the first semiconductor device 120 includes an image sensing device and includes peripheral circuitry associated with a photosensitive region (e.g., a photodiode region), such as readout circuitry, control circuitry, or other functional circuitry (all not shown) included in the image sensing device. In this manner, the first semiconductor element 120 formed in the front side a receives light 600 from the backside B of the semiconductor layer 102. The second semiconductor element 220 may include a logic device to control an image sensing device of the semiconductor device 120. Thus, the first base structure 100 in the first integrated circuit wafer 100 and the second base structure 200 of the second integrated circuit wafer 200 may be connected to form a semiconductor device of the three-dimensional integrated circuit 10, such as a three-dimensional stacked semiconductor device including an image sensing device on the first integrated circuit wafer 100 and a logic device on the second integrated circuit wafer 200. The first semiconductor element 120 and the second semiconductor element 220 may each be formed in their semiconductor layers before the first integrated circuit die 100 and the second integrated circuit die 200 are bonded together. The multifunctional conductive layer 700 in the first region X is electrically and physically completely isolated from the first metal interconnect structure in the first base structure 100 through the first dielectric layer 106 and completely isolated from the second metal interconnect structure in the second base structure 200 through the second dielectric layer 206, respectively.
In the operation of the three-dimensional integrated circuit shown in fig. 2, a certain amount of heat and radiation is generated along with the operation of the second semiconductor device 220 as a logic device, and external light transmitted through the first substrate structure 100 will reach the second substrate structure 200 and reflect irregular light back to the first substrate structure 100, thereby causing thermal and optical interference to the first semiconductor device 120. Therefore, in the present embodiment, through the arrangement of the multifunctional conductive layer 700, the projection of the image sensing device 120 in the first substrate structure 100 on a set plane falls within the projection of the multifunctional conductive layer 700 on the set plane, which is perpendicular to the thickness direction of the first dielectric layer 106. The light and heat interference caused by the operation of the second semiconductor device 220 to the first semiconductor device 120 can be isolated by the characteristics of the conductive material of the multifunctional conductive layer 110, such as good light and heat-proof conductor.
In one embodiment, the multifunctional conductive layer 700 includes a metal material such as aluminum or tantalum, and the first dielectric layer 106 includes silicon oxide (SixOy), silicon nitride (SixNy), silicon oxycarbide (SixCyOz), or silicon carbonitride (SixCyNz), x, y, and z being numbers not less than 1. The surface of the first dielectric layer 106 facing the multifunctional conductive layer 700 is subjected to a surface treatment such as a plasma treatment or a chemical treatment. In this way, the surface-treated first dielectric layer 106 and the multifunctional conductive layer 700 form a covalent bond, so that the first substrate structure 100 and the second substrate structure 200 can be bonded together to form a semiconductor device for a three-dimensional integrated circuit. The multifunctional conductive layer 700 is prepared only after material deposition, and no additional processes such as photolithography and masking are needed.
In the present embodiment, in the second region Y, the second base structure 200 does not include any semiconductor devices, the second interconnect layer 204 includes a metal layer 420, and a plurality of conductive plugs 410 disposed in the second dielectric layer 410 and a portion of the second interconnect layer 204. The conductive plugs 410 are disposed between the multifunctional conductive layer 700 and the conductive layer 420 to electrically connect the above-mentioned devices, and form a pad structure 400 with the conductive layer 420, and the pad structure 400 is electrically connected to the second semiconductor device 220 in the first region X through a suitable circuit (not shown). The first base structure 100 does not include any semiconductor devices and the first interconnect layer 104 does not include any metal layers disposed in insulating layers. An opening 800 is formed in a portion of the first base structure 100. The opening 800 penetrates through the first substrate structure 102, the first interconnect layer 104 and the first dielectric layer 106, exposing a portion of the multifunctional conductive layer 700 in the second region Y, wherein the multifunctional conductive layer 700 exposed by the opening 800 can be used as a bonding pad for connecting an internal circuit and an external circuit. A bonding pad 860 electrically connected to the multifunctional conductive layer 700 and an insulating layer 850 surrounding at least a portion of the bonding pad 860 are formed in the opening 800. The pads electrically connected to the multifunctional conductive layer 700 and the insulating layer surrounding at least a portion of the pads form a lead-out structure passing through the first base structure in a thickness direction of the first base structure and extending to be partially in contact with the multifunctional conductive layer 700 for receiving/outputting an electrical signal from the pad structure 400 in the second base structure 200 transmitted through the multifunctional conductive layer 700 of the second region Y, thereby providing an external connection scheme of the second semiconductor element 220 in the semiconductor device located in the lower semiconductor structure.
In this embodiment, the first substrate structure 100 in the third region X further includes an electrical connection structure 900, and the electrical connection structure 900 sequentially passes through the first substrate structure 100, the multifunctional conductive layer 700 and a portion of the second substrate structure 200 to be electrically connected to the second interconnection structure in the second substrate structure 200. The electrical connection structure 900 may be formed by a Through Silicon Via (TSV) process after the first substrate structure 100, the multifunctional conductive layer 700 and the second substrate structure 200 are connected, and includes a conductive layer 910 and a conductive diffusion barrier layer 920 between the conductive layer 910 and an adjacent film layer. The conductive diffusion barrier layer 920 surrounds the bottom and sides of the conductive layer 910, and the electrical connection structure 900 is electrically separated from the multifunctional conductive layer 700 by the first dielectric layer 106 and the second dielectric layer 206.
Fig. 3 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a second embodiment of the present invention. The semiconductor device shown in fig. 3 is substantially similar to the semiconductor device shown in fig. 2, and the differences between the two semiconductor devices are mainly disclosed below.
Referring to fig. 3, in the present embodiment, the multifunctional conductive layer 700 is a film formed on the first substrate structure 100, and is connected to the second dielectric layer 206 of the second substrate structure 200 and the multifunctional conductive layer 700 by bonding, and a bonding junction 500 "is formed therebetween.
Fig. 4 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a third embodiment of the present invention. The semiconductor device shown in fig. 4 is substantially similar to the semiconductor device shown in fig. 2, and the differences between the two semiconductor devices are mainly disclosed hereinafter.
Referring to fig. 4, in the present embodiment, the semiconductor device includes a first substrate structure 100, a second substrate structure 200, and a multifunctional conductive layer 700 and a third dielectric layer 1000 disposed between the first substrate structure 100 and the second substrate structure 200. The third dielectric layer 1000 and the multifunctional conductive layer 700 are formed on the second substrate structure 200, and the third dielectric layer 1000 is connected to the multifunctional conductive layer 700, and is connected to the first dielectric layer 106 and the third dielectric layer 1000 of the first substrate structure 100 by bonding, and a bonding interface 500' "is formed therebetween.
Fig. 5 is a schematic partial cross-sectional view of a semiconductor device in a three-dimensional integrated circuit according to a fourth embodiment of the present invention. The semiconductor device shown in fig. 5 is substantially similar to the semiconductor device shown in fig. 4, and the differences between the two semiconductor devices are mainly disclosed hereinafter.
Referring to fig. 5, in the present embodiment, the third dielectric layer 1000 and the multifunctional conductive layer 700 are formed on the second substrate structure 200, and the third dielectric layer 1000 is connected to the multifunctional conductive layer 700, and the second dielectric layer 206 and the third dielectric layer 1000 of the second substrate structure 200 are connected by bonding, and a bonding interface 500 "" is formed therebetween.
Accordingly, the present invention provides embodiments of semiconductor devices in three-dimensional integrated circuits as shown in fig. 2-5, so as to provide semiconductor devices with better light, heat and/or electromagnetic interference resistance and lower manufacturing cost than the semiconductor devices in the conventional three-dimensional integrated circuits.
It should be noted that, in the semiconductor devices in the three-dimensional integrated circuit shown in the foregoing embodiments of the present invention, the image sensing device of the first substrate structure and the logic device of the second substrate structure are not limited. Depending on the actual functional requirements of the three-dimensional integrated circuit, the same type of semiconductor devices or different types of semiconductor devices may be disposed in respective substrate structures of the three-dimensional integrated circuit, and the multifunctional conductive layer may be disposed between the semiconductor devices of the first substrate structure and the semiconductor devices of the second substrate structure, so as to serve as an isolation layer for light, heat and/or electromagnetic waves between adjacent semiconductor devices. The semiconductor device can be selected from one of an image sensing device, a diode device, a power device, a logic device and a metal oxide semiconductor device. In addition, in the semiconductor devices in the three-dimensional integrated circuits according to the embodiments of the invention, the multifunctional conductive layer 700 in the first region X does not need to cover the entire region between the first substrate structure 100 and the second substrate structure 200, and it only needs to cover the region that needs to be isolated between the first semiconductor element 120 in the first substrate structure 100 'and the second semiconductor element 220 in the second substrate structure 200'.
In summary, in the semiconductor device of the three-dimensional integrated circuit disclosed in the embodiment of the present invention, through the characteristics of the multifunctional conductive layer, such as light-proof, good thermal conductor and/or electromagnetic wave shielding, the metal layer of the bonding interface can be used as an isolation layer for light, heat and/or electromagnetic waves, so that it is not necessary to fabricate the isolation layer for isolating light, heat and/or electromagnetic wave interference in the internal film layer of the semiconductor device of each integrated circuit chip by using additional photolithography and mask processes, and the like, and the semiconductor device of the three-dimensional integrated circuit disclosed in the embodiment of the present invention has the technical effects of solving the problems of stacked chip interference in the current 3D chip stacking technology and reducing the fabrication cost of 3D chip stacking. In addition, by the arrangement of the lead-out structure and the multifunctional conductive layer, an external connection scheme of a semiconductor element positioned below the semiconductor device is also provided.
It should be noted that the three-dimensional integrated circuits of the embodiments shown in fig. 2-5 of the present invention include the first substrate structure and the second substrate structure whose arrangement positions can be interchanged, and the present invention is not limited to the cases shown in fig. 2-5.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention.
Claims (12)
1. A semiconductor device, comprising:
a first base structure including a first semiconductor element and a first dielectric layer on the first semiconductor element;
a second base structure comprising a second semiconductor element and a second dielectric layer on the second semiconductor element;
the multifunctional conducting layer is positioned between the first substrate structure and the second substrate structure, two sides of the multifunctional conducting layer are respectively connected with the first dielectric layer and the second dielectric layer, projections of the first semiconductor element and the second semiconductor element on a set plane fall into the projection of the multifunctional conducting layer on the set plane, and the set plane is perpendicular to the thickness direction of the first dielectric layer; and
and the lead-out structure is used for receiving/outputting an electric signal, penetrates through the first substrate structure along the thickness direction and extends to be locally contacted with the multifunctional conductive layer.
2. The semiconductor device of claim 1, wherein the second base structure further comprises an interconnect structure, the second dielectric layer being between the multifunctional conductive layer and the interconnect structure;
the semiconductor device further includes an electrical connection structure within the first base structure, the electrical connection structure passing through the multifunctional conductive layer and electrically connected to the interconnect structure.
3. The semiconductor device of claim 1, wherein the first base structure further comprises a third dielectric layer, the third dielectric layer being connected to the multifunctional conductive layer, and the second dielectric layer being connected to the third dielectric layer.
4. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element comprise at least one of an image sensor, a diode, a power device, a memory device, a logic device, and a metal oxide semiconductor device.
5. The semiconductor device according to claim 4, wherein one of the first semiconductor element and the second semiconductor element is an image sensor or a logic device.
6. The semiconductor device according to claim 1, wherein the first dielectric layer and the multifunctional conductive layer are connected by bonding, or wherein the second dielectric layer and the multifunctional conductive layer are connected by bonding.
7. The semiconductor device according to claim 1, wherein outer edges of the multifunctional conductive layer are aligned with outer edges of the first dielectric layer and the second conductive layer.
8. The semiconductor device according to claim 7, wherein the multifunctional conductive layer is a film layer covering the entire first and second dielectric layers.
9. The semiconductor device according to claim 1, wherein the multifunctional conductive layer comprises aluminum or tantalum.
10. The semiconductor device of claim 1, wherein the first and second dielectric layers comprise silicon oxide, silicon nitride, a silicon oxy-carbon compound, or a silicon oxy-carbon compound.
11. The semiconductor device according to claim 1, wherein the lead-out structure comprises a pad electrically connected to the multifunctional conductive layer and an insulating layer surrounding at least a part of the pad.
12. The semiconductor device according to claim 1, wherein the multifunctional conductive layer is an opaque conductive layer.
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| CN102403328A (en) * | 2010-09-13 | 2012-04-04 | 美商豪威科技股份有限公司 | Image sensor with improved noise shielding |
| CN102544034A (en) * | 2010-10-27 | 2012-07-04 | 索尼公司 | Solid-state imaging device, semiconductor device, manufacturing methods thereof, and electronic apparatus |
| CN104981907A (en) * | 2013-02-14 | 2015-10-14 | 奥林巴斯株式会社 | Semiconductor substrate, image pickup element, and image pickup apparatus |
| CN107240593A (en) * | 2017-05-19 | 2017-10-10 | 上海集成电路研发中心有限公司 | Global exposing pixels cellular construction of a kind of stack and forming method thereof |
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