TWI621237B - Semiconductor package and its semiconductor wiring substrate - Google Patents

Abstract

A semiconductor wiring substrate includes a first wiring layer, a second wiring layer and a dielectric layer. The dielectric layer is between the first circuit layer and the second circuit layer. The first circuit layer includes a plurality of first signal lines and a first ground line. The first signal line and the first ground line are alternately distributed in the first circuit layer. The second circuit layer is located on one side of the first circuit layer. The second circuit layer includes a plurality of second signal lines and a second ground line. The second signal line and the second ground line are alternately distributed in the second circuit layer, and an orthographic projection of the second signal line to the first circuit layer is between any two adjacent first signal lines.

Description

Semiconductor package device and semiconductor wiring substrate thereof

The present invention relates to a wiring substrate, and more particularly to a semiconductor wiring substrate and a semiconductor package device.

In recent years, with the rapid development of advanced processes, the design of integrated circuits (ICs) has become more complicated, making the packaging of two-dimensional (2D-IC) integrated circuits of semiconductor packages in the past unsatisfactory. Some packaging needs, so the semiconductor industry has developed 2.5-dimensional wafer (2.5D-IC) or three-dimensional wafer (3D-IC) stacking technology.

For example, a 2.5-dimensional integrated circuit is characterized in that wafers of different functions or properties are stacked on a Silicon Interposer, respectively, and wiring and via-holes are interposed in the interposer (Through-Silicon Via, TSV). ) Electrically connected to each other.

However, due to the relatively dense wiring pattern in the conventional 矽 interposer, not only the performance and cost saving effects provided are limited, but also signal loss and crosstalk are more likely to occur in signal transmission.

An object of the present invention is to provide a semiconductor package device and a semiconductor wiring substrate thereof for solving the inconvenience and lack of the above prior art, that is, not only improving signal transmission performance, reducing manufacturing cost, but also reducing signal loss. And the opportunity for signal crosstalk.

According to an embodiment of the invention, the semiconductor wiring substrate comprises an upper contact layer, a lower contact layer, a first wiring layer, a second wiring layer and a first dielectric layer. The lower contact layer is electrically connected to the upper contact layer. The first dielectric layer is between the first circuit layer and the second circuit layer. The first circuit layer and the second circuit layer are both located between the upper contact layer and the lower contact layer, and electrically connect the upper contact layer and the lower contact layer. The first circuit layer includes a plurality of first signal lines and a plurality of first ground lines. The first signal line and the first ground line are alternately and spaced apart from each other within the first circuit layer. The second circuit layer is located on one side of the first circuit layer. The second circuit layer includes a plurality of second signal lines and a plurality of second ground lines. The second signal line and the second ground line are alternately and spaced apart from each other in the second circuit layer. An orthographic projection of a second signal line to the first circuit layer is between any two adjacent first signal lines.

In one or more embodiments of the present invention, an orthographic projection of a first signal line to a second line layer is between any two adjacent second signal lines.

In one or more embodiments of the present invention, at least one of the first ground lines is between any two adjacent first signal lines, and at least one of the second ground lines is located at any two adjacent second Between signal lines.

In one or more embodiments of the present invention, the first signal line The first ground line is alternately distributed in the first circuit layer in a pair of two, and the second signal line and the second ground line are alternately distributed in the second circuit layer in a pair of two.

In one or more embodiments of the present invention, at least one of the first ground lines has a line width greater than a line width of at least one of the first signal lines.

In one or more embodiments of the present invention, the spacing between any two adjacent first signal lines is greater than the spacing between any adjacent first signal lines and the first ground lines.

In one or more embodiments of the present invention, the semiconductor wiring substrate further includes a third wiring layer and a second dielectric layer. The third circuit layer is located on one side of the first circuit layer opposite to the second circuit layer. The third circuit layer includes a plurality of third signal lines and a plurality of third ground lines. The third ground line and the third signal line are alternately and spaced apart in the third circuit layer. An orthographic projection of a third signal line to the second circuit layer is between any two adjacent second signal lines, and an orthographic projection of a third signal line to the first circuit layer and one of the first signal lines overlapping. The second dielectric layer is between the second circuit layer and the third circuit layer.

In one or more embodiments of the present invention, the semiconductor wiring substrate further includes at least one shielding structure and a main connection region. The shielding structure is periodically alternately formed in the first circuit layer and the second circuit layer, and connects all of the first ground lines and all the second ground lines. The main connection area is located between the upper contact layer and the lower contact layer, and is electrically connected to the shielding structure.

In one or more embodiments of the invention, the shield structure includes a plurality of electrically conductive perforations. Each of the conductive vias penetrates the first dielectric layer and connects any adjacent first ground line and second ground line.

In one or more embodiments of the invention, the shielding structure is located Between any adjacent first signal line and second signal line.

In one or more embodiments of the present invention, the plurality of shield structures are parallel to each other and are arranged in a combined layer of the first circuit layer, the dielectric layer and the second circuit layer.

According to another embodiment of the present invention, the semiconductor wiring substrate comprises a main connection region, a first circuit layer, a second circuit layer, a dielectric layer and at least one shielding structure. The first circuit layer includes a plurality of first signal lines. The second circuit layer is located on one side of the first circuit layer. The second circuit layer includes a plurality of second signal lines. The dielectric layer is between the first circuit layer and the second circuit layer. The shielding structure is periodically alternately formed in the first circuit layer, the dielectric layer and the second circuit layer, electrically connected to the main connection region, and located between any adjacent first signal line and the second signal line for shielding Signal exchange between any adjacent first signal line and second signal line.

In one or more embodiments of the present invention, the shield structure includes a plurality of first ground lines, a plurality of second ground lines, and a plurality of conductive vias. The first ground lines and the first signal lines are alternately distributed among the first circuit layers. The second ground line and the second signal line are alternately distributed among the second circuit layers. Each of the conductive vias extends through the dielectric layer and connects any adjacent first ground line to the second ground line.

In one or more embodiments of the present invention, at least one of the first ground lines is between any two adjacent first signal lines, and at least one of the second ground lines is located at any two adjacent second signals. Between the lines.

In one or more embodiments of the present invention, the first signal line and the first ground line are alternately distributed in a first circuit layer in a pair of two, the second signal The line and the second ground line are alternately distributed in a second circuit layer in a pair of two.

In one or more embodiments of the present invention, at least one of the first ground lines has a line width greater than a line width of the first signal line, and at least one of the second ground lines has a line width greater than a line width of the second signal line.

In one or more embodiments of the present invention, the plurality of shield structures are parallel to each other and are arranged in the first circuit layer, the dielectric layer, and the second circuit layer.

According to another embodiment of the present invention, the semiconductor package device includes at least one wafer semiconductor, a package substrate, and an interposer. The interposer includes the above-described semiconductor wiring substrate between the wafer semiconductor and the package substrate, and electrically connects the wafer semiconductor and the package substrate.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. With the above technical solutions, considerable technological progress can be achieved, and industrially widely used value, which has at least the following advantages: 1. Increasing the wiring usability in each layer of the semiconductor wiring substrate, thereby improving the number of surface contacts and signal transmission performance; 2. Reduce the chance of signal loss and signal crosstalk on the semiconductor wiring substrate; 3. Reduce the number of existing substrate layers in the original design, effectively reduce the overall thickness, and thus reduce manufacturing costs.

The above description is only for explaining the problems to be solved by the present invention, the technical means for solving the problems, the effects thereof, and the like, and the specific details of the present invention will be described in detail in the following embodiments and related drawings.

10, 11, 12, 13‧‧‧ semiconductor wiring substrate

20‧‧‧Upper contact layer

30‧‧‧Under the contact layer

40‧‧‧Line layer

50‧‧‧Dielectric layer

100, 100A, 100B, 100C‧‧‧ first line layer

101‧‧‧First layer

102‧‧‧first signal line

103‧‧‧First grounding wire

200, 200A, 200B, 200C‧‧‧ second circuit layer

201‧‧‧Second layer

202‧‧‧second signal line

203‧‧‧Second grounding wire

300‧‧‧ third circuit layer

301‧‧‧ third layer

302‧‧‧ third signal line

303‧‧‧ Third grounding wire

400‧‧‧First dielectric layer

500‧‧‧Second dielectric layer

600‧‧‧Main area

700‧‧‧Shielding structure

720‧‧‧Electrical perforation

800‧‧‧Semiconductor package

810‧‧‧ wafer semiconductor

811‧‧‧ wafer contacts

820‧‧‧Intermediary

821‧‧‧Semiconductor wiring substrate

822‧‧‧Upper layer

823‧‧‧ first contact

824‧‧‧Under the contact layer

825‧‧‧second junction

830‧‧‧Package substrate

831‧‧‧Substrate contacts

CL‧‧‧ combination layer

G1, G2, G3, G4, G5, G6‧‧‧ spacing

M‧‧‧Multilayer structure

P1, P2, P3, P4‧‧‧ orthographic projection

W1, W2, W3, W4, W5, W6, W7, W8‧‧‧ line width

X, Y, Z‧‧‧ axial

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; FIG. 2B is a partial schematic view showing a plurality of circuit layers in a semiconductor wiring substrate according to an embodiment of the present invention; FIG. 2B is a partial schematic view showing a plurality of circuit layers of a semiconductor wiring substrate according to an embodiment of the present invention; FIG. 4 is a partial schematic view showing two circuit layers of a semiconductor wiring substrate according to an embodiment of the present invention; FIG. 5 is a partial schematic view showing two circuit layers of a semiconductor wiring substrate according to an embodiment of the present invention; A partial top view of a circuit layer in a semiconductor wiring substrate according to an embodiment of the present invention; FIG. 6 is a cross-sectional view taken along line AA of FIG. 5; and FIG. 7 is a semiconductor package according to an embodiment of the present invention. A cross-sectional view of the device.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the present invention, these practical details are not necessarily need. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

Fig. 1 is a partial cross-sectional view showing a semiconductor wiring substrate 10 according to an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the semiconductor wiring substrate 10 includes an upper contact layer 20, a lower contact layer 30, a plurality of wiring layers 40, and a plurality of dielectric layers 50. The lower contact layer 30 is electrically connected to the upper contact layer 20 through the wiring layers 40. The upper contact layer 20 and the lower contact layer 30 are respectively located on opposite sides of the semiconductor wiring substrate 10. These circuit layers 40 are located between the upper contact layer 20 and the lower contact layer 30, and are electrically connected to the upper contact layer 20 and the lower contact layer 30. The dielectric layers 50 are respectively sandwiched between any two adjacent circuit layers 40, between the upper contact layer 20 and one of the circuit layers 40, or between the lower contact layer 30 and one of the circuit layers 40. . In the present embodiment, since at least any two adjacent circuit layers 40 respectively contain signal lines (such as voltage or data signals) that do not overlap each other in the vertical direction (such as the axial direction Z), in order to widen these signals. The spacing of the lines from each other does not reduce the impedance value and the transmission speed between the signal lines, thereby reducing the chance of signal loss and signal crosstalk.

In order to facilitate the reader to easily identify the signal line and the ground line, in the following diagram, the signal line of each line layer uses S as the code for simple identification, and the ground line uses G as the code for simple identification.

2A is a partial schematic view showing a plurality of wiring layers of a semiconductor wiring substrate according to an embodiment of the present invention. Specifically, as shown in FIG. 2A, the semiconductor wiring substrate 10 includes a multilayer structure M. The multilayer structure M is located between the upper contact layer 20 and the lower contact layer 30 (Fig. 1), and electrically connects the upper contact layer 20 and the lower contact layer 30. The multilayer structure M includes a first circuit layer 100 and a second circuit layer 200, respectively. The first dielectric layer 400. The first circuit layer 100 and the second circuit layer 200 are stacked in a stacking direction (eg, the axial direction Z). The first circuit layer 100 is stacked on one side of the second circuit layer 200, and the first dielectric layer 400 is located between the first circuit layer 100 and the second circuit layer 200.

In the present embodiment, more specifically, the first wiring layer 100 includes a first layer body 101, a plurality of first signal lines 102, and a plurality of first ground lines 103. The first layer body 101 is on a plane (such as an X-Y plane), and the first signal lines 102 and the first ground lines 103 are wired on the first layer body 101. This plane (e.g., the X-Y plane) is orthogonal to the above-described lamination direction, or substantially orthogonal. More specifically, the first signal line 102 and the first ground line 103 are alternately and spaced apart from each other in the first layer body 101. For example, the first signal line 102 and the first ground line 103 are alternately arranged one-to-one with each other. In the first layer body 101, that is, the number of the first ground lines 103 between any two adjacent first signal lines 102 in the same first circuit layer 100 is one. As such, the spacing G1 between any two adjacent first signal lines 102 is greater than the spacing G2 between any adjacent first signal lines 102 and the first ground lines 103. In addition, the line width W1 of each or at least one of the first ground lines 103 is substantially equal to the line width W2 of each or at least one of the first signal lines 102 to facilitate control of any two adjacent first signal lines 102. The spacing between the G1. For example, but not limited to, the above line widths W1 and W2 are all in the range of 0.5μ~10μ. Furthermore, the cross-sectional area of each or at least one of the first ground lines 103 is substantially equal to the cross-sectional area of each or at least one of the first signal lines 102. However, the present invention is not limited to the line width of the first ground line and the line width of the first signal line must be equal.

The second circuit layer 200 includes a second layer 201, a plurality of second The signal line 202 is connected to a plurality of second ground lines 203. The second layer body 201 is on another plane (such as an X-Y plane), and the second signal lines 202 and the second ground lines 203 are wired on the second layer body 201. The other plane is orthogonal to the stacking direction or substantially orthogonal. More specifically, the second signal line 202 and the second ground line 203 are alternately and spacedly distributed in the second layer body 201. For example, the second signal line 202 and the second ground line 203 are alternately arranged one-to-one with each other. In the two-layer body 201, that is, the number of the second ground lines 203 between any two adjacent second signal lines 202 in the same second circuit layer 200 is one. Thus, the spacing G3 between any two adjacent second signal lines 202 is greater than the spacing G4 between any adjacent second signal lines 202 and the second ground lines 203. In addition, the line width W3 of each or at least one of the second ground lines 203 is substantially equal to the line width W4 of each or at least one of the second signal lines 202 to facilitate control of any two adjacent second signal lines 202. The spacing between the G3. For example, but not limited to, the above line widths W3 and W4 are all in the range of 0.5μ~10μ. Furthermore, the cross-sectional area of each or at least one of the second ground lines 203 is substantially equal to the cross-sectional area of each or at least one of the second signal lines 202. However, the present invention is not limited to the line width of the second ground line and the line width of the second signal line must be equal.

As can be seen from FIG. 2A, the second signal lines 202 and the first signal lines 102 do not overlap each other, that is, the orthographic projections P1 of any of the first signal lines 102 to the second circuit layer 200 are located at any two adjacent positions. The second signal line 202 overlaps with any second signal line 202, and the orthographic projection P2 of any second signal line 202 to the first circuit layer 100 is located at any two adjacent first signal lines. Between 102, rather than overlapping any of the first signal lines 102. Thus, the first signal line 102 and the second signal line 202 are not too close. Lead to signal loss and signal crosstalk.

2B is a partial schematic view showing a plurality of wiring layers of the semiconductor wiring substrate according to the embodiment of the present invention. As shown in FIG. 2B, the multilayer structure M of FIG. 2B is substantially the same as the multilayer structure M of FIG. 2A. One of the differences is that the multilayer structure M further includes the third wiring layer 300 and the second dielectric layer 500. The first wiring layer 100, the second wiring layer 200, and the third wiring layer 300 are stacked in the above-described lamination direction (e.g., the axial direction Z). The second circuit layer 200 is stacked between the first circuit layer 100 and the third circuit layer 300, and the second dielectric layer 500 is located between the second circuit layer 200 and the third circuit layer 300.

More specifically, the third circuit layer 300 includes a third layer body 301, a plurality of third signal lines 302, and a plurality of third ground lines 303. The third layer body 301 is on another plane (such as an X-Y plane), and the third signal lines 302 and the third ground lines 303 are wired on the third layer body 301. The further plane and the stacking direction are orthogonal to each other or substantially orthogonal. More specifically, the third signal line 302 and the third ground line 303 are alternately and spacedly distributed in the third layer body 301. For example, the third signal line 302 and the third ground line 303 are alternately arranged one-to-one with each other. In the three-layer body 301, that is, the number of the third ground lines 303 between any two adjacent third signal lines 302 in the same third circuit layer 300 is one. Thus, the spacing G5 between any two adjacent third signal lines 302 is greater than the spacing G6 between any adjacent third signal lines 302 and third ground lines 303. In addition, the line width W5 of each or at least one of the third ground lines 303 is substantially equal to the line width W6 of each or at least one of the third signal lines 302 to facilitate control of any two adjacent third signal lines 302. The spacing between the G5. For example, but not limited to, the above line widths W5 and W6 are all in the range of 0.5μ~10μ. Each or to The cross-sectional area of one of the third ground lines 303 is substantially equal to the cross-sectional area of each or at least one of the third signal lines 302. However, the present invention is not limited to the line width of the third ground line and the line width of the third signal line must be equal.

As can be seen from FIG. 2B, the third signal lines 302 and the second signal lines 202 do not overlap each other, that is, the orthographic projections P3 of any of the third signal lines 302 to the second circuit layer 200 are located at any two adjacent positions. The second signal line 202 overlaps with any of the second signal lines 202, and the front projection P4 of any third signal line 302 to the first circuit layer 100 overlaps with one of the first signal lines 102.

The semiconductor wiring substrate of each of the above embodiments is a silicon interposer. Further, the first layer body, the second layer body, and the third layer body are basically composed of a semiconductor material such as germanium or gallium arsenide, however, the invention is not limited thereto. The first dielectric layer and the second dielectric layer include a material such as an oxide, a nitride, or an oxynitride, however, the invention is not limited thereto. The first ground line, the second ground line, the third ground line, the first signal line, the second signal line, and the third signal line respectively comprise a conductive material (for example, metal or indium tin oxide), however, the invention is not limited thereto .

FIG. 3 is a partial schematic view showing two of the circuit layers of the semiconductor wiring substrate 11 according to an embodiment of the present invention. As shown in FIG. 3, the semiconductor wiring substrate 11 of the third embodiment is substantially the same as the semiconductor wiring substrate 10 of the second drawing, for example, any two adjacent first signal lines 102 in the same first wiring layer 100A. The number of the first ground lines 103 is still one, except that the line width W7 of each or at least one of the first ground lines 103 is greater than the line width W2 of each or at least one of the first signal lines 102. To enhance signal shielding Performance. Although the line width W7 is greater than the line width W2, for example, but not limited thereto, the line width W7 and the line width W2 are both in the range of 0.5 μ to 10 μ. However, the present invention is not limited to the line width of the first ground line must be greater than the line width of the first signal line. The cross-sectional area of each or at least one of the first ground lines 103 is greater than the cross-sectional area of each or at least one of the first signal lines 102.

Similarly, in the same second circuit layer 200A, the number of second ground lines 203 between any two adjacent second signal lines 202 is still one, but only one or at least one of the second ground lines 203 The line width W8 is greater than the line width W3 of each or at least one of the second signal lines 202 to further enhance the performance of the signal shielding. Although the line width W8 is greater than the line width W3, for example, but not limited thereto, the line width W8 and the line width W3 are both in the range of 0.5 μ to 10 μ. However, the present invention is not limited to the line width of the second ground line must be greater than the line width of the second signal line. The cross-sectional area of each or at least one of the second ground lines 203 is greater than the cross-sectional area of each or at least one of the second signal lines 202.

4 is a partial schematic view showing two of the circuit layers of the semiconductor wiring substrate 12 according to an embodiment of the present invention. As shown in FIG. 4, the semiconductor wiring board 12 of FIG. 4 is substantially the same as the semiconductor wiring board 10 of the second drawing A, and one of the differences is that, in this embodiment, the first signal line 102 and the first ground line 103 are provided. One-to-two alternately distributed in the first layer body 101, that is, the number of the first ground lines 103 between any two adjacent first signal lines 102 in the same first circuit layer 100B is two. One or more. Similarly, the second signal line 202 and the second ground line 203 are alternately distributed one to two in the second layer body 201, that is, any two adjacent second signals in the same second circuit layer 200B. The number of second ground lines 203 between the lines 202 is two or more.

Fig. 5 is a partial top plan view showing a wiring layer in the semiconductor wiring substrate 13 according to an embodiment of the present invention. Figure 6 is a cross-sectional view of Figure 5 taken along line A-A. As shown in FIG. 5, the semiconductor wiring substrate 13 further includes a plurality of shield structures 700 and a main contact region 600. The main connection area 600 is located in the above-described multilayer structure M (Fig. 2A), for example, in the first layer body 101. However, the present invention does not limit the position of the main connection area in the semiconductor wiring substrate. These shield structures 700 are parallel to each other and are arranged side by side on the semiconductor wiring substrate 13. Each of the shielding structures 700 is connected to the main connecting region 600 along an axial direction Y, and the second extending direction is orthogonal to the first extending direction (such as the X axis) and the stacking direction (such as the Z axis), or substantially orthogonal.

As shown in FIGS. 5 and 6, each of the shielding structures 700 is wavy and formed in the combined layer CL of the first wiring layer 100C, the first dielectric layer 400 and the second wiring layer 200C. (Refer to the dotted line range indicated by the shield structure 700). Each of the shielding structures 700 is periodically alternately formed in the first wiring layer 100C, the first dielectric layer 400, and the second wiring layer 200C, that is, the shielding structure 700 is repeatedly disposed up and down in any two adjacent firsts. Between the signal lines 102, between any two adjacent second signal lines 202, and between the adjacent first signal lines 102 and the second signal lines 202. In addition, the shield structure 700 integrally connects all of the first ground lines 103 and all of the second ground lines 203 and electrically connects the main contact regions 600.

More specifically, the shield structure 700 includes a plurality of conductive perforations 720. Each of the conductive vias 720 penetrates the first dielectric layer 400 and connects any adjacent first ground line 103 and second ground line 203. Each of the conductive vias 720 is, for example, a through silicon via (TSV) or a through glass via (TGV).

Thus, a portion of the first ground lines 103 of the first circuit layer 100C and a portion of the second ground lines 203 of the second circuit layer 200 form the same conductor as all of the conductive vias 720 described above (refer to the reference shielding structure 700). The shielding structure 700 of the dotted line range, and the shielding structure 700 is repeatedly disposed up and down between any two adjacent first signal lines 102, between any two adjacent second signal lines 202, and adjacent Between the first signal line 102 and the second signal line 202, the shielding structure 700 can shield between any two adjacent first signal lines 102 and between any two adjacent second signal lines 202 and adjacent ones. The signal exchange between the first signal line 102 and the second signal line 202 further guides the electromagnetic waves of all the first signal lines 102 and the second signal line 202 to the main connection area 600.

FIG. 7 is a cross-sectional view of a semiconductor package device 800 in accordance with an embodiment of the present invention. As shown in FIG. 7, the semiconductor package device 800 includes a plurality of wafer semiconductors 810, a package substrate 830, and a silicon interposer 820. The buffer interposer 820 is located between the wafer semiconductor 810 and the package substrate 830 and electrically connects the wafer semiconductor 810 and the package substrate 830. The wafer semiconductor 810 and the semiconductor wiring substrate 821 are not covered by any packaging material.

Specifically, the germanium interposer 820 includes a semiconductor wiring substrate 821, an upper contact layer 822, and a lower contact layer 824. The semiconductor wiring substrate 821 is located between the upper contact layer 822 and the lower contact layer 824. The upper contact layer 822 has a plurality of first contacts 823 (including solder pads and solder balls). The lower contact layer 824 has a plurality of second contacts 825 (including pads and solder balls). Each wafer semiconductor 810 has a plurality of wafer contacts 811 (including pads and solder balls) arranged in a spaced relationship. The package substrate 830 has a plurality of substrate contacts 831 (including solder pads) arranged at intervals. These first contacts 823 are soldered separately These wafer contacts 811. These second contacts 825 are respectively soldered to the substrate contacts 831. However, in other embodiments, the wafer semiconductor and the semiconductor wiring substrate may also be covered by the encapsulating material.

The wafer semiconductor 810 can be a volatile memory (such as: dynamic random access memories (DRAMs) and/or static random access memories (SRAMs)), and/or non-volatile. Memory (such as: flash memory).

It should be noted that in the present embodiment, the semiconductor wiring substrate is a tantalum interposer. However, the present invention is not limited thereto, and the semiconductor wiring substrate may be replaced with another sheet material in the semiconductor package device.

Finally, the various embodiments disclosed above are not intended to limit the invention, and those skilled in the art can be protected in various modifications and refinements without departing from the spirit and scope of the invention. In the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (17)

A semiconductor wiring substrate comprising: an upper contact layer; a lower contact layer electrically connecting the upper contact layer; a first circuit layer located between the upper contact layer and the lower contact layer, electrically connecting the An upper contact layer and a lower contact layer, the first circuit layer includes a plurality of first signal lines and a plurality of first ground lines, and the first signal lines and the first ground lines are alternately and spaced apart from each other In the first circuit layer, a second circuit layer is located on one side of the first circuit layer, and includes a plurality of second signal lines and a plurality of second ground lines, and the second signal lines and the second lines The grounding lines are alternately and spacedly distributed in the second circuit layer, wherein an orthogonal projection of one of the second signal lines to the first circuit layer is between any two adjacent first signal lines; a first dielectric layer between the first circuit layer and the second circuit layer; at least one shielding structure is periodically alternately formed in the first circuit layer and the second circuit layer, and all of the first a ground line and all of the second ground lines; and a main connection area The contact layer is located between the upper and the lower contact layer, is electrically connected to the shield structure. The semiconductor wiring substrate of claim 1, wherein an orthographic projection of one of the first signal lines to the second circuit layer is between any two adjacent second signal lines. The semiconductor wiring substrate of claim 1, wherein at least one of the first ground lines is located between any two adjacent first signal lines, and at least one of the second ground lines is located at any two Between adjacent ones of the second signal lines. The semiconductor wiring substrate of claim 1, wherein the first signal lines and the first ground lines are alternately distributed in the first circuit layer in a pair of two, the second signal lines and the first The two ground lines are alternately distributed in the second circuit layer in a pair of two. The semiconductor wiring substrate of claim 1, wherein a line width of at least one of the first ground lines is not less than a line width of at least one of the first signal lines. The semiconductor wiring substrate of claim 1, wherein a spacing between any two adjacent first signal lines is greater than a spacing between any adjacent first signal lines and the first ground lines. The semiconductor wiring substrate of claim 1, further comprising: a third circuit layer located on a side of the second circuit layer opposite to the first circuit layer, comprising a plurality of third signal lines and a plurality of third ground lines The third ground lines and the third signal lines are alternately and spacedly distributed in the third circuit layer. The forward projection of one of the third signal lines to the second circuit layer is between any two adjacent second signal lines, and one of the third signal lines is to the first circuit layer. An orthographic projection overlaps one of the first signal lines; and a second dielectric layer is between the second circuit layer and the third circuit layer. The semiconductor wiring substrate of claim 1, wherein the shielding structure comprises a plurality of conductive vias, each of the conductive vias penetrating the first dielectric layer, and connecting any adjacent first ground lines and the Second ground wire. The semiconductor wiring substrate of claim 1, wherein the shielding structure is located between any adjacent first signal line and the second signal line. The semiconductor wiring substrate of claim 1, wherein the plurality of shielding structures are parallel to each other and arranged in a combined layer of the first wiring layer and the second wiring layer. A semiconductor wiring substrate comprising: a main connection region; a first circuit layer comprising a plurality of first signal lines; and a second circuit layer on one side of the first circuit layer, comprising a plurality of second signal lines; a dielectric layer between the first circuit layer and the second circuit layer; and at least one shielding structure periodically alternately formed in the first circuit layer, the dielectric layer and the second circuit layer, The main connection area is electrically connected between any adjacent first signal line and the second signal line for shielding signal exchange between the first signal line and the second signal line. The semiconductor wiring substrate of claim 11, wherein the shielding structure comprises: a plurality of first ground lines, wherein the first signal lines are alternately distributed in the first circuit layer; and a plurality of second ground lines, And the second signal lines are alternately distributed in the second circuit layer; and a plurality of conductive vias, each of the conductive vias penetrating the dielectric layer and connecting any adjacent first ground lines And the second ground line. The semiconductor wiring substrate of claim 12, wherein at least one of the first ground lines is located between any two adjacent first signal lines; and at least one of the second ground lines is located at any one of Between adjacent ones of the second signal lines. The semiconductor wiring substrate of claim 12, wherein the first signal lines and the first ground lines are alternately distributed in a pair of two In the first circuit layer, the second signal lines and the second ground lines are alternately distributed in the second circuit layer in a pair of two. The semiconductor wiring substrate of claim 12, wherein a line width of at least one of the first ground lines is not less than a line width of at least one of the first signal lines; and at least one of the second ground lines The line width is not less than a line width of at least one of the second signal lines. The semiconductor wiring substrate of claim 12, wherein the plurality of the at least one shielding structures are parallel to each other and are arranged in the first wiring layer, the dielectric layer and the second wiring layer. A semiconductor package device comprising: at least one wafer semiconductor; a package substrate; and an interposer comprising a semiconductor wiring substrate according to any one of claims 1 to 16, between the wafer semiconductor and the package substrate, And electrically connecting the wafer semiconductor and the package substrate.