KR100871708B1 - Chip having side pad, method of fabrication the same and package using the chip - Google Patents

Abstract

Provided are a chip, a method of manufacturing the same, and a package using the same, capable of properly securing a position of a side pad. The chip and method include side pads exposed to the sidewalls and formed of a plurality of conductive patterns separated from each other in the vertical direction of the sidewalls, and dimples positioned above and below the side pads to adjust the position of the side pads. The package includes a second connection terminal for electrically connecting the side pad and the circuit board. The chip may be extended in a horizontal or vertical direction with respect to the circuit board, and may be attached to the circuit board by providing an electrical connection terminal.

Package, dimples, side pads, connection terminals.

Description

Chip having dimple, manufacturing method and package using the chip {Chip having side pad, method of fabrication the same and package using the chip}

1 is a perspective view schematically showing one example of a conventional semiconductor chip.

2 is a perspective view schematically showing another example of a conventional semiconductor chip.

3 is a perspective view schematically showing an embodiment of a chip of the present invention.

4 is a plan view illustrating a process of separating the substrate of the present invention into chips.

5A through 5C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing a chip according to an embodiment of the present invention.

6 is a perspective view schematically showing another embodiment of the chip of the present invention.

7A to 7C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing a chip according to another embodiment of the present invention.

8 is a perspective view schematically showing another embodiment of the chip of the present invention.

9A to 9C are plan views illustrating a relationship between an electrical structure including metal wires, vias, and circuit wires, and a second side pad, respectively.

FIG. 10A is a plan view illustrating an embodiment of a structure of a package using a chip of the present invention, and FIG. 10B is a cross-sectional view taken along line B-B of FIG. 10A.

FIG. 11 is a cross-sectional view illustrating a structure in which a new chip is stacked in a direction perpendicular to a circuit board in the package of FIG. 10B.

FIG. 12A is a plan view illustrating a structure in which a new chip is connected to the circuit board in a direction horizontal to the circuit board of FIG. 10B, and FIG. 12B is a cross-sectional view taken along line C-C of FIG. 12A.

FIG. 13 is a plan view illustrating a package in which the structure of FIG. 12A is extended two-dimensionally. FIG.

14 and 15 are cross-sectional views illustrating modified examples of the second connection terminal of FIG. 10A.

16A is a plan view illustrating another embodiment of a structure of a package using a chip of the present invention, and FIG. 16B is a cross-sectional view taken along the line D-D of FIG. 16A.

17A is a plan view illustrating a method of packaging by combining the side pads, the dimples and the top pad of the present invention. FIG. 17B is a cross-sectional view taken along the line E-E of FIG. 17A.

18 is a plan view illustrating a case in which side pads and dimples are formed on all sidewalls of the chip of the present invention, and top pads are formed at two corners of the top surface of the chip.

19 is a plan view illustrating an example in which side pads and dimples are formed on all sidewalls of a chip of the present invention, and top pads are formed at three corners of an upper surface of the chip.

FIG. 20 is a plan view illustrating an example in which side pads and dimples are formed on some sidewalls of a chip of the present invention, and top pads are formed at some edges of an upper surface of the chip.

21A is a plan view illustrating another embodiment of a package structure using a chip of the present invention, and FIG. 21B is a cross-sectional view taken along the line F-F of FIG. 21A.

* Description of the symbols for the main parts of the drawings *

100; Chip 102; Board

108a, b; Pad conductive patterns 108; Material layer for side pad

120a, b; Conductive pattern 120; First side pad

130; Upper pad 160; 2nd side pad

170; First dimple 180; 2nd dimple

200a; Layer to Form Metallization

200b; Layers to form vias

200c; Layer to Form Circuit Wiring

210; Metallization 212; Via

214; Circuit wiring 300; Circuit board

310; First connection terminal 320; 2nd connection terminal

320; First substrate pad 330; Bonding Wire

The present invention relates to a chip, such as a semiconductor chip of the present invention, a method for manufacturing the same, and a package thereof, and more particularly, to a chip including a dimple for adjusting a position of a side pad, for example, a height. It relates to a package using a chip.

As the size of electronic products becomes smaller, the size of electronic devices corresponding thereto is also decreasing. In spite of the small size of the device, there is a demand for a chip having a large device capacity and an excellent function, for example, a semiconductor chip. Accordingly, the package using the chip also requires a small size, a large capacity and a fast processing speed.

In the manufacturing process of a semiconductor chip, a semiconductor wafer (or substrate) is divided into a plurality of chips (or dies) defined by scribe lines formed on the surface of the wafer. The wafer is cut along each scribe line by, for example, a diamond-tipped cutter and separated into individual chips.

1 is a perspective view schematically showing one example of a conventional semiconductor chip.

According to FIG. 1, a chip 10, such as a semiconductor chip, forms at least one side wall 50 with respect to the top surface 40 and the top surface 40, so-called active surface. Although the chip 10 providing four sidewalls 50 is shown in the drawing, a chip having various numbers of sidewalls may be used in some cases. The first side pad 20, which is a conductive pad, is formed of a plurality of conductive patterns 20a and 20b exposed to the sidewall 50 and separated from each other in the vertical direction of the sidewall 50. Although not indicated by reference numerals between the conductive patterns 20a and 20b, an insulating film such as a silicon oxide film is positioned. In this case, an upper pad 50, which is another conductive pad, may be attached to the upper surface 10 of the chip 10.

2 is a perspective view schematically showing another example of a conventional semiconductor chip. Here, the chip 10 may include the chip of FIG. 2 except for the second side pad 60 including a conductive pattern 60a (hereinafter referred to as a buried pattern) formed by a separate filling filling the conductive patterns 20a and 20b. Same as 10). The first and second side pads 60 as described above may be stacked in multiple layers than shown.

Side pads 20 and 60 are required to have a suitable height for the packaging process. However, it is often difficult to implement an appropriate side pad due to the small number of layers forming the side pads. Accordingly, it may be difficult to package the chip because the height of the side pads is not secured.

Therefore, the technical problem to be achieved by the present invention is to provide a chip that can properly secure the position of the side pad. In addition, another technical problem is to provide a method for manufacturing the chip. Furthermore, another technical problem is to provide various types of packages using the chip.

Chip having a dimple according to the present invention for achieving the above technical problem is exposed to the side wall, the side pad made of a plurality of conductive patterns separated from each other in the vertical direction of the side wall and the side pad located above and below the side pad It includes a dimple to adjust the position of the pad.

One example of a method of manufacturing a chip having a dimple according to the present invention for achieving the above another technical problem is first to form an electrical structure on a substrate on which a scribe line is defined. Thereafter, a first dimple material layer is formed on the substrate between the electrical structures. A plurality of pad conductive patterns are formed on the first dimple material layer, the plurality of pads being vertically separated from each other over the scribe line. The substrate on which the pad conductive pattern is formed is covered with a protective insulating film. The protective insulating layer, the pad conductive pattern, and the first dimple material layer are removed by the width of the scribe line to form a conductive pattern and a first dimple.

Another example of a method of manufacturing a chip having a dimple according to the present invention for achieving the above another technical problem is to first form an electrical structure on a substrate on which a scribe line is defined. Thereafter, a plurality of pad conductive patterns are formed on the substrate, the plurality of pads being vertically separated while covering the scribe lines. The substrate on which the pad conductive pattern is formed is covered with a protective insulating film. A second dimple material layer is formed on the pad conductive pattern in the protective insulating layer. The protective insulating layer, the pad conductive pattern, and the second dimple material layer are removed by the width of the scribe line to form a conductive pattern and a second dimple.

One example of a package using a chip having a dimple according to the present invention for achieving the above another technical problem includes a circuit board including an electric circuit. In addition, the side pad is placed directly on the circuit board, and exposed to the side wall and formed of a plurality of conductive patterns separated from each other in the vertical direction of the side wall and dimples which can be positioned above and below the side pad to adjust the position of the side pad. Includes a chip comprising a. And a second connection terminal electrically connecting the circuit board and the side pad.

Another example of a package using a chip having a dimple according to the present invention for achieving the another technical problem is a side pad and the side pad made of a plurality of conductive patterns exposed to the side wall and separated from each other in the vertical direction of the side wall Located above and below the first chip including a dimple capable of adjusting the position of the side pad. In addition, the side pads are disposed independently of the first chip and are exposed to sidewalls and are disposed on upper and lower sides of the side pads formed of a plurality of conductive patterns separated from each other in the vertical direction of the sidewalls, and the position of the side pads can be adjusted. And a second chip comprising dimples. And a second connection terminal electrically connecting the first side pad and the second side pad.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Like reference numerals denote like elements throughout the embodiments.

Embodiments of the present invention will present a chip having dimples located above or below a conductive pad made of a plurality of conductive patterns exposed to the sidewalls and separated from each other in the vertical direction of the sidewalls. The chip is the same as a conventional semiconductor chip and may also be referred to as a die, and the chip may be denoted by the same reference numeral for convenience of description even with slight modifications. In addition, since the chip may be packaged in various forms, examples of packages using the chip will be listed in detail following the description of the chip. Accordingly, the chip and the package will be said to share the features of the present invention. Hereinafter, the conductive pad will be given an appropriate name and reference numeral according to the embodiment.

<Example about Chip>

3 is a perspective view schematically showing an embodiment of the chip 100 of the present invention.

According to FIG. 3, a chip 100, such as a semiconductor chip, forms at least one sidewall 150 with respect to the top surface 140 and the top surface 140, so-called active surface. In the figure, a chip 100 providing four sidewalls 150 is shown. However, in some cases, a chip having various numbers of sidewalls may be used.

The first side pad 120, which is a conductive pad, is formed of a plurality of conductive patterns 120a and 120b exposed to the sidewall 150 and separated from each other in the vertical direction of the sidewall 150. The first side pad 120 may protrude from the side wall 150, but preferably has the same plane as the side wall 150. Although not indicated by reference numerals between the conductive patterns 120a and 120b, an insulating film such as a silicon oxide film is positioned.

Although two conductive patterns 120a and 120b are exemplified in the drawing, as will be described later, the number of conductive patterns may be set differently as necessary. The conductive patterns 120a and 120b may be formed of at least one layer selected from conductive metal nitride layers such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride.

Shapes such as the width and thickness of the conductive patterns 120a and 120b may be set in consideration of the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. In addition, the position and number of the first side pads 120 may also be variously determined by the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. For example, the position of the first side pad 120 may vary depending on the thicknesses of the second interlayer insulating layer 110 and the conductive patterns 120a and 120b, respectively. In particular, the first side pad 120 associated with the package will be described in detail later.

The first dimple 170 is positioned below the first side pad 120. In detail, the first dimple 170 may be in contact with the first side pad 120 or may be spaced apart by a predetermined interval. In addition, the first dimple 170 may be formed in contact with the substrate 102 of FIG. 5 or may be formed to be separated from the substrate. The first dimple 170 may be formed of at least one layer selected from conductive metal nitride layers such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride.

An upper pad 130, which is another conductive pad, may be attached to the upper surface 140 of the chip 100 of FIG. 2. The upper pad 130 may be formed of at least one layer selected from conductive metal nitride layers such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride. The number of top pads 130 may vary depending on the type of package. This will be described later in detail.

4 is a plan view illustrating a process of separating a substrate such as a semiconductor wafer (102 of FIG. 5) into a chip 100 of the present invention. In other words, the side pad material layer 108 and the first dimple material layer 170a may be formed on the scribe line SL and the chip 100 on a portion (a) of the substrate 102 having the plurality of chips 100. Across. The scribe lines SL extend in plan while maintaining the same width. An upper pad 130 is disposed on each chip 100. The distance between the opposing first side pad 120 (FIG. 5C) and the first dimple 170 defines the width of the scribe line SL. In other words, the first side pad material layer 108 and the first dimple material layer 170a to be removed are determined according to the width of the scribe line SL.

5A through 5C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing the chip 100 according to an embodiment of the present invention.

Referring first to FIG. 5A, a conductive region 104 is formed on a substrate 102. The conductive region 104 may be one of the electrical structures to be presented later. In this case, the substrate 102 may be a semiconductor wafer or multiple patterns (not shown) may be formed on the wafer. Subsequently, the substrate 102 on which the conductive region 104 is formed is covered by the first interlayer insulating film 106. The first interlayer insulating film 106 may be formed by, for example, depositing a silicon oxide film.

Subsequently, the first dimple material layer 170a is formed through the first interlayer insulating film 106 on the substrate 102 between the conductive regions 104 by a conventional method. The first dimple material layer 170a may be formed in contact with the substrate 102 as shown, but may be formed at regular intervals from the substrate 102 as necessary.

Referring to FIG. 5B, a pad conductive pattern 108b is formed on the planarized first interlayer insulating layer 106 to cover a portion of the scribe line SL. In this case, the pad conductive pattern 108b may be formed in contact with the first dimple material layer 170a. In some cases, a separate interlayer insulating film (not shown) may be disposed on the first dimple material layer 170a to adjust the height of the conductive pad in the entire chip.

Thereafter, as illustrated, the first interlayer insulating film 106 and the pad conductive pattern 108b are covered with the second interlayer insulating film 110, and the pad conductive pattern 108a is formed on the second interlayer insulating film 110. do. The pad conductive patterns 108a and 108b are a material layer 108 for forming the first side pad 120 of the present invention. Subsequently, a protective interlayer insulating film 112 covering the second interlayer insulating film 110 and the pad conductive pattern 108a and the top pad 130 described with reference to FIG. 3 may be formed on the surface thereof.

The shape of the chip 100 such as the width and thickness of the pad conductive patterns 108a and 108b and the first dimple material layer 170a, the type of package, and the process of forming an electrical structure inside the chip 100 may be used. Can be set in consideration. In addition, the position and number of the first side pad material layer 108, the first dimple material layer 170a, and the upper pad 130 are also defined by the shape of the chip 100, the type of the package, and the inside of the chip 100. Various determinations can be made by a process of forming an electrical structure or the like. For example, the height of the first dimple material layer 170a may vary depending on the thickness and the number of the second interlayer insulating film 110 and the pad conductive patterns 108a and 108b, respectively.

The first dimple material layer 170a and the pad conductive patterns 108a and 108b may be formed together to form an electrical structure inside the chip 100. For example, the wiring is formed by adding a region for forming the first dimple material layer 170a and the pad conductive patterns 108a and 108b to a mask for forming an electrical wiring inside the chip 100. At the same time, the first dimple material layer 170a and the pad conductive patterns 108a and 108b may be formed. That is, a separate photolithography process for forming the first dimple material layer 170a and the pad conductive patterns 108a and 108b is not required. This will be described later in detail.

Referring to FIG. 5C, the substrate 102 is cut along each scribe line SL by a diamond-tipped cutter, as shown in FIG. 4, and separated into respective chips 100. When each chip 100 is individualized, the side surface of the chip 100 is formed of conductive patterns 120a and 120b by removing portions of the side pad material layer 108 and the first dimple material layer 170a, respectively. The first side pad 120 and the first dimple 170 are exposed.

6 is a perspective view schematically showing another embodiment of the chip 100 of the present invention. Here, the chip 100 may include the chip of FIG. 3 except for the second side pad 160 including a conductive pattern 160a (hereinafter referred to as a buried pattern) formed by a separate filling filling between the conductive patterns 120a and 120b. Same as 100).

As shown, the buried pattern 160a filling between the conductive patterns 120a and 120b is at least one layer selected from among conductive metal nitride films such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride or tungsten nitride. Can be done. That is, the exposed side surface of the second side pad 160 may be integrated with a conductive material.

Shapes such as the width and thickness of the buried pattern 160a may be set in consideration of the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. In addition, the position and the number of the second side pads 160 may also be variously determined by the shape of the chip 100, the type of the package, and the process of forming an electrical structure inside the chip 100. For example, the position of the second side pad 160 may vary depending on the thicknesses of the second interlayer insulating layer 110, the conductive patterns 120a and 120b, and the buried patterns 160a and the first dimples 170, respectively. have.

7A to 7C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing the chip 100 according to another embodiment of the present invention.

Referring to FIG. 7A, a conductive region 104 is formed on the substrate 102. In this case, the substrate 102 may be a semiconductor wafer or multiple patterns (not shown) may be formed on the wafer. Subsequently, the substrate 102 on which the conductive region 104 is formed is covered by the first interlayer insulating film 106. The first interlayer insulating film 106 may be formed by, for example, depositing a silicon oxide film.

Subsequently, the first dimple material layer 170a is formed through the first interlayer insulating film 106 on the substrate 102 between the conductive regions 104 by a conventional method. The first dimple material layer 170a may be formed in contact with the substrate 102 as shown, but may be formed at regular intervals from the substrate 102 as necessary.

Next, a pad conductive pattern 108b is formed on the planarized first interlayer insulating film 106 to cover a portion of the scribe line SL. In this case, the pad conductive pattern 108b may be formed in contact with the first dimple material layer 170a. In some cases, a separate interlayer insulating film (not shown) may be disposed on the first dimple material layer 170a to adjust the height of the entire chip.

Thereafter, the first interlayer insulating film 106 and the pad conductive pattern 108b are covered with the second interlayer insulating film 110 as shown. A part of the second interlayer insulating film 110 is removed using a conventional photolithography method to expose the top surface of the pad conductive pattern 108b. After filling the conductive pattern 152a for filling in the portion of the second interlayer insulating film 110 removed, a flat top surface is formed. The width of the filling conductive pattern 152a may be the same as that of the pad conductive pattern 108b, but is not necessarily limited thereto.

Referring to FIG. 7B, a pad conductive pattern 108a is formed on the second interlayer insulating film 110. The patterns 108a, 152a, and 108b are a layer of material 154 for forming the second side pads 160. Subsequently, a protective insulating film 112 covering the second interlayer insulating film 110 and the pad conductive pattern 108a and the top pad 130 described with reference to FIG. 3 may be formed on the surface thereof.

The first dimple material layer 170a and the buried conductive pattern 152a may be formed together to form an electrical structure inside the chip 100. For example, the first dimple material layer 170a may add a region for forming the first dimple material layer 170a to a mask for forming a contact for wiring of the electrical structure. In addition, a region for forming the filling conductive pattern 152a may be added to a mask for forming a via in the chip 100, thereby forming the via and forming the filling conductive pattern 152a. That is, a separate photolithography process for forming the first dimple material layer 170a and the buried conductive pattern 152a may not be required. This will be described later in detail.

Referring to FIG. 7C, the substrate 102 is cut along each scribe line SL by a diamond-tipped cutter, for example, and separated into respective chips 100. When the chip 100 is individualized, the side surfaces of the chip 100 may be partially removed from the patterns 108a, 152a, and 108b and a portion of the first dimple material layer 170a. The second side pad 160 and the first dimple 170 made of 120b are exposed. The process of separating the chip 110 is as described above.

8 is a perspective view schematically showing another embodiment of the chip 100 of the present invention. As shown, another embodiment of the present invention differs from the structure of the chip described with reference to FIG. 6 in the position of the second dimple 180. The second dimple 180 is positioned on an upper side of the second side pad 160, that is, opposite to the first dimple 170 with respect to the second side pad 160. Another embodiment of the present invention presents the possibility that the dimples of the present invention can be variously applied.

9A to 9C are plan views illustrating a relationship between an electrical structure including metal wirings, vias, and circuit wirings, respectively, and the second side pad 160. At this time, the side pad of the present invention is applied to the second side pad 160 of FIG. The second side pad 160 includes a buried pattern 160a buried between the separated conductive patterns 120a and 120b. The conductive patterns 120a and 120b are respectively located on the side of the layer for forming the via and the layer for forming the circuit wiring, and the buried pattern 160a for forming the via. To illustrate that the layers are formed simultaneously with the patterns 120a, 120b, 152a of the present invention, they are presented by way of example.

In the exemplary embodiment of the present invention, the conductive pattern formed on the side of the layer 200a for forming the metal wiring 210 is assumed to be the conductive pattern 120a of the uppermost layer of the second side pad 160. That is, the process of forming the metal wiring 210 and the process of forming the uppermost conductive pattern 120a may be performed.

In addition, the conductive pattern formed on the side surface of the layer 200c for forming the circuit wiring 214 was determined as the conductive pattern 120b of the lowermost layer of the second side pad 160. That is, the process of forming the circuit wiring 214 can be performed and the process of forming the lowermost conductive pattern 120b can be performed. In some cases, the positions of the conductive patterns 120a and 120b may be interchanged. Reference numeral 220 denotes a circuit element inside the chip 100.

The conductive pattern formed on the side of the layer 200b for forming the via 212 may be a buried pattern 160a of the second side pad 160. In other words, the via pattern 212 may be formed at the same time as the via 212 is formed.

Similarly, the first and second dimples 170 and 180 may also be formed at the same time as the process of forming a via (not shown) for forming the metal wiring 210 or the circuit wiring 214. Accordingly, a separate photolithography process for forming the first and second dimples 170 and 180 may not be required.

The embodiment of the present invention is to apply the first and second dimples 170 and 180 when the second side pad 160 fails to secure an appropriate height as described above. That is, when there are few layers for forming metal lines, layers for forming circuit lines, and layers for forming vias, the second side pads 160 cannot secure an appropriate height. Accordingly, before the second side pad 160 is formed, the height of the second side pad 160 can be adjusted by forming the first dimple 170 that can adjust the height of the second side pad 160. have. In addition, although the second dimple 180 will be described with reference to FIG. 14, the second dimple 180 may be used to adjust the height of the second side pad 160 in the case of a rectangular solder ball.

<Example for Package>

10A is a plan view illustrating an embodiment of a structure of a package using a chip of the present invention, and FIG. 10B is a cross-sectional view taken along line B-B of FIG. 10A. At this time, the chip 100 is applied to the first side pad 120 and the first dimple 170 of FIG. The first side pad 120 and the first dimple 170 are merely described by way of example, and the side pads may be applied to all the pads described above within the scope of the present invention.

10A and 10B, a package includes a circuit board 300 including an electric circuit and a chip 100 of the present invention placed directly on the circuit board 300. One surface of the circuit board 300 has a first connection terminal 310, for example, a solder ball attached to the outside of the package, and the other surface of the circuit board 300, and a first substrate pad 320 for electrical connection with the chip 100. Is formed. The chip 100 of the present invention is directly placed on the substrate 300 between the first substrate pads 320.

The circuit board 102 applied to the present invention is not particularly limited, but may be a printed circuit board having at least one layer or a circuit board for a film package in which a circuit pattern is formed on a polymer film. The circuit board may be applied to various applications, for example, signal processing of a memory device, a display device, or a DDI device. In particular, since circuit boards are moving toward reducing size and weight, various types and types of circuit boards are expanding their application fields.

A chip 100, such as a semiconductor chip, forms an upper surface (140 in FIG. 2), which is called an active surface, and at least one sidewall (150 in FIG. 2) with respect to the upper surface. Although the chip 100 providing four sidewalls is shown in the drawing, a chip having various numbers of sidewalls may be used in some cases. The chip 100 includes a first side pad 120 and a first dimple 170 of the present invention, which are conductive pads formed of a plurality of conductive patterns 120a and 120b separated from each other in the vertical direction of the sidewall while being exposed to the sidewall. do.

Placed directly on the circuit board 300 means that no material layer is inserted between the circuit board 300 and the chip 100. And, it means that the chip 100 is located on the circuit board 300 without any physical or chemical coupling between the circuit board 300 and the chip 100. Accordingly, a conventional adhesive layer is not required between the circuit board 300 and the chip 100. Since the chip 100 is directly placed on the circuit board 300 and there is no adhesive layer, the height (or thickness) of the package may be greatly reduced. However, in some cases, the chip 100 may be attached onto the circuit board 300 using the adhesive layer.

  The circuit board 300 and the chip 100 are connected to each other using the first side pad 120 and the first substrate pad 320 by the second connection terminal 312. In this case, the first side pad 120 may serve as an input / output pad and the second connection terminal 312 may serve as an input / output terminal. The first dimple 170 adjusts the height of the first dimple 170 so that the second connection terminal 312 may be connected to the first side pad 120 and the first substrate pad 320. In one embodiment of the present invention provides a second connection terminal 312 in the form of a solder ball. The first and second connection terminals 310 and 312 may be formed by a conventional method, and are attached to the respective pads by performing a reflow process.

The number of second connection terminals 312 may vary depending on the type of package. For example, a package requiring fewer input / output pads may have a smaller number of second connection terminals 312, and a package requiring a large number of input / output pads may have a larger number of second connection terminals 312. Can lose. Also, although the second connection terminal 312 is formed on all sidewalls of the chip 100 in the drawing, the second connection terminal 312 may be formed only on some sidewalls of the chip 100.

FIG. 11 is a cross-sectional view illustrating a structure in which a new chip 100 is stacked in a direction perpendicular to the circuit board 300 in the package of FIG. 10B. As shown, an upper pad 130 is further formed on the chip 100 of FIG. 10B on the upper surface of the chip 100 directly placed on the circuit board 300. The new pad 100 is stacked on the upper pad 130 by being connected by a third connection terminal 314 such as a solder ball. The new chip 100 may be the chip 100 of the present invention, or in some cases, may be a different chip from the chip 100.

In the new chip 100, a chip pad 322 is formed to be connected to the third connection terminal 314. If the new chip 100 is the same as the chip 100 of the present invention, the chip pad 322 may be the top pad 130 described above.

FIG. 12A is a plan view illustrating a structure in which a new chip 100 is connected to a circuit board 300 in a horizontal direction in the package of FIG. 10B, and FIG. 12B is a cross-sectional view taken along line C-C of FIG. 12A. The present example is for modularizing the plurality of chips 100 using the first side pad 120 and the first dimple 170 of the package of FIG. 10B.

12A and 12B, when the plurality of chips 100 are connected by the second connection terminal 312 in the horizontal direction, the size of the package may be reduced as compared with the arrangement of the chips 100 independently. . That is, in an independently arranged package, a second connection terminal 312 for connecting to an external circuit such as the circuit board 300 is required for each chip 100. However, the illustrated package of the present invention uses the second connection terminal 312 for connecting the two chips 100 in common to the two chips 100, thereby reducing the size of the package.

On the other hand, the packages arranged independently requires a circuit (not shown) for connecting to an external circuit inside each chip 100. However, the package of the present invention can share the circuit, there is an advantage that the size of the chip 100 can be reduced. In the drawings, the same chip 100 is horizontally connected, but in some cases, chips including different electrical structures may be connected to each other.

The package of the present invention can be expanded two-dimensionally as shown in FIG. 13 using the first side pad 120 and the first dimple 170 by applying the concept described above. The two-dimensionally extended package can further reduce the size of the package and chip. Even in this case, chips including different electrical structures may be connected.

14 and 15 are cross-sectional views illustrating modified examples of the second connection terminal of FIG. 10A. In this case, the height of the first side pad 120 may be adjusted using the second dimple 180 of the present invention.

Specifically, as shown in FIG. 14, the second connection terminal may be formed as a connection terminal 316 having a quadrangular cross section, and may be formed as a connection terminal 318 having a triangular cross section as shown in FIG. 15. The connecting terminals 316 and 318 in the form of square and triangle cross-sections are provided by way of example only, and other types of connecting terminals may be implemented as necessary.

 By using the connection terminals 316 and 318 having a rectangular and triangular cross-sectional shape, a contact area between the first substrate pad 320, the first side pad 120, and the second dimple 180 can be sufficiently secured. . Therefore, the adhesive force between the circuit board 300 and the chip 100 by the square and triangular connection terminals 316 and 318 may be more firm than the ball type connection terminals. Here, the connection terminal 318 having a triangular cross-sectional shape may be formed by sufficiently reflowing the connection terminal 316 having a rectangular cross-sectional shape manufactured by a conventional method.

16A is a plan view illustrating another embodiment of a structure of a package using a chip of the present invention, and FIG. 16B is a cross-sectional view taken along the line D-D of FIG. 16A. In this case, the circuit board 300, the first connection terminal 310, the second connection terminal 312, the first substrate pad 320, and the chip 100 are the same as those described with reference to FIG. 10B. That is, the above description may be applied as it is except for the connection portion by the bonding wire 330. Accordingly, the second connection terminal 312 may use various forms as shown in FIGS. 14 and 15.

Referring to FIGS. 16A and 16B, a package includes a circuit board 300 including an electric circuit and a chip 100 of the present invention placed directly on the circuit board 300. The circuit board 300 and the chip 100 are connected to each other by using the first side pad 120 and the first substrate pad 320 by the second connection terminal 312. The number of second connection terminals 312 may vary depending on the type of package. For example, a package requiring fewer input / output pads may have a smaller number of second connection terminals 312, and a package requiring a large number of input / output pads may have a larger number of second connection terminals 312. Can lose. The first dimple 170 adjusts the height of the first dimple 170 so that the second connection terminal 312 may be connected to the first side pad 120 and the first substrate pad 320. Also, although the second connection terminal 312 is formed on all sidewalls of the chip 100 in the drawing, the second connection terminal 312 may be formed only on some sidewalls of the chip 100.

The upper pad 130 formed on the upper surface of the chip 100 and the second substrate pad 332 formed on the circuit board 300 are connected by the bonding wires 330. The bonding wire 330 may be attached to the pads 130 and 332 using a conventional wire bonding method or a tape to which the bonding wire 330 is attached.

The number of bonding wires 330 may vary depending on the type of package. For example, a package requiring a small number of input / output pads may have a smaller number of bonding wires 330, and a package requiring a large number of input / output pads may have a larger number of bonding wires 330. In addition, although the bonding wires 330 are all formed at the corners of the upper surface of the chip 100 in the drawing, the bonding wires 330 may be formed only at some corners of the upper surface of the chip 100.

Although not shown, the package having the bonding wire 330 may have a structure stacked in a direction perpendicular to the circuit board 300 as shown in FIG. 11. At this time, the upper pad 130 is connected by a third connecting terminal (314 in FIG. 11) such as solder balls, and a new chip (100 in FIG. 11) is stacked. The new chip 100 may be the chip 100 of the present invention, or in some cases, may be a different chip from the chip 100.

The side pads, the first dimples and the top pads may be used in combination with each other. That is, the number of side pads, first dimples and top pads may be adjusted according to the type of package. For example, a package requiring fewer input / output pads may have a smaller number of side pads, first dimples, and a top pad, and a package requiring a large number of input / output pads may have a number of side pads and a top pad, respectively. Can also be a lot.

The method of combining the side pads, the first dimples and the top pads can be presented in various ways. Here are some ways that can be practically applied to a package: In the first method, as shown in FIG. 16A, first side pads 120 and first dimples 170 are formed on all sidewalls of the chip 100, and top pads 130 are formed on all edges of the top surface of the chip 100. To electrically connect the chip 100 and the circuit board 300. In the second method, the first side pads 120 and the first dimples 170 are formed on all sidewalls of the chip 100, and the top pads 130 are formed only at some edges of the top surface of the chip 100. ) And the circuit board 300 are electrically connected. This will be described with reference to FIGS. 17A to 19.

In the third method, the first side pad 120 and the first dimple 170 are formed on some sidewalls of the chip 100, and the top pad 130 is formed at all corners of the top surface of the chip 100. ) And the circuit board 300 are electrically connected to each other. Although this will not be described separately, it will be conceptually sufficiently accessible in the description of other methods below. The fourth method forms the first side pad 120 and the first dimple 170 on some sidewalls of the chip 100, and forms the top pad 130 only at some edges of the top surface of the chip 100. ) And the circuit board 300 are electrically connected. This will be described with reference to FIG. 20.

 FIG. 17A is a plan view illustrating a method of packaging the side pad 120, the first dimple 170, and the top pad 130 according to the present invention. FIG. 17B is a cross-sectional view taken along the line E-E of FIG. 17A.

17A and 17B are examples of applying the second method. That is, the first side pad 120 and the first dimple 170 are formed on all sidewalls of the chip 100, and the top pad 130 is formed only at one corner of the top surface of the chip 100 to form the chip 100. ) And the circuit board 300 are electrically connected. The first side pad 120, the first dimple 170, and the first substrate pad 320 are connected by the second connection terminal 312, and the top pad 130 and the second substrate pad 332 are bonded. Connected by wire 330.

18 illustrates an example in which the first side pads 120 and the first dimples 170 are formed on all sidewalls of the chip 100, and the top pads 130 are formed at two corners of the top surface of the chip 100. It is a top view showing. 19 illustrates a case in which the first side pads 120 and the first dimples 170 are formed on all sidewalls of the chip 100, and the top pads 130 are formed at three corners of the top surface of the chip 100. It is a top view showing.

As in the first and second methods, the first side pad 120, the first side pad 120, and the first side pad 120 connected to the circuit board 300 are combined by combining the first side pad 120, the first dimple 170, and the top pad 130. The number of the dimples 170 and the top pad 130 may be appropriately dispersed. Particularly, when the top pad 130 is electrically connected to all or some corners of the top surface while the first side pad 120 and the first dimple 170 are formed on all sidewalls, the size of the chip 100 and the package may be reduced. Can be. Furthermore, the pads may be appropriately disposed according to the shape of the chip 100 or the package by not forming the bonding wires 330 at some corners of the upper surface.

In addition, according to the second method of the present invention, as described with reference to FIGS. 12A to 13, the chip 100 may be connected to the edge portion where the bonding wire 330 is not formed. When the plurality of chips 100 are connected by the second connection terminal 312, the size of the package may be reduced compared to that of the chips 100 independently. In addition, the package of the present invention may be extended two-dimensionally as shown in FIG. 13 by using the first side pad 120 and the first dimple 170 by applying the concept described above. Expanding in two dimensions can further reduce the size of packages and chips.

20 is an example of applying the above fourth method. That is, the first side pad 120 and the first dimple 170 are formed on some sidewalls of the chip 100, and the top pad 130 is formed on a part of the top surface of the chip 100, for example, one corner. The chip 100 and the circuit board 300 are electrically connected to each other. The first side pad 120 and the first substrate pad 320 are connected by the second connection terminal 312, and the top pad 130 and the second substrate pad 332 are connected by the bonding wire 330. do.

As shown in FIG. 20, when the first side pad 120 and the top pad 130 are disposed, the size of the chip 100 and the package may be reduced. That is, since the first side pad 120 and the first dimple 170 are not formed on some sidewalls, a circuit for connecting to an external circuit may not be disposed in the chip 100.

21A is a plan view illustrating another embodiment of a package structure using a chip of the present invention, and FIG. 21B is a cross-sectional view taken along the line F-F of FIG. 21A.

Referring to FIGS. 21A and 21B, a circuit board 300 including an electrical circuit and a chip 100 such as a semiconductor chip are included. The chip 100 is attached to the circuit board 300 via a third connection terminal 314, and has sidewalls 120 and a first side pad 120 formed of a plurality of conductive patterns separated from each other in the vertical direction of the sidewalls. Two dimples 180. That is, except for the shape of the package, the chip used in the package described herein uses side pads with separated conductive patterns.

The first side pad 120 is connected to the first substrate pad 320 on the circuit board 300 by a connection terminal 316 having a rectangular cross section. In addition, the third substrate pad 340 and the top pad 130 on the circuit board 300 below the chip 100 are connected by the third connection terminal 314. In the drawing, although the connection terminal 316 having a rectangular cross-sectional shape is presented, various types of connection terminals may be applied within the scope of the present invention.

As mentioned above, although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible. For example, the conductive pattern constituting the side pads may be formed at the same time as the metal wirings, the circuit wirings, and the vias inside the chip, but may be formed at the same time as the redistribution lines for forming the bonding pads such as the upper pads. .

The chip having the side pad according to the present invention described above may have a dimple capable of adjusting the height of the conductive pattern separated on the sidewall, thereby appropriately adjusting the height of the conductive pattern. Furthermore, the dimple is formed simultaneously with the process of forming the electrical structure inside the chip, so that a separate photolithography process is not required.

In addition, the package using the chip is placed directly on the circuit board, it is possible to greatly reduce the thickness of the single-layer or laminated package. In addition, the size of the package may be reduced by horizontally connecting the chips using side pads and dimples.

Furthermore, by using a combination of the side pads, dimples and the top pad, the number of pads can be adjusted in various ways according to the type of package, thereby reducing the size of the package.

Claims (39)

A side pad exposed on sidewalls and formed of a plurality of conductive patterns separated from each other in a vertical direction of the sidewalls; And And a dimple including a dimple positioned above and below the side pad to adjust a position of the side pad. The chip of claim 1, wherein the sidewalls have one or more dimples. The chip having a dimple of claim 1, wherein the side pad is a first side pad having an insulating layer disposed between the conductive patterns. The chip of claim 1, wherein the side pad is a second side pad having a conductive buried pattern embedded between the conductive patterns. Claim 5 was abandoned upon payment of a set-up fee. The chip of claim 1, wherein a shape of the dimple is determined by a process of forming an electrical structure inside the chip. Claim 6 was abandoned when the registration fee was paid. The chip of claim 1, wherein the dimple comprises at least one layer selected from the group consisting of aluminum, copper, tungsten, molybdenum, and conductive metal nitride. Claim 7 was abandoned upon payment of a set-up fee. The chip of claim 1, wherein a position of the dimple is determined according to a type of package. The chip of claim 1, further comprising a conductive upper pad on an upper surface of the chip defined by the sidewalls. Forming an electrical structure on the substrate on which the scribe line is defined; Forming a first dimple material layer on the substrate between the electrical structures; Forming a plurality of pad conductive patterns on the first dimple material layer, the plurality of pads being vertically divided over the scribe line; Covering the substrate on which the pad conductive pattern is formed with a protective insulating film; And Removing the protective insulating layer, the pad conductive pattern, and the first dimple material layer by a width of the scribe line to form a conductive pattern and a first dimple. The method of claim 9, wherein the first dimple is formed simultaneously with forming the electrical structure. The method of claim 9, wherein the forming of the pad conductive pattern includes: Forming a first interlayer insulating film on the substrate; Forming a first pad conductive pattern on the first interlayer insulating film; Forming a second interlayer dielectric layer covering the first pad conductive pattern and the first interlayer dielectric layer; And forming a conductive pattern for a second pad on the second interlayer insulating film. The method of claim 11, wherein the forming of the first pad conductive pattern and the second pad conductive pattern comprises: And forming a buried conductive pattern between the first pad conductive pattern and the second pad conductive pattern. Claim 13 was abandoned upon payment of a registration fee. 10. The method of claim 9, further comprising forming a top pad on the protective insulating film. Forming an electrical structure on the substrate on which the scribe line is defined; Forming a plurality of pad conductive patterns on the substrate, the plurality of pads being vertically separated from the scribe line; Covering the substrate on which the pad conductive pattern is formed with a protective insulating film; Forming a second dimple material layer on the pad conductive pattern in the protective insulating film; And Removing the protective insulating layer, the pad conductive pattern, and the second dimple material layer by a width of the scribe line to form a conductive pattern and a second dimple. A circuit board including an electric circuit; A side pad disposed directly on the circuit board and exposed to the side wall, the side pad including a plurality of conductive patterns separated from each other in the vertical direction of the side wall, and dimples positioned above and below the side pad to adjust the position of the side pad Chips to make; And A package using a chip having a dimple including a second connection terminal for electrically connecting the circuit board and the side pad. Claim 16 was abandoned upon payment of a setup registration fee. The package of claim 15, wherein the side pad is a first side pad having an insulating layer disposed between the conductive patterns. Claim 17 was abandoned upon payment of a registration fee. The package according to claim 15, wherein the side pads are second side pads having conductive buried patterns embedded between the conductive patterns. 16. The package of claim 15, wherein the chip is placed on the circuit board without physical or chemical bonding. Claim 19 was abandoned upon payment of a registration fee. The package using a chip having a dimple of claim 15, further comprising an adhesive layer for adhesion between the chip and the circuit board. Claim 20 was abandoned upon payment of a registration fee. The package using a chip having a dimple of claim 15, wherein the second connection terminal is any one or a plurality of solder balls, a rectangular cross section, and a triangular cross section. Claim 21 was abandoned upon payment of a registration fee. The package of claim 15, further comprising a top pad on an upper surface of the chip. Claim 22 was abandoned upon payment of a registration fee. 22. The package of claim 21, further comprising one or a plurality of chips stacked vertically with respect to the circuit board by a third connection terminal connected to the top pad. delete Claim 24 was abandoned when the setup registration fee was paid. 22. The package using a chip with dimples according to claim 21, wherein the dimples, the side pads and the top pads can be used in combination. Claim 25 was abandoned upon payment of a registration fee. 25. The package of claim 24, wherein the number of the combined dimples, side pads, and top pads is determined by the number of electrical input and output pads required by the chip. Claim 26 was abandoned upon payment of a registration fee. 25. The package of claim 24, wherein the dimples and side pads are disposed on all sidewalls of the chip, and the top pads are disposed on all corners of the top surface of the chip. Claim 27 was abandoned upon payment of a registration fee. 25. The package of claim 24, wherein the dimples and the side pads are disposed on all sidewalls of the chip, and the top pads are disposed at some corners of the top surface of the chip. Claim 28 was abandoned upon payment of a registration fee. 25. The package of claim 24, wherein the dimples and the side pads are disposed on some sidewalls of the chip, and the top pads are disposed at all corners of the top surface of the chip. Claim 29 was abandoned upon payment of a set-up fee. 25. The package of claim 24, wherein the dimples and the side pads are disposed at some side surfaces of the chip, and the top pads are disposed at some corners of the top surface of the chip. A first chip including a side pad formed of a plurality of conductive patterns exposed to sidewalls and separated from each other in a vertical direction of the sidewalls, and dimples positioned above and below the sidepads to adjust a position of the sidepads; Side pads formed independently of the first chip and exposed to sidewalls and separated from each other in the vertical direction of the sidewalls and dimples positioned above and below the sidepads to adjust the position of the sidepads A second chip comprising; And A package using a chip having a dimple including a second connection terminal for electrically connecting the first side pad and the second side pad. 32. The package of claim 30, wherein the first and second chips are extended in two dimensions by the second connection terminal. Claim 32 was abandoned upon payment of a registration fee. 31. The package of claim 30, wherein at least one of the first chip and the second chip further comprises a top pad formed on the top surface to contact the bonding wire. Claim 33 was abandoned upon payment of a registration fee. 33. The package of claim 32, further comprising one or a plurality of chips stacked vertically with respect to the circuit board by a third connection terminal connected to the top pad. A circuit board including an electrical circuit; And A side pad formed of a plurality of conductive patterns separated from each other in the up and down direction of the side wall while being exposed to the side wall and attached to the circuit board via an electrical connection terminal, and positioned on the upper and lower sides of the side pad. A chip comprising a dimple to adjust the; And A package using a chip having a dimple including a second connection terminal for electrically connecting the circuit board and the side pad. Claim 35 was abandoned upon payment of a registration fee. 35. The package of claim 34, wherein the side pad is a first side pad having an insulating layer disposed between the conductive patterns. Claim 36 was abandoned upon payment of a registration fee. Claim 37 was abandoned upon payment of a registration fee. 35. The package of claim 34, wherein the second connection terminal is any one or a plurality of solder balls, rectangular cross-sectional shapes, and triangular cross-sectional shapes. Claim 38 was abandoned upon payment of a registration fee. 35. The package of claim 34, further comprising a conductive upper pad on an upper surface of the chip defined by the sidewalls. 39. The package of claim 38, further comprising one or a plurality of chips stacked vertically with respect to the circuit board by a third connection terminal connected to the top pad.

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