KR100843232B1 - Chip having side pad, method of fabrication the same and package using the chip - Google Patents

Abstract

A chip having a side pad, a manufacturing method thereof, and a package using the same are provided to reduce the size of a package by mounting the package on a printed circuit board directly. A chip(100) includes a side pad(120) which is exposed to the sidewall and composed of a plurality of conductive patterns(120a,120b) separated in the vertical direction of the sidewall. The sidewall is composed of one or more side pads. The side pad includes a first side pad having an insulating layer arranged between the conductive patterns, and a second side pad having a conductive buried pattern buried between the conductive patterns. The number of conductive patterns is determined by the shape of the side pad.

Description

Chip having side pad, method of fabrication and package using same chip {Chip having side pad, method of fabrication the same and package using the chip}

1 is a perspective view schematically showing a conventional chip.

2 is a perspective view schematically showing an embodiment of a chip of the present invention.

Figure 3 is a perspective view schematically showing a modification of one embodiment of a chip of the present invention with a top pad attached.

4 is a plan view illustrating a process of separating the substrate of the present invention into chips.

5A through 5C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing a chip according to an embodiment of the present invention.

6 is a perspective view schematically showing another embodiment of the chip of the present invention.

7A to 7C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing a chip according to another embodiment of the present invention.

8 is a perspective view illustrating a process of simultaneously forming an electrical structure and a side pad in the chip of the present invention.

9A to 9C are plan views illustrating a relationship between an electrical structure including metal wires, vias, and circuit wires, and a second side pad, respectively.

10A is a plan view illustrating an embodiment of a structure of a package using a chip of the present invention, and FIG. 10B is a cross-sectional view taken along line B-B of FIG. 10A.

FIG. 11 is a cross-sectional view illustrating a structure in which a new chip is stacked in a direction perpendicular to a circuit board in the package of FIG. 10B.

FIG. 12A is a plan view illustrating a structure in which a new chip is connected to the circuit board in a direction horizontal to the circuit board of FIG. 10B, and FIG. 12B is a cross-sectional view taken along line C-C of FIG. 12A.

FIG. 13 is a plan view illustrating a package in which the structure of FIG. 12A is extended two-dimensionally. FIG.

14 and 15 are cross-sectional views illustrating modified examples of the second connection terminal of FIG. 10A.

16A is a plan view illustrating another embodiment of a structure of a package using a chip of the present invention, and FIG. 16B is a cross-sectional view taken along the line D-D of FIG. 16A.

17A is a plan view illustrating a method of packaging by combining the side pad and the top pad of the present invention. FIG. 17B is a cross-sectional view taken along the line E-E of FIG. 17A.

18 is a plan view illustrating a case in which side pads are formed on all sidewalls of a chip of the present invention, and top pads are formed at two corners of an upper surface of the chip.

19 is a plan view illustrating a case in which side pads are formed on all sidewalls of a chip of the present invention, and top pads are formed at three corners of an upper surface of the chip.

20 is a plan view illustrating an example in which side pads are formed on a portion of sidewalls of a chip of the present invention, and top pads are formed at some edges of an upper surface of the chip.

21A is a plan view illustrating another embodiment of a package structure using a chip of the present invention, and FIG. 21B is a cross-sectional view taken along the line F-F of FIG. 21A.

* Description of the symbols for the main parts of the drawings *

100; Chip 102; Board

108a, b; Pad conductive patterns 108; Material layer for side pad

120a, b; Conductive pattern 120; First side pad

130; Upper pad 160; 2nd side pad

200a; Layer to Form Metallization

200b; Layers to form vias

200c; Layer to Form Circuit Wiring

210; Metallization 212; Via

214; Circuit wiring 300; Circuit board

310; First connection terminal 320; 2nd connection terminal

320; First substrate pad 330; Bonding Wire

The present invention relates to a chip such as a semiconductor chip of the present invention, a method for manufacturing the same, and a package thereof, and more particularly, to a chip including a side pad, a method for manufacturing the same, and a package using the chip.

As the size of electronic products becomes smaller, the size of electronic devices corresponding thereto is also decreasing. In spite of the small size of the device, there is a demand for a chip having a large device capacity and an excellent function, for example, a semiconductor chip. Accordingly, the package using the chip also requires a small size, a large capacity and a fast processing speed.

In the manufacturing process of a semiconductor chip, a semiconductor wafer (or substrate) is divided into a plurality of chips (or dies) defined by scribe lines formed on the surface of the wafer. The wafer is cut along each scribe line by, for example, a diamond-tipped cutter and separated into individual chips.

A chip 10, such as a conventional semiconductor chip, may be formed of an upper surface 20 on which a pad 40 is formed and a side wall 30 with respect to the upper surface 20, as shown in FIG. 1. In this case, the upper surface 20 may be an active surface, and the pad 40 may be, for example, an input / output pad for electrical signal processing. By the way, since the size of the chip 10 is getting smaller, it becomes difficult to arrange | position the pad 40 suitably.

Accordingly, an object of the present invention is to provide a chip capable of appropriately arranging pads capable of electrical signal processing in response to a smaller chip size. In addition, another technical problem is to provide a method for manufacturing the chip. Furthermore, another technical problem is to provide various types of packages using the chip.

Chip having a side pad according to the present invention for achieving the above technical problem includes a side pad made of a plurality of conductive patterns exposed to the side wall, separated from each other in the vertical direction of the side wall.

In this case, the side pad may be a first side pad having an insulating layer disposed between the conductive patterns, and may be a second side pad having a conductive buried pattern embedded between the conductive patterns.

In a preferred embodiment of the present invention, the conductive pattern and the buried pattern may be located on the side of the layer for forming the electrical structure inside the chip. For example, the electrical structure may be metal wiring, circuit wiring and via.

According to another aspect of the present invention, there is provided a method of manufacturing a chip having a side pad according to the present invention, which forms an electrical structure on a substrate on which a scribe line is defined. Thereafter, a plurality of pad conductive patterns are formed on the substrate, the plurality of pads being vertically separated while covering the scribe lines. The substrate on which the pad conductive pattern is formed is covered with a protective insulating film. The protective insulating layer and the pad conductive pattern are removed by the width of the scribe line to form a conductive pattern. In this case, the pad conductive pattern may be simultaneously formed with the electrical structure.

One package using a chip having a side pad according to the present invention for achieving the above another technical problem is a circuit board including an electrical circuit and directly placed on the circuit board and exposed to the sidewalls each other in the vertical direction of the sidewalls It includes a chip including a side pad made of a plurality of separated conductive patterns. And a second connection terminal electrically connecting the circuit board and the side pad.

In the present invention, the side pad and the top pad can be used in combination. That is, the number of side pads and top pads combined may be determined by the number of electrical input and output pads required by the chip.

Specifically, the side pads may be disposed on all sidewalls of the chip, and the top pads may be disposed on all edges of the top surface of the chip. In addition, the side pads may be disposed on all sidewalls of the chip, and the top pad may be disposed at some edges of the top surface of the chip. Further, the side pads may be disposed on some sidewalls of the chip, and the top pads may be disposed at all corners of the top surface of the chip. The side pads may be disposed on some side surfaces of the chip, and the top pads may be disposed on some edges of the top surface of the chip.

Another package using a chip having a side pad according to the present invention for achieving the above another technical problem is a first chip including a side pad made of a plurality of conductive patterns exposed to the side wall and separated from each other in the vertical direction of the side wall And a second chip disposed independently of the first chip, the side chip including a plurality of conductive pads exposed on sidewalls and separated from each other in a vertical direction of the sidewalls. The apparatus may further include a second connection terminal electrically connecting the first side pad and the second side pad. The first chip and the second chip may be extended two-dimensionally in a horizontal direction with respect to the circuit board by the second connection terminal.

Another package using a chip having a side pad according to the present invention for achieving the above another technical problem is a circuit board including an electrical circuit and attached to the circuit board via an electrical connection terminal, the side wall The chip may include a chip including side pads exposed and separated from each other in a vertical direction of the side wall. In addition, a second connection terminal for electrically connecting the circuit board and the side pad.

The packages proposed in the present invention may stack the chip of the present invention or a new chip in a vertical direction with respect to the circuit board.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Like reference numerals denote like elements throughout the embodiments.

Embodiments of the present invention will propose a chip comprising a conductive pad made of a plurality of conductive patterns exposed to the side wall and separated from each other in the vertical direction of the side wall. The chip may be referred to as a die as a conventional semiconductor chip, and the chip may be denoted by the same reference numeral for convenience of description even with slight modifications. In addition, since the chip may be packaged in various forms, examples of packages using the chip will be listed in detail following the description of the chip. Accordingly, the chip and the package will be said to share the features of the present invention. Hereinafter, the conductive pad will be given an appropriate name and reference numeral according to the embodiment.

<Example about Chip>

2 is a perspective view schematically showing an embodiment of the chip 100 of the present invention.

According to FIG. 2, a chip 100, such as a semiconductor chip, forms at least one sidewall 150 with respect to the top surface 140 and the top surface 140, the so-called active surface. In the figure, a chip 100 providing four sidewalls 150 is shown. However, in some cases, a chip having various numbers of sidewalls may be used.

The first side pad 120, which is a conductive pad, is formed of a plurality of conductive patterns 120a and 120b exposed to the sidewall 150 and separated from each other in the vertical direction of the sidewall 150. The first side pad 120 may protrude from the side wall 150, but preferably has the same plane as the side wall 150. Although not indicated by reference numerals between the conductive patterns 120a and 120b, an insulating film such as a silicon oxide film is positioned.

Although two conductive patterns 120a and 120b are exemplified in the drawing, as will be described later, the number of conductive patterns may be set differently as necessary. The conductive patterns 120a and 120b may be formed of at least one layer selected from conductive metal nitride layers such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride.

Shapes such as width and thickness of the conductive patterns 120a and 120b may be set in consideration of the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. In addition, the position and number of the first side pads 120 may also be variously determined by the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. For example, the position of the first side pad 120 may vary depending on the thicknesses of the second interlayer insulating layer 110 and the conductive patterns 120a and 120b, respectively. In particular, the first side pad 120 associated with the package will be described in detail later.

An upper pad 130, which is another conductive pad, may be attached to the upper surface 140 of the chip 100 of FIG. 2. The upper pad 130 may be formed of at least one layer selected from conductive metal nitride layers such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride. The number of top pads 130 may vary depending on the type of package. This will be described later in detail.

4 is a plan view illustrating a process of separating a substrate 102 such as a semiconductor wafer into a chip 100 of the present invention. In other words, the side pad material layer 108 is disposed on the scribe line SL and the chip 100 in a portion (a) of the substrate 102 having the plurality of chips 100. The scribe lines SL extend in plan while maintaining the same width. An upper pad 130 is disposed on each chip 100. The distance between the opposing first side pads (120 in FIG. 4C) defines the width of the scribe line SL. In other words, the material layer 108 for the first side pad to be removed is determined according to the width of the scribe line SL.

5A through 5C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing the chip 100 according to an embodiment of the present invention.

Referring first to FIG. 5A, a conductive region 104 is formed on a substrate 102. The conductive region 104 may be one of the electrical structures to be presented later. In this case, the substrate 102 may be a semiconductor wafer or multiple patterns (not shown) may be formed on the wafer. Subsequently, the substrate 102 on which the conductive region 104 is formed is covered by the first interlayer insulating film 106. The first interlayer insulating film 106 may be formed by, for example, depositing a silicon oxide film.

Referring to FIG. 5B, a pad conductive pattern 108b is formed on the planarized first interlayer insulating layer 106 to cover a portion of the scribe line SL. Thereafter, as illustrated, the first interlayer insulating film 106 and the pad conductive pattern 108b are covered with the second interlayer insulating film 110, and the pad conductive pattern 108a is formed on the second interlayer insulating film 110. do. The pad conductive patterns 108a and 108b are a material layer 108 for forming the first side pad 120 of the present invention. Subsequently, a protective interlayer insulating film 112 covering the second interlayer insulating film 110 and the pad conductive pattern 108a and the top pad 130 described with reference to FIG. 3 may be formed on the surface thereof.

The shape of the chip 100 such as the width and thickness of the pad conductive patterns 108a and 108b, the type of the package, and the process of forming an electrical structure inside the chip 100 may be set. In addition, the position and number of the first side pad material layer 108 and the top pad 130 may also vary depending on the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. You can decide. For example, the height of the first side pad material layer 108 may vary depending on the thicknesses of the second interlayer insulating layer 110 and the pad conductive patterns 108a and 108b, respectively.

The pad conductive patterns 180a and 108b may be formed together when forming the electrical structure inside the chip 100. For example, a region for forming pad conductive patterns 108a and 108b is added to a mask for forming electrical wiring inside the chip 100, and the pad conductive patterns 108a, 108b). That is, a separate photolithography process for forming the pad conductive patterns 108a and 108b is not required. This will be described later in detail.

Referring to FIG. 5C, the substrate 102 is cut along each scribe line SL by a diamond-tipped cutter, as shown in FIG. 4, and separated into respective chips 100. When the chip 100 is individualized, the side surface of the chip 100 is exposed to the first side pad 120 made of the conductive patterns 120a and 120b from which a portion of the side pad material layer 108 is removed.

6 is a perspective view schematically showing another embodiment of the chip 100 of the present invention. Here, the chip 100 may include the chip of FIG. 3 except for the second side pad 160 including a conductive pattern 160a (hereinafter referred to as a buried pattern) formed by a separate filling filling between the conductive patterns 120a and 120b. Same as 100).

As shown, the buried pattern 160a filling between the conductive patterns 120a and 120b is at least one layer selected from among conductive metal nitride films such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride or tungsten nitride. Can be done. That is, the exposed side surface of the second side pad 160 may be integrated with a conductive material.

Shapes such as the width and thickness of the buried pattern 160a may be set in consideration of the shape of the chip 100, the type of package, and the process of forming an electrical structure inside the chip 100. In addition, the position and the number of the second side pads 160 may also be variously determined by the shape of the chip 100, the type of the package, and the process of forming an electrical structure inside the chip 100. For example, the position of the second side pad 160 may vary depending on the thicknesses of the second interlayer insulating layer 110, the conductive patterns 120a and 120b, and the buried pattern 160a, respectively.

7A to 7C are cross-sectional views taken along the line A-A of FIG. 4 to explain a process of manufacturing the chip 100 according to another embodiment of the present invention.

Referring to FIG. 7A, a conductive region 104 is formed on the substrate 102. In this case, the substrate 102 may be a semiconductor wafer or multiple patterns (not shown) may be formed on the wafer. Subsequently, the substrate 102 on which the conductive region 104 is formed is covered by the first interlayer insulating film 106. The first interlayer insulating film 106 may be formed by, for example, depositing a silicon oxide film.

Subsequently, a pad conductive pattern 108b is formed on the planarized first interlayer insulating film 106 to cover a portion of the scribe line SL. Thereafter, the first interlayer insulating film 106 and the pad conductive pattern 108b are covered with the second interlayer insulating film 110 as shown. A part of the second interlayer insulating film 110 is removed using a conventional photolithography method to expose the top surface of the pad conductive pattern 108b. After filling the conductive pattern 152a for filling in the portion of the second interlayer insulating film 110 removed, a flat top surface is formed. The width of the filling conductive pattern 152a may be the same as that of the pad conductive pattern 108b, but is not necessarily limited thereto.

Referring to FIG. 7B, a pad conductive pattern 108a is formed on the second interlayer insulating film 110. The patterns 108a, 152a, and 108b are a material layer 154 for forming the second side pad 160 of the present invention. Subsequently, a protective insulating film 112 covering the second interlayer insulating film 110 and the pad conductive pattern 108a and the top pad 130 described with reference to FIG. 3 may be formed on the surface thereof.

The filling conductive pattern 152a may be formed together to form an electrical structure inside the chip 100. For example, a region for forming a filling conductive pattern 152a may be added to a mask for forming a via in the chip 100 to form a filling conductive pattern 152a at the same time as the via is formed. have. That is, a separate photolithography process for forming the filling conductive pattern 152a is not required. This will be described later in detail.

Referring to FIG. 7C, the substrate 102 is cut along each scribe line SL by a diamond-tipped cutter, for example, and separated into respective chips 100. When each chip 100 is individualized, the side surface of the chip 100 may include a second side pad 160 formed of patterns 120a, 160a, and 120b from which some of the patterns 108a, 152a, and 108b are removed. Is exposed. The process of separating the chip 110 is as described above.

8 is a perspective view for explaining a process of simultaneously forming the electrical structure and the side pad 160 inside the chip 100 of the present invention. At this time, the side pad of the present invention is applied to the second side pad 160 of FIG.

Referring to FIG. 8, the second side pad 160 includes a buried pattern 160a embedded between the separated conductive patterns 120a and 120b. The conductive patterns 120a and 120b are respectively located on the side of the layer for forming the via and the layer for forming the circuit wiring, and the buried pattern 160a for forming the via. To illustrate that the layers are formed simultaneously with the patterns 120a, 120b, 152a of the present invention, they are presented by way of example.

9A to 9C are plan views illustrating a relationship between an electrical structure including metal wirings, vias, and circuit wirings, respectively, and the second side pad 160. In the exemplary embodiment of the present invention, the conductive pattern formed on the side of the layer 200a for forming the metal wiring 210 is assumed to be the conductive pattern 120a of the uppermost layer of the second side pad 160. That is, the process of forming the metal wiring 210 and the process of forming the uppermost conductive pattern 120a may be performed.

In addition, the conductive pattern formed on the side surface of the layer 200c for forming the circuit wiring 214 was determined as the conductive pattern 120b of the lowermost layer of the second side pad 160. That is, the process of forming the circuit wiring 214 can be performed and the process of forming the lowermost conductive pattern 120b can be performed. In some cases, the positions of the conductive patterns 120a and 120b may be interchanged. Reference numeral 220 denotes a circuit element inside the chip 100.

The conductive pattern formed on the side of the layer 200b for forming the via 212 may be a buried pattern 160a of the second side pad 160. In other words, the via pattern 212 may be formed at the same time as the via 212 is formed.

In an embodiment of the present invention, the side pads formed on the side of the chip 100 may include a first side pad 120 having two separate conductive patterns and a second side pad 160 having a buried pattern added to the first side pads. ) As an example. However, the side pad of the present invention can determine the number of conductive patterns and buried patterns separated within the scope of the present invention. The number may vary depending on the thickness of each conductive pattern and the buried pattern and the type of package. Accordingly, two or more separated conductive patterns may be provided, and thus the number of buried patterns may vary.

For example, in current LSIs, up to seven separate conductive patterns are possible. Accordingly, up to six buried patterns may be possible. In addition, the buried pattern does not necessarily need to be formed between all the separated conductive patterns. In other words, in the case of the above LSI, if necessary, less than six buried patterns can be formed.

<Example for Package>

10A is a plan view illustrating an embodiment of a structure of a package using a chip of the present invention, and FIG. 10B is a cross-sectional view taken along line B-B of FIG. 10A. At this time, the chip 100 is applied to the first side pad 120 of FIG. The first side pad 120 is merely described as an example, and the side pad may be applied to all the pads described above within the scope of the present invention.

10A and 10B, a package includes a circuit board 300 including an electric circuit and a chip 100 of the present invention placed directly on the circuit board 300. One surface of the circuit board 300 is attached with a first connection terminal 310, for example, a solder ball, for electrical connection to the outside of the package, and the other surface with the first substrate pad 320 for electrical connection with the chip 100. ) Is formed. The chip 100 of the present invention is directly placed on the substrate 300 between the first substrate pads 320.

The circuit board 102 applied to the present invention is not particularly limited, but may be a printed circuit board having at least one layer or a circuit board for a film package in which a circuit pattern is formed on a polymer film. The circuit board may be applied to various applications, for example, signal processing of a memory device, a display device, or a DDI device. In particular, since circuit boards are moving toward reducing size and weight, various types and types of circuit boards are expanding their application fields.

A chip 100, such as a semiconductor chip, forms an upper surface (140 in FIG. 2), which is called an active surface, and at least one sidewall (150 in FIG. 2) with respect to the upper surface. Although the chip 100 providing four sidewalls is shown in the drawing, a chip having various numbers of sidewalls may be used in some cases. The chip 100 includes a first side pad 120 that is a conductive pad made of a plurality of conductive patterns 120a and 120b separated from each other in the vertical direction of the sidewall while being exposed to the sidewall.

Placed directly on the circuit board 300 means that no material layer is inserted between the circuit board 300 and the chip 100. And, it means that the chip 100 is located on the circuit board 300 without any physical or chemical coupling between the circuit board 300 and the chip 100. Accordingly, a conventional adhesive layer is not required between the circuit board 300 and the chip 100. Since the chip 100 is directly placed on the circuit board 300 and there is no adhesive layer, the height (or thickness) of the package may be greatly reduced. However, in some cases, the chip 100 may be attached onto the circuit board 300 using the adhesive layer.

  The circuit board 300 and the chip 100 are connected to each other using the first side pad 120 and the first substrate pad 320 by the second connection terminal 312. In this case, the first side pad 120 may serve as an input / output pad and the second connection terminal 312 may serve as an input / output terminal. In one embodiment of the present invention provides a second connection terminal 312 in the form of a solder ball. The first and second connection terminals 310 and 312 may be formed by a conventional method, and are attached to the respective pads by performing a reflow process.

The number of second connection terminals 312 may vary depending on the type of package. For example, a package requiring fewer input / output pads may have a smaller number of second connection terminals 312, and a package requiring a large number of input / output pads may have a larger number of second connection terminals 312. Can lose. Also, although the second connection terminal 312 is formed on all sidewalls of the chip 100 in the drawing, the second connection terminal 312 may be formed only on some sidewalls of the chip 100.

FIG. 11 is a cross-sectional view illustrating a structure in which a new chip 100 is stacked in a direction perpendicular to the circuit board 300 in the package of FIG. 10B. As shown, an upper pad 130 is further formed on the chip 100 of FIG. 10B on the upper surface of the chip 100 directly placed on the circuit board 300. The new pad 100 is stacked on the upper pad 130 by being connected by the third connection terminal 314 such as solder balls. The new chip 100 may be the chip 100 of the present invention, or in some cases, may be a different chip from the chip 100.

In the new chip 100, a chip pad 322 is formed to be connected to the third connection terminal 314. If the new chip 100 is the same as the chip 100 of the present invention, the chip pad 322 may be the top pad 130 described above.

FIG. 12A is a plan view illustrating a structure in which a new chip 100 is connected to a circuit board 300 in a horizontal direction in the package of FIG. 10B, and FIG. 12B is a cross-sectional view taken along line C-C of FIG. 12A. This example is for modularizing the plurality of chips 100 using the first side pad 120 of the package of FIG. 10B.

12A and 12B, when the plurality of chips 100 are connected by the second connection terminal 312 in the horizontal direction, the size of the package may be reduced as compared with the arrangement of the chips 100 independently. . That is, in an independently arranged package, a second connection terminal 312 for connecting to an external circuit such as the circuit board 300 is required for each chip 100. However, the illustrated package of the present invention uses the second connection terminal 312 for connecting the two chips 100 in common to the two chips 100, thereby reducing the size of the package.

On the other hand, the packages arranged independently requires a circuit (not shown) for connecting to an external circuit inside each chip 100. However, the package of the present invention can share the circuit, there is an advantage that the size of the chip 100 can be reduced. In the drawings, the same chip 100 is horizontally connected, but in some cases, chips including different electrical structures may be connected to each other.

The package of the present invention can be expanded two-dimensionally as shown in FIG. 13 by using the first side pad 120 by applying the concept described above. The two-dimensionally extended package can further reduce the size of the package and chip. Even in this case, chips including different electrical structures may be connected.

14 and 15 are cross-sectional views illustrating modified examples of the second connection terminal of FIG. 10A.

Specifically, as shown in FIG. 14, the second connection terminal may be formed as a connection terminal 316 having a quadrangular cross section, and may be formed as a connection terminal 318 having a triangular cross section as shown in FIG. 15. The connecting terminals 316 and 318 in the form of square and triangle cross-sections are provided by way of example only, and other types of connecting terminals may be implemented as necessary.

 By using the connection terminals 316 and 318 having a quadrangular and triangular cross-sectional shape, a sufficient contact area between the first substrate pad 320 and the first side pad 120 can be secured. Therefore, the adhesive force between the circuit board 300 and the chip 100 by the square and triangular connection terminals 316 and 318 may be more firm than the ball type connection terminals. Here, the connection terminal 318 having a triangular cross-sectional shape may be formed by sufficiently reflowing the connection terminal 316 having a rectangular cross-sectional shape manufactured by a conventional method.

In the above modifications, the connection terminals of the rectangular and triangular cross-sectional shape is taken as an example, but in some cases, all or part of the cross-sectional shape may form a curved surface. In particular, the triangular connection terminal may be partially curved.

16A is a plan view illustrating another embodiment of a structure of a package using a chip of the present invention, and FIG. 16B is a cross-sectional view taken along the line D-D of FIG. 16A. In this case, the circuit board 300, the first connection terminal 310, the second connection terminal 312, the first substrate pad 320, and the chip 100 are the same as those described with reference to FIG. 10B. That is, the above description may be applied as it is except for the connection portion by the bonding wire 330. Accordingly, the second connection terminal 312 may use various forms as shown in FIGS. 14 and 15.

Referring to FIGS. 16A and 16B, a package includes a circuit board 300 including an electric circuit and a chip 100 of the present invention placed directly on the circuit board 300. The circuit board 300 and the chip 100 are connected to each other by using the first side pad 120 and the first substrate pad 320 by the second connection terminal 312. The number of second connection terminals 312 may vary depending on the type of package. For example, a package requiring fewer input / output pads may have a smaller number of second connection terminals 312, and a package requiring a large number of input / output pads may have a larger number of second connection terminals 312. Can lose. Also, although the second connection terminal 312 is formed on all sidewalls of the chip 100 in the drawing, the second connection terminal 312 may be formed only on some sidewalls of the chip 100.

The upper pad 130 formed on the upper surface of the chip 100 and the second substrate pad 332 formed on the circuit board 300 are connected by the bonding wires 330. The bonding wire 330 may be attached to the pads 130 and 332 using a conventional wire bonding method or a tape to which the bonding wire 330 is attached.

The number of bonding wires 330 may vary depending on the type of package. For example, a package requiring a small number of input / output pads may have a smaller number of bonding wires 330, and a package requiring a large number of input / output pads may have a larger number of bonding wires 330. In addition, although the bonding wires 330 are all formed at the corners of the upper surface of the chip 100 in the drawing, the bonding wires 330 may be formed only at some corners of the upper surface of the chip 100.

Although not shown, the package having the bonding wire 330 may have a structure stacked in a direction perpendicular to the circuit board 300 as shown in FIG. 11. At this time, the upper pad 130 is connected by a third connecting terminal (314 in FIG. 11) such as solder balls, and a new chip (100 in FIG. 11) is stacked. The new chip 100 may be the chip 100 of the present invention, or in some cases, may be a different chip from the chip 100.

The side pads and the top pad can be used in combination with each other. That is, the number of side pads and top pads can be adjusted according to the type of package. For example, a package requiring fewer input / output pads may have fewer side pads and a top pad, and a package requiring more input / output pads may have a larger number of side pads and a top pad. have.

The combination of the side pads and the top pad can be presented in various ways. Here are some ways that can be practically applied to a package: In the first method, as shown in FIG. 16A, the first side pads 120 are formed on all sidewalls of the chip 100, and the top pads 130 are formed on all edges of the top surface of the chip 100, thereby forming a circuit with the chip 100. The substrate 300 is electrically connected. In the second method, the first side pads 120 are formed on all sidewalls of the chip 100, and the top pads 130 are formed only at some edges of the top surface of the chip 100 to form the chip 100 and the circuit board 300. Is electrically connected. This will be described with reference to FIGS. 17A to 19.

In the third method, the first side pad 120 is formed on some sidewalls of the chip 100, and the top pad 130 is formed at all corners of the top surface of the chip 100 to form the chip 100 and the circuit board 300. Is electrically connected. Although this will not be described separately, it will be conceptually sufficiently accessible in the description of other methods below. In a fourth method, the first side pads 120 are formed on some sidewalls of the chip 100, and the top pads 130 are formed only at some edges of the top surface of the chip 100, thereby forming the chip 100 and the circuit board 300. Is electrically connected. This will be described with reference to FIG. 20.

 17A is a plan view illustrating a method of packaging by combining the side pad 120 and the top pad 130 of the present invention. FIG. 17B is a cross-sectional view taken along the line E-E of FIG. 17A.

17A and 17B are examples of applying the second method. That is, the first side pads 120 are formed on all sidewalls of the chip 100, and the top pads 130 are formed at only one corner of the top surface of the chip 100 to form the chip 100 and the circuit board 300. Is electrically connected. The first side pad 120 and the first substrate pad 320 are connected by the second connection terminal 312, and the top pad 130 and the second substrate pad 332 are connected by the bonding wire 330. do.

FIG. 18 is a plan view illustrating an example in which the first side pads 120 are formed on all sidewalls of the chip 100, and the top pads 130 are formed at two corners of the top surface of the chip 100. 19 is a plan view illustrating an example in which the first side pads 120 are formed on all sidewalls of the chip 100, and the top pads 130 are formed at three corners of the top surface of the chip 100.

By combining the first side pads 120 and the top pads 130 as in the first and second methods, the number of the first side pads 120 and the top pads 130 connected to the circuit board 300 is appropriately adjusted. It can be used to distribute. In particular, when the top pad 130 is electrically connected to all or some corners of the top surface while the first side pad 120 is formed on all sidewalls, the size of the chip 100 and the package may be reduced. Furthermore, the pads may be appropriately disposed according to the shape of the chip 100 or the package by not forming the bonding wires 330 at some corners of the upper surface.

In addition, according to the second method of the present invention, as described with reference to FIGS. 12A to 13, the chip 100 may be connected to the edge portion where the bonding wire 330 is not formed. When the plurality of chips 100 are connected by the second connection terminal 312, the size of the package may be reduced compared to that of the chips 100 independently. In addition, the package of the present invention may be extended two-dimensionally as shown in FIG. 13 by using the first side pad 120 by applying the concept described above. Expanding in two dimensions can further reduce the size of packages and chips.

20 is an example of applying the above fourth method. That is, the first side pad 120 is formed on some sidewalls of the chip 100, and the top pad 130 is formed on a part of the top surface of the chip 100, for example, one corner, to form the chip 100 and the circuit board. The 300 is electrically connected. The first side pad 120 and the first substrate pad 320 are connected by the second connection terminal 312, and the top pad 130 and the second substrate pad 332 are connected by the bonding wire 330. do.

As shown in FIG. 20, when the first side pad 120 and the top pad 130 are disposed, the size of the chip 100 and the package may be reduced. That is, since the first side pad 120 is not formed on some sidewalls, a circuit for connecting to an external circuit may not be disposed in the chip 100.

21A is a plan view illustrating another embodiment of a package structure using a chip of the present invention, and FIG. 21B is a cross-sectional view taken along the line F-F of FIG. 21A.

Referring to FIGS. 21A and 21B, a circuit board 300 including an electrical circuit and a chip 100 such as a semiconductor chip are included. The chip 100 is attached to the circuit board 300 via the third connection terminal 314, and the sidewall includes a first side pad 120 formed of a plurality of conductive patterns separated from each other in the vertical direction of the sidewall. do. That is, except for the shape of the package, the chip used in the package described herein uses side pads with separated conductive patterns.

The first side pad 120 is connected to the first substrate pad 320 on the circuit board 300 by a connection terminal 316 having a rectangular cross section. In addition, the third substrate pad 340 and the top pad 130 on the circuit board 300 below the chip 100 are connected by the third connection terminal 314. In the drawing, although the connection terminal 316 having a rectangular cross-sectional shape is presented, various types of connection terminals may be applied within the scope of the present invention.

As mentioned above, although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible. For example, the conductive pattern constituting the side pads may be formed at the same time as the metal wirings, circuit wirings, and vias inside the chip, but may also be formed simultaneously with forming a redistribution line for forming a bonding pad such as a top pad. .

The chip having the side pad according to the present invention described above has a side pad by a conductive pattern separated on the sidewall, so that the pad capable of electrical signal processing can be appropriately disposed in response to the size of the chip being reduced. Can be. Furthermore, the side pads are formed at the same time as the process of forming the electrical structure inside the chip, so that no separate photo etching process is required.

In addition, the package using the chip is placed directly on the circuit board, it is possible to greatly reduce the thickness of the single-layer or laminated package. In addition, the size of the package can be reduced by horizontally connecting the chips using the side pads.

Furthermore, by using a combination of the side pad and the top pad, the number of pads can be adjusted in various ways according to the type of the package, thereby reducing the size of the package.

Claims (71)

A chip having a side pad exposed to the side wall, the side pad including a side pad made of a plurality of conductive patterns separated from each other in the vertical direction of the side wall. The chip of claim 1, wherein the sidewall includes one or more side pads. The chip of claim 1, wherein the side pad is a first side pad having an insulating layer disposed between the conductive patterns. The chip of claim 1, wherein the side pad is a second side pad having a conductive buried pattern embedded between the conductive patterns. The chip of claim 1, wherein the number of the conductive patterns is determined by a shape of the side pad. The chip of claim 1, wherein a shape of the conductive pattern is determined by a shape of the side pad. The chip of claim 1, wherein a shape of the conductive pattern is determined by a process of forming an electrical structure inside the chip. The chip of claim 1, wherein the conductive pattern comprises at least one layer selected from conductive metal nitride layers such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride. The chip of claim 4, wherein the conductive pattern and the buried pattern are positioned on side surfaces of a layer for forming an electrical structure inside the chip. The chip of claim 9, wherein the electrical structure is a metal wiring. 10. The chip of claim 9, wherein the electrical structure is circuit wiring. The chip of claim 4, wherein the electrical structure is positioned at a side of a layer formed on a side of a layer in which a via is formed in the chip. The chip of claim 3, wherein a position of the first side pad is varied depending on a thickness of the insulating layer. The chip of claim 3, wherein a position of the first side pad is changed depending on a thickness of the conductive pattern. The chip of claim 3, wherein a position of the first side pad is determined according to a type of package. The chip of claim 4, wherein a position of the second side pad is varied depending on a thickness of the conductive pattern and the buried pattern. The chip of claim 4, wherein a position of the second side pad is determined according to a type of package. The chip of claim 4, wherein the second side pad comprises a buried pattern formed between the conductive patterns. The chip of claim 4, wherein the second side pad has a buried pattern formed in a portion between the conductive patterns. The chip of claim 1, further comprising a conductive top pad on a top surface of the chip defined by the sidewalls. The chip as claimed in claim 20, wherein the top pad comprises at least one layer selected from conductive metal nitride films such as aluminum, copper, tungsten, molybdenum and titanium nitride, tantalum nitride, or tungsten nitride. The chip of claim 20, wherein the number of the top pads is determined according to a type of package. The chip of claim 20, wherein the conductive pattern is a redistribution pattern electrically connected to the top pad. Forming an electrical structure on the substrate on which the scribe line is defined; Forming a plurality of pad conductive patterns on the substrate, the plurality of pads being vertically separated from the scribe line; Covering the substrate on which the pad conductive pattern is formed with a protective insulating film; And And removing the protective insulating layer and the pad conductive pattern by the width of the scribe line to form a conductive pattern. 25. The method of claim 24, wherein the pad conductive pattern is formed at the same time as the electrical structure. The method of claim 24, wherein the forming of the pad conductive pattern includes: Forming a first interlayer insulating film on the substrate; Forming a first pad conductive pattern on the first interlayer insulating film; Forming a second interlayer dielectric layer covering the first pad conductive pattern and the first interlayer dielectric layer; And forming a conductive pattern for a second pad on the second interlayer insulating film. 27. The method of claim 26, wherein the step of forming the conductive pattern for the first pad and the conductive pattern for the second pad, And forming a buried conductive pattern between the first pad conductive pattern and the second pad conductive pattern. 27. The method of claim 26, wherein the first pad conductive pattern is formed on a side surface of a layer forming a metal wiring, which is one of the electrical structures. 27. The method of claim 26, wherein the second pad conductive pattern is formed on a side surface of a layer forming a circuit pattern which is one of the electrical structures. The method of claim 27, wherein the buried conductive pattern is formed on a side surface of a layer forming a via which is one of the electrical structures. 28. The method of claim 27, wherein the buried conductive pattern is formed between all of the pad conductive patterns. 28. The method of claim 27, wherein the buried conductive pattern is formed between a portion of the pad conductive pattern. 25. The method of claim 24, further comprising forming a top pad on the protective insulating film. A circuit board including an electric circuit; A chip disposed directly on the circuit board, the chip including a side pad formed of a plurality of conductive patterns separated from each other in a vertical direction of the side wall while being exposed to the side wall; And A package using a chip having a side pad including a second connection terminal for electrically connecting the circuit board and the side pad. 35. The method of claim 34, wherein one surface of the circuit board is attached with a first connection terminal for electrical connection to the outside of the package, and the other surface includes a first substrate pad for placing the second connection terminal Package using a chip having a side pad. 35. The package of claim 34, wherein the side pad is a first side pad having an insulating layer disposed between the conductive patterns. 35. The package of claim 34, wherein the side pads are second side pads with conductive buried patterns embedded between the conductive patterns. The package using a chip with side pads according to claim 37, wherein the second side pads have buried patterns formed on all of the conductive patterns. 38. The package of claim 37, wherein the second side pad has a buried pattern formed in a portion between the conductive patterns. 35. The package of claim 34, wherein the chip is placed on the circuit board without physical or chemical bonding. 35. The package of claim 34, further comprising an adhesive layer for adhesion between the chip and the circuit board. 35. The package of claim 34, wherein the second connection terminal is any one or a plurality of solder balls, rectangular cross-sectional shapes, and triangular cross-sectional shapes. 35. The package of claim 34, wherein the number of the second connection terminals is determined by the number of electrical input and output pads required by the chip. 35. The package of claim 34, further comprising an upper pad on an upper surface of the chip. 45. The package of claim 44, further comprising one or more chips stacked vertically with respect to the circuit board by third connection terminals connected to the top pad. . 45. The package of claim 44, wherein the top pad is connected to a second substrate pad formed on the circuit board by a bonding wire. 47. The package of claim 46, wherein the number of bonding wires is determined by the number of electrical input and output pads required by the chip. 48. The chip of claim 46, further comprising one or a plurality of chips stacked vertically with respect to the circuit board by a third connection terminal connected to the top pad. package. 45. The package of claim 44, wherein the side pad and the top pad can be used in combination. 50. The package of claim 49, wherein the number of side pads and top pads combined is determined by the number of electrical input and output pads required by the chip. 50. The package of claim 49, wherein the side pads are disposed on all sidewalls of the chip, and the top pads are disposed on all edges of the top surface of the chip. 50. The package of claim 49, wherein the side pads are disposed on all sidewalls of the chip, and the top pads are disposed at some edges of the top surface of the chip. 50. The package of claim 49, wherein the side pads are disposed on some sidewalls of the chip, and the top pads are disposed at all corners of the top surface of the chip. 50. The package of claim 49, wherein the side pads are disposed on some side surfaces of the chip, and the top pads are disposed at some corners of the top surface of the chip. A first chip including a first side pad formed on a plurality of conductive patterns exposed to sidewalls and separated from each other in a vertical direction of the sidewalls; A second chip disposed independently of the first chip and including a second side pad including a plurality of conductive patterns exposed on sidewalls and separated from each other in a vertical direction of the sidewalls; And A package using a chip having a side pad including a second connection terminal for electrically connecting the first side pad and the second side pad. 56. The package of claim 55, wherein at least one of the first side pad and the second side pad includes an insulating film disposed between the conductive patterns. 56. The package of claim 55, wherein at least one of the first side pad and the second side pad includes a conductive buried pattern embedded between the conductive patterns. 58. The package using a chip with side pad according to claim 57, wherein the conductive buried pattern is buried in all between the conductive patterns. 58. The package of claim 57, wherein the conductive buried pattern has a buried pattern formed in a portion between the conductive patterns. 58. The package of claim 57, wherein the second connection terminal is any one selected from solder ball shape and rectangular cross-sectional shape or a combination thereof. 56. The package of claim 55, wherein the first and second chips are extended in two dimensions by the second connection terminal. 56. The package of claim 55, wherein at least one of the first chip or the second chip further comprises a top pad formed on the top surface to contact the bonding wires. 63. The chip according to claim 62, further comprising one or more chips stacked vertically with respect to the circuit board by third connection terminals connected to the top pad. package. A circuit board including an electrical circuit; And A chip attached to the circuit board via an electrical connection terminal, the chip including a side pad formed of a plurality of conductive patterns separated from each other in a vertical direction of the side wall while being exposed to the side wall; And A package using a chip having a side pad including a second connection terminal for electrically connecting the circuit board and the side pad. 65. The package using a chip of claim 64, wherein the side pad is a first side pad having an insulating layer disposed between the conductive patterns. 65. The package of claim 64, wherein the side pad is a second side pad having a conductive buried pattern embedded between the conductive patterns. 67. The package of claim 66, wherein the second side pad has a buried pattern formed between all of the conductive patterns. 67. The package of claim 66, wherein the second side pad has a buried pattern formed in a portion between the conductive patterns. 65. The package of claim 64, wherein the second connection terminal is any one or a plurality of solder ball, rectangular cross-sectional, and triangular cross-sectional shapes. 65. The package of claim 64, further comprising a conductive top pad on a top surface of the chip defined by the sidewalls. 71. The package of claim 70, further comprising one or more chips stacked vertically with respect to the circuit board by a third connection terminal connected to the top pad. .

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