CN111243551B - Multiplexing display panel, circuit driving correction method and adjusting method - Google Patents

Multiplexing display panel, circuit driving correction method and adjusting method Download PDF

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Publication number
CN111243551B
CN111243551B CN202010336331.8A CN202010336331A CN111243551B CN 111243551 B CN111243551 B CN 111243551B CN 202010336331 A CN202010336331 A CN 202010336331A CN 111243551 B CN111243551 B CN 111243551B
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data
gray scale
scale voltage
time
lookup table
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CN111243551A (en
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徐阳
李�杰
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Nanjing CEC Panda LCD Technology Co Ltd
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Nanjing East China Electronic Information Technology Co ltd
Nanjing CEC Panda LCD Technology Co Ltd
Nanjing CEC Panda FPD Technology Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0271Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention relates to a multiplex display panel and a circuit driving correction method and an adjusting method, wherein the multiplex display panel comprises a feedback line, one end of the feedback line is connected with a leftmost or rightmost data line, and the other end of the feedback line is connected with a device for measuring a voltage waveform diagram of the feedback line; the time sequence controller is internally provided with a buffer and a lookup table embedded in the time sequence controller, the lookup table comprises a first group of lookup table and a second group of lookup table, and the gray scale voltage data of the first group of lookup table and the gray scale voltage data of the second group of lookup table are obtained by comparing and adjusting the voltage of the data line actually measured by the feedback line with the target voltage of the data line. According to the invention, the voltage waveform diagram of the gray scales is measured through the feedback line, and the first group of lookup tables and the second lookup table are determined according to the comparison between the voltage value measured by each gray scale and the target voltage value, so that a very good charging effect is achieved, and the display quality is improved.

Description

Multiplexing display panel, circuit driving correction method and adjusting method
Technical Field
The invention belongs to the technical field of liquid crystal display panels, and particularly relates to a multiplexing display panel, a circuit driving correction method and an adjusting method.
Technical Field
As the TFT-LCD has a narrower frame, the chip IC has a smaller size and the number of pins thereof is reduced, and for the reason, the chip IC having the MUX (Multiplexer) technology is used. The MUX technology is a technology that uses one output terminal SoutT of the MUX circuit to drive a plurality of data lines S in the panel, which are now commonly used as 1:2 and 1:3, that is, the output terminal SoutT drives 2 or 3 data lines in the panel. As shown in fig. 1, the panel is provided with criss-cross gate lines G1, G2, …, Gn and data lines S1, S2, …, Sm, pixel cells located at intersections of the gate lines and the data lines, a source driver having output terminals SoutT (Sout 1, Sout2, …, SoutT), and a MUX circuit connected to the source driver, wherein the MUX circuit adopts a 2:4 (i.e., 1: 2) manner, i.e., two MUX circuits correspond to 4 data lines, wherein the MUX circuit has input first switch signals SW1 and second switch signals SW2, and further includes a plurality of driving switches T selectively connected to the first switch signals SW1 and the second switch signals SW2, and connected to the corresponding data lines through the driving switches T.
When the panel load is large, the waveform distortion of the data line S connected to the MUX circuit is more likely to occur, as shown in fig. 2, the first data line S1 connected to the first output terminal Sout1 is distorted, and the difference in charging further causes the difference in image reality.
The data of the first output terminal Sout1 in one frame time are D1, D2, D3, D4, … … and D2m, the first output terminal Sout1 is connected to the first data line S1 through the driving switch T controlled by the first switching signal SW1, and the first output terminal Sout1 is connected to the third data line S3 through the driving switch T controlled by the second switching signal SW 2. Since the first switch signal SW1 and the second switch signal SW2 are alternately turned on in sequence, data of the first data line S1 is D1, D3, D5, … …, D2m-1 in one frame time, and data of the third data line S3 is D1, D3, D5, … …, D2m-1 in one frame time.
Compared with a common driving mode, the load of the driving switch T of the MUX circuit is large, waveform climbing on a data line on a panel is slow, and stable waveforms on the data line cannot reach a set voltage value all the time due to the large voltage division influence of the load of the MUX circuit.
The conventional over-voltage compensation method is to compensate for frame-switched data, and is not suitable for a display panel having a MUX circuit.
Disclosure of Invention
The invention aims to provide a multiplexing display panel, a circuit driving correction method and a circuit driving adjustment method, which improve data distortion and achieve good charging effect.
The invention provides a multiplexing display panel, which comprises a grid line, a data line, a pixel unit, a source driver, a time schedule controller and a multiplexing circuit, wherein the grid line and the data line are arranged in a criss-cross manner, the pixel unit is positioned at the intersection of the grid line and the data line, the time schedule controller is connected with the source driver, the multiplexing circuit is connected with the source driver and the data line, the multiplexing display panel also comprises a feedback line, one end of the feedback line is connected with the far end of the leftmost side or the rightmost side of the data line, and the other end of the feedback line is connected with a; the time sequence controller is internally provided with a buffer and a lookup table embedded in the time sequence controller, the lookup table comprises a first set of lookup table and a second set of lookup table, the first set of lookup table is used for correcting ascending and descending distortion data, the second set of lookup table is used for correcting error values, and gray scale voltage data of the first set of lookup table and gray scale voltage data of the second set of lookup table are obtained by comparing and adjusting voltage of a data line actually measured by the feedback line and target voltage of the data line.
Preferably, the multiplexing circuit has a first switching signal and a second switching signal inputted thereto, and the multiplexing circuit includes a driving switch connected to the corresponding data line; the source driver has a plurality of output terminals, wherein the number of the driving switches is 2 times the number of the output terminals.
Preferably, the gates of the odd driving switches are connected with the first switching signal, and the gates of the even driving switches are connected with the second switching signal; the source electrode of the driving switch is connected with the corresponding data line.
Preferably, when the same output end is adopted, the gray scale voltage data corresponding to one switch signal is adopted in the longitudinal direction of the first group of lookup tables, and the gray scale voltage data corresponding to the next adjacent switch signal is adopted in the abscissa; the first lookup table is used in the current time; the second group of lookup tables are used within the driving time, and the vertical direction of the second group of lookup tables corresponds to gray scale voltage data on the data line, the horizontal coordinate of the second group of lookup tables corresponds to gray scale voltage data to be displayed on the data line.
Preferably, the current time and the driving time together constitute an on time of the driving switch of the multiplexing circuit, the current time is a charging time of a previous stage of the driving switch of the multiplexing circuit, and the driving time is a charging time of a subsequent stage of the driving switch of the multiplexing circuit.
Preferably, the multiplexing circuit has three switching signals inputted thereto, and the multiplexing circuit includes driving switches connected to the corresponding data lines; the source driver has a plurality of output terminals, wherein the number of the driving switches is 3 times the number of the output terminals.
The invention also provides a circuit driving correction method of the multiplexing display panel, which comprises the following steps:
s1: comparing the gray scale voltage data of the pixel to be displayed with the gray scale voltage data of the output end corresponding to the source driver in the pixel in the buffer at a switching time;
s2: using a first set of lookup tables to correct at the current time;
s3: correcting the error value by using a second lookup table for correcting the error value during the driving time;
s4: inputting the corrected gray scale voltage to a corresponding data line through a source driver;
wherein the switching time is a duration of a high level of the switching signal input to the multiplexing circuit.
Preferably, step S1 includes the steps of:
s11: inputting the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel into a buffer of the time schedule controller, and temporarily storing the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel by the buffer;
s12: inputting the gray scale voltage data of the current pixel and the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel into a lookup table;
s13: the gray scale voltage data to be displayed and the gray scale voltage data of the output end corresponding to the source driver in the pixel at the switching time of the pixel in the buffer are compared and analyzed.
Preferably, in step S4, the source driver outputs the corrected gray-scale voltage to the data line of the current pixel via the multiplexing circuit.
The invention also provides a method for adjusting the multiplexing display panel, which comprises the following steps:
obtaining a gray scale voltage waveform diagram of an output end of a source driver and a feedback line;
adjusting the compensation voltage data of the first group of lookup tables to reduce the rise and fall time of the gray scale voltage at the current time until the proper gray scale voltage is reached at the end of the current time and the feedback line reaches the target voltage;
and continuously observing the change condition of the data at the output end of the source driver in the driving time, and adjusting the gray scale voltage data of the second group of lookup tables.
According to the invention, the voltage waveform diagram of the gray scales is measured through the remote feedback line, the first group of lookup tables and the second lookup tables are determined according to the comparison between the voltage value measured by each gray scale and the target voltage value, and the subsequent display data enables the distortion of the panel to be compensated according to the first group of lookup tables and the second group of lookup tables of the time schedule controller, so that a very good charging effect is achieved, and the display quality is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art multiplexing display panel;
FIG. 2 is a diagram illustrating waveform distortion of the multiplexing circuit shown in FIG. 1 input to data lines;
FIG. 3 is a schematic structural diagram of a multiplexing display panel according to the present invention;
FIG. 4 is a graph of the charging waveform on the data line actually measured by the feedback line for the panel of FIG. 3;
FIG. 5 is a graph of a charging waveform compensated for the distortion data shown in FIG. 3;
FIG. 6 is a method of correcting the distortion data shown in FIG. 3;
FIG. 7 is a diagram illustrating a first set of lookup tables of a timing controller according to the present invention;
FIG. 8 is a diagram illustrating a second set of lookup tables of the timing controller according to the present invention;
FIG. 9 is a waveform diagram of the present invention after being corrected.
Detailed Description
Fig. 3 is a schematic structural diagram of a multiplexing display panel according to the present invention, in which gate lines G1, G2, …, Gn and data lines S1, S2, …, Sm are arranged in the panel, pixel units are located at intersections of the gate lines and the data lines, a source driver (S _ Drive) 10, a timing controller (Tcon) 20 connected to the source driver 10, and a MUX circuit (i.e., a multiplexing circuit) 30 connected to the source driver 10 and the data lines, wherein the MUX circuit outputs signals to the data lines in a 1:2 or 1:3 manner, and in this embodiment, the MUX circuit is in a 2:4 (i.e., 1: 2) manner, i.e., two MUX circuits correspond to 4 data lines.
Wherein the MUX circuit 30 has a first switch signal SW1 and a second switch signal SW2 as inputs, and the MUX circuit 30 includes a driving switch 31 connected to the data line. The source driver 10 has a plurality of output terminals SoutT, wherein the number of the output terminals is half of the number of the driving switches 31, the number of the driving switches 31 is the same as the number of the data lines, and T is equal to m/2.
The gates of the odd driving switches 31 are connected to the first switch signal SW1, and the gates of the even driving switches 31 are connected to the second switch signal SW 2; the source of the driving switch 31 is connected to the data line;
the xth and (x + 2) th driving switches 31 are in one group, and the drains of the driving switches 31 in each group are all connected to the same output terminal.
In other embodiments, the MUX circuit samples 1:3, i.e. three drive switches 31 are connected to the same output, and the MUX circuit has 3 switch signals input.
The number of driving switches 31 is 2 times or 3 times the number of output terminals.
The multiplexing display panel further includes a feedback line (FB) 40, one end of the feedback line 40 being connected to a distal end of the leftmost or rightmost data line, and the other end thereof being connected to a device for measuring a voltage waveform pattern of the feedback line 40, the voltage waveform pattern of the feedback line 40 being tested by the device to obtain a voltage waveform pattern of the distal end of the leftmost or rightmost data line.
The far end of the data line means: the data line is located at the end farthest from the MUX circuit.
Fig. 4 is a schematic waveform diagram illustrating a first output terminal Sout1 of the source driver 10 and a schematic waveform diagram illustrating a signal output to a data line after passing through a MUX circuit (i.e., before compensation), and fig. 5 is a schematic waveform diagram illustrating a signal output to a data line after compensation by a first output terminal Sout1 and a second output terminal Sout2 of the source driver 10.
As shown in fig. 4, the first output terminal Sout1 of the source driver 10 is shown as a black line, and the charging waveform on the data line actually measured by the feedback line 40 is shown as a dotted line, and it can be seen that there is a large amplitude attenuation of the voltage after passing through the MUX circuit.
As shown in fig. 5, by increasing the voltages of the two row lines above the first output terminal Sout1 of the source driver 10 before inputting to the MUX circuit, the charging waveform actually obtained by the data lines is the FB dotted line, and it can be seen that the voltages achieve the desired effect after passing through the MUX circuit.
The first output terminal SOUT1 and the first data line S1 are connected to the driving switch 31 by a first switch signal SW1, and the first output terminal SOUT1 and the third data line S3 are connected to the driving switch 31 by a second switch signal SW 2.
The time sequence controller 20 is internally provided with a buffer 21 and a lookup table 22 embedded in the time sequence controller 20, the gray scale voltage data of the lookup table 22 is obtained by comparing and adjusting the voltage of the data line actually measured by the feedback line 40 with the target voltage of the data line, that is, comparing the voltage waveform of the feedback line 40 under each gray scale with the target voltage by initial measurement, and adjusting the gray scale display data of the lookup table 22 in the time sequence controller, so that the measured voltage of the feedback line 40 is consistent with the target voltage, thereby achieving the purpose of measurement and correction.
In this embodiment, two sets of lookup tables are embedded in the timing controller 20, which are a first set of lookup table and a second set of lookup table, respectively, where the first set of lookup table is used to correct distortion data of rise and fall (i.e. gray scale voltage in the rise phase and the fall phase) (for accelerating rise and fall time and reaching the vicinity of the target voltage as soon as possible, as shown in fig. 7), and the second set of lookup table is used to correct error value (i.e. attenuation meaning for solving the problem that the MUX circuit causes excessive resistance and capacitance to cause voltage division, which results in that the target voltage cannot be accurately reached, as shown in fig. 8).
The gray scale voltage data of the first set of lookup tables and the gray scale voltage data of the second set of lookup tables are obtained by comparing and adjusting the voltage of the data line actually measured by the feedback line 40 with the target voltage of the data line.
For the first set of lookup tables for correcting the rising and falling, when the same output terminal SoutT is used, the gray scale voltage data corresponding to the second switch signal SW2 is used in the vertical direction shown in fig. 7, the gray scale voltage data corresponding to the first switch signal SW1 is used in the horizontal axis, and the lookup table shown in fig. 7 is used in the current time (Forward).
For the second set of lookup tables for correcting the error value, the vertical direction shown in fig. 8 is corresponding to a gray scale voltage data on the data line, the horizontal axis is corresponding to the gray scale voltage data to be displayed on the data line, and the lookup table shown in fig. 8 is used during the Driving time (Driving).
The second switch signal SW2 for initially controlling the driving switch 31 at the first output terminal SOUT1 inputs a low level, which has data of D0 and is located in row H0, the first switch signal SW1 and the second switch signal SW2 sequentially input a high level to control the driving switch 31 to be turned on, data to be displayed are D1 and D2, the first switch signal SW1 corresponds to data of D1, and the second switch signal SW2 corresponds to data of D2. When the first output terminal SOUT1 is going to send out D1 data, the timing controller 20 compares D1 with the value of D0 in the buffer 21, and the first output terminal SOUT1 sends out the compensation data D1 complement obtained by the first lookup table in the current time, so that the actual voltage of the feedback line 40 reaches the target value D1 after the current time is over, and the first output terminal SOUT1 sends out the compensation data D1 complement' obtained by the second lookup table in the driving time, so that the actual voltage of the feedback line 40 accurately reaches the target value D1 in the driving time. When the first switch signal SW1 is inputted to the low-level off control switch 31, the voltage on the first data line S1 is maintained at the target value D1 due to the shutdown of the MUX circuit. The current time (Forward) and the Driving time (Driving) jointly form the on time of the Driving switch 31 of the MUX circuit, the current time (Forward) is the front charging time of the Driving switch 31 of the MUX circuit, and the Driving time (Driving) is the rear charging time of the Driving switch 31 of the MUX circuit.
The present invention also discloses a method for driving and correcting the multiplexing circuit, as shown in fig. 6, comprising the following steps:
s1: comparing the gray scale voltage data of the pixel to be displayed with the gray scale voltage data of the output end corresponding to the source driver 10 in the last switching time of the pixel in the buffer 21;
s2: using a first set of lookup tables to correct at the current time;
s3: correcting the error value by using a second lookup table for correcting the error value during the driving time;
s4: the corrected gray scale voltage is input to the corresponding data line (the data line corresponding to the pixel to be displayed) through the source driver.
The switching time is the duration of the high level of the switching signal input to the MUX circuit, and the specific switching signal may be the first switching signal SW1 or the second switching signal SW2 of this embodiment, or one of the three switching signals.
Step S1 includes the following steps:
s11: inputting the gray scale voltage data of the output terminal corresponding to the source driver in the last switching time of the pixel into the buffer 21 of the timing controller 20, and temporarily storing the gray scale voltage data of the output terminal corresponding to the source driver in the last switching time of the pixel in the buffer 21;
s12: inputting the gray scale voltage data of the current pixel and the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel into the lookup table 22;
s13: the gray scale voltage data to be displayed and the gray scale voltage data of the output end corresponding to the source driver in the pixel at the switching time of the pixel in the buffer are compared and analyzed.
In step S4, the source driver 10 outputs the corrected gray-scale voltage to the data line of the current pixel through the MUX circuit.
The distorted data at the output terminal of the source driver 10 can be compensated by the above method.
The distortion in the second lookup table means that if the data line actually wants to obtain 8 gray scale voltages and the gray scale voltage of the data line actually measured through the feedback line 40 is 5, which indicates that 3 gray scales are lost in the process of inputting the output end of the source driver 10 to the MUX circuit, the 3 gray scales are compensated in a correction manner, so that 11 gray scale voltages are output to the output end of the source driver 10 in the next row of pixel time.
As shown in fig. 9, the specific method of step S2 includes:
s21: when the gray scale voltage is corrected by using the first group of lookup tables within the current time (Forward) (e.g. within the time t1 at the first two dotted lines shown in fig. 9), the voltage on the corresponding data line reaches the target voltage within a certain time; when the gray-scale voltage is corrected using the second set of lookup tables during the Driving time (Driving) (e.g., during the time t2 at the two subsequent dotted lines shown in fig. 9), the voltage on the corresponding data line is stabilized to the target voltage (e.g., line 002 shown in fig. 9).
The invention compares the voltage waveform of the far-end feedback line under each gray scale with the target voltage by initial measurement, adjusts the gray scale display data of the lookup table in the time schedule controller, and corrects the distortion in the panel; the time sequence driver is divided into two time periods, data processed by the two groups of lookup tables are output to the source electrode driver to be corrected and output, errors of the panel can be corrected, and display quality is improved.
The invention also discloses a method for adjusting the multiplexing display panel, which comprises the following steps:
obtaining a gray scale voltage waveform diagram of the output terminal Sout of the source driver 10 (for example, the first output terminal Sout1, the line 001 shown in fig. 9, the gray scale voltage output from the timing controller 20 to the source driver 10) and the feedback line (FB) 40 (the line 003 shown in fig. 9);
adjusting the compensation voltage data of the first group of lookup tables to reduce the rise and fall time of the gray scale voltage at the current time until the proper gray scale voltage data is reached at the end of the current time and the feedback line reaches the target voltage;
continuously observing the change of the data at the output terminal Sout of the source driver 10 in the Driving time (Driving) (the end of the Driving time is the closing time point of the MUX circuit), adjusting the gray scale voltage data of the error corrected second set of lookup tables so that the target voltage is accurately reached at the end of the Driving time.
The invention measures the voltage waveform diagram of the gray scale through the far-end feedback line (the feedback line is positioned at the leftmost side or the rightmost side, namely the far-end meaning), determines the first group of lookup tables and the second lookup tables according to the comparison of the voltage value under each gray scale measurement and the target voltage value, and compensates the panel distortion according to the first group of lookup tables and the second group of lookup tables of the time schedule controller by the subsequent display data, thereby achieving better charging effect under the condition of the MUX circuit switching and improving the display quality.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the embodiments, and various equivalent modifications can be made within the technical spirit of the present invention, and the technical solutions of the present invention are within the scope of the present invention.

Claims (6)

1. A multiplexing display panel, it includes being equipped with criss-cross gate line and data link, locate at gate line and pixel unit of the intersection of data link, source driver, timing controller that is connected with source driver and multiplex circuit to connect source driver and data link, characterized by that, also include the feedback line, one end of the said feedback line is connected with far-end of the leftmost or rightmost data link, its another end is connected with the apparatus which measures the voltage waveform pattern of the said feedback line; the time sequence controller is internally provided with a buffer and a lookup table embedded in the time sequence controller, the lookup table comprises a first set of lookup table and a second set of lookup table, the first set of lookup table is used for correcting ascending and descending distortion data, the second set of lookup table is used for correcting error values, and gray scale voltage data of the first set of lookup table and gray scale voltage data of the second set of lookup table are obtained by comparing and adjusting voltage of a data line actually measured by the feedback line with target voltage of the data line; the multiplexing circuit is provided with a first switching signal and a second switching signal which are input, and comprises driving switches connected with corresponding data lines; the source electrode driver is provided with a plurality of output ends, wherein the number of the driving switches is 2 times of the number of the output ends; when the same output end is adopted, the gray scale voltage data corresponding to one switching signal is adopted in the longitudinal direction of the first group of lookup tables, and the gray scale voltage data corresponding to the next adjacent switching signal is adopted in the abscissa; the first lookup table is used in the current time; the longitudinal direction of the second group of lookup tables is corresponding to gray scale voltage data on the data line, the abscissa is corresponding to gray scale voltage data to be displayed on the data line, and the second lookup tables are used within the driving time; the current time and the driving time jointly form the opening time of the driving switch of the multiplexing circuit, the current time is the front charging time of the driving switch of the multiplexing circuit, and the driving time is the rear charging time of the driving switch of the multiplexing circuit.
2. The multiplexed display panel of claim 1, wherein: the grid electrode of the odd drive switch is in signal connection with the first switch, and the grid electrode of the even drive switch is in signal connection with the second switch; the source electrode of the driving switch is connected with the corresponding data line.
3. A circuit driving correction method for a multiplexed display panel according to claim 1 or 2, comprising the steps of:
s1: comparing the gray scale voltage data of the pixel to be displayed with the gray scale voltage data of the output end corresponding to the source driver in the pixel in the buffer at a switching time;
s2: using a first set of lookup tables to correct at the current time;
s3: correcting the error value by using a second lookup table for correcting the error value during the driving time;
s4: inputting the corrected gray scale voltage to a corresponding data line through a source driver;
wherein the switching time is a duration of a high level of the switching signal input to the multiplexing circuit.
4. The method for correcting circuit driving of a multi-channel display panel according to claim 3, wherein the step S1 comprises the steps of:
s11: inputting the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel into a buffer of the time schedule controller, and temporarily storing the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel by the buffer;
s12: inputting the gray scale voltage data of the current pixel and the gray scale voltage data of the output end corresponding to the source driver in the last switching time of the pixel into a lookup table;
s13: the gray scale voltage data to be displayed and the gray scale voltage data of the output end corresponding to the source driver in the pixel at the switching time of the pixel in the buffer are compared and analyzed.
5. The method as claimed in claim 3, wherein in step S4, the source driver outputs the corrected gray-scale voltage to the data line of the current pixel via the multiplexing circuit.
6. A method of adjusting a multiplexed display panel, for use in the multiplexed display panel of claim 1 or 2, comprising the steps of:
obtaining a gray scale voltage waveform diagram of an output end of a source driver and a feedback line;
adjusting the compensation voltage data of the first group of lookup tables to reduce the rise and fall time of the gray scale voltage at the current time until the proper gray scale voltage is reached at the end of the current time and the feedback line reaches the target voltage;
and continuously observing the change condition of the data at the output end of the source driver in the driving time, and adjusting the gray scale voltage data of the second group of lookup tables.
CN202010336331.8A 2020-04-26 2020-04-26 Multiplexing display panel, circuit driving correction method and adjusting method Expired - Fee Related CN111243551B (en)

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