CN111223907A - Array substrate, manufacturing method thereof and display device - Google Patents

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display device, relates to the technical field of display, and aims to improve the capacitance value of a storage capacitor in a pixel driving circuit. The capacitor structure in the array substrate comprises: the first polar plate, the dielectric layer and the second polar plate are sequentially stacked along the direction far away from the substrate; the shading patterns are multiplexed into first polar plates in the corresponding pixel driving circuits, and the buffer layers are multiplexed into dielectric layers; the array substrate further includes: the step difference compensation patterns are arranged on the periphery of each shading pattern, and in the direction perpendicular to the substrate, the difference value between the height of the surface of each step difference compensation pattern, which is back to the substrate, and the height of the shading pattern, which is back to the surface of the substrate, is smaller than a first threshold value; the orthographic projection of the buffer layer on the substrate is respectively overlapped with the orthographic projection of the shading pattern on the substrate and the orthographic projection of the step difference compensation pattern on the substrate, and the thickness of the buffer layer is smaller than a second threshold value in the direction perpendicular to the substrate. The array substrate provided by the invention is used for driving the light-emitting unit to display.

Description

Array substrate, manufacturing method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.

Background

Organic Light-Emitting Diode (OLED) display panels are increasingly used in various fields due to their advantages of high brightness, low power consumption, fast response, high definition, good flexibility, high Light-Emitting efficiency, and the like.

In the OLED display panel, the light emitting element is generally driven by the pixel driving circuit to emit light, and along with the improvement of the resolution and the refresh rate of the display panel, the capacitance of the storage capacitor in the pixel driving circuit needs to be continuously increased, so how to increase the capacitance of the storage capacitor in the pixel driving circuit becomes a problem to be solved urgently.

Disclosure of Invention

The invention aims to provide an array substrate, a manufacturing method thereof and a display device, which are used for improving the capacitance value of a storage capacitor in a pixel driving circuit.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides an array substrate, including: the light-shielding layer, the buffer layer and the driving circuit layer are arranged on the substrate;

the light shielding layer comprises a plurality of independent light shielding patterns;

the driving circuit layer comprises a plurality of pixel driving circuits distributed in an array mode, the pixel driving circuits correspond to the shading graphs one by one, each pixel driving circuit comprises a capacitor structure, and the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate are sequentially stacked along the direction far away from the substrate;

the shading patterns are multiplexed into corresponding first polar plates in the pixel driving circuit, and the buffer layer is multiplexed into the dielectric layer;

the array substrate further includes:

the step difference compensation patterns are arranged on the periphery of each shading pattern, and in the direction perpendicular to the substrate, the difference value between the height of the surface, back to the substrate, of each step difference compensation pattern and the height of the surface, back to the substrate, of each shading pattern is smaller than a first threshold value;

the orthographic projection of the buffer layer on the substrate is respectively overlapped with the orthographic projection of the shading pattern on the substrate, and the orthographic projection of the step difference compensation pattern on the substrate, and the thickness of the buffer layer is smaller than a second threshold value in the direction perpendicular to the substrate.

Optionally, the shading pattern is made of a metal material, and the step difference compensation pattern is made of a metal oxide material corresponding to the metal material.

Optionally, the shading pattern is made of a metal material, and the step difference compensation pattern is made of a negative photoresist material.

Optionally, the buffer layer has a thickness of

In the meantime.

Optionally, the capacitor structure further includes:

and the third polar plate is positioned on one side of the second polar plate, which is opposite to the substrate, and an interlayer insulating layer is arranged between the second polar plate and the third polar plate.

Based on the above technical solution of the array substrate, a second aspect of the invention provides a display device, which includes the array substrate.

Based on the technical solution of the array substrate, a third aspect of the present invention provides a method for manufacturing an array substrate, for manufacturing the array substrate, the method including:

manufacturing a plurality of independent shading graphs and segment difference compensation graphs positioned at the periphery of each shading graph on a substrate, wherein in the direction vertical to the substrate, the difference value between the height of the surface of the segment difference compensation graph back to the substrate and the height of the surface of the shading graph back to the substrate is smaller than a first threshold value;

manufacturing a buffer layer on one side of the plurality of independent shading graphs, which faces away from the substrate, wherein orthographic projections of the buffer layer on the substrate are respectively overlapped with orthographic projections of the shading graphs on the substrate, and orthographic projections of the step difference compensation graphs on the substrate, and the thickness of the buffer layer is smaller than a second threshold value in a direction perpendicular to the substrate;

making a driving circuit layer, wherein the driving circuit layer comprises a plurality of pixel driving circuits distributed in an array, the pixel driving circuits correspond to the shading graphs one by one, each pixel driving circuit comprises a capacitor structure, and the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate are sequentially stacked along the direction far away from the substrate; the shading patterns are multiplexed into the corresponding first polar plates in the pixel driving circuit, and the buffer layer is multiplexed into the dielectric layer.

Optionally, the step of fabricating a plurality of independent light-shielding patterns and a step compensation pattern around each of the light-shielding patterns on the substrate specifically includes:

forming a metal material layer by using a metal material;

manufacturing a photoresist layer on one side of the metal material layer back to the substrate;

carrying out exposure and development processes on the photoresist layer to form a photoresist reserved region and a photoresist removed region, wherein the photoresist reserved region corresponds to the region where the shading pattern is located, and the photoresist removed region corresponds to other regions except the region where the shading pattern is located;

and oxidizing the metal material layer in the photoresist removing area to change the metal material layer in the photoresist removing area into a metal oxide layer.

Optionally, the step of oxidizing the metal material layer in the photoresist removal region specifically includes:

and oxidizing the metal material layer in the photoresist removing area by adopting an anodic oxidation process.

Optionally, the step of fabricating a plurality of independent light-shielding patterns and a step compensation pattern around each of the light-shielding patterns on the substrate specifically includes:

forming a metal material layer by using a metal material;

patterning the metal material layer by adopting a composition process to form a plurality of independent shading patterns;

forming a negative photoresist layer by using a negative photoresist material, wherein the negative photoresist layer covers the plurality of independent shading patterns and the peripheral area of each shading pattern;

exposing the negative photoresist layer from one side of the substrate to form a negative photoresist layer reserved area and a negative photoresist layer removed area, wherein the negative photoresist layer removed area corresponds to the area where the shading pattern is located, and the negative photoresist layer reserved area corresponds to other areas except the area where the shading pattern is located;

and removing the negative photoresist layer in the negative photoresist layer removing region by using a developing solution, wherein the negative photoresist in the negative photoresist layer reserving region is used as the step difference compensation pattern.

Optionally, the step of manufacturing the capacitor structure further includes:

manufacturing an interlayer insulating layer on one side of the second plate, which is opposite to the substrate;

and manufacturing a third polar plate on one side of the interlayer insulating layer, which is opposite to the substrate.

In the technical scheme provided by the invention, the periphery of each shading graph is provided with a segment difference compensation graph capable of compensating the segment difference generated by the shading graph, so that the difference between the height of the surface of the segment difference compensation graph back to the substrate and the height of the surface of the shading graph back to the substrate is smaller than a first threshold value; meanwhile, the orthographic projection of the buffer layer on the substrate is respectively overlapped with the orthographic projection of the shading graph on the substrate and the orthographic projection of the level difference compensation graph on the substrate, so that the buffer layer completely covers the shading graph and the level difference compensation graph; because the segment difference compensation pattern compensates the segment difference generated by the shading pattern, the buffer layer does not need to cover the side face of the shading pattern, so that the thickness of the buffer layer in the direction perpendicular to the substrate can be reduced, namely, the shading pattern can be well covered only by forming a thin buffer layer, and the shading pattern is prevented from being damaged by the fact that etching liquid permeates into the shading pattern in the process of active layer pattern etching.

Moreover, since the capacitance value of the capacitor structure is inversely proportional to the thickness of the buffer layer (i.e., the dielectric layer), the capacitance value of the capacitor structure can be effectively increased by reducing the thickness of the buffer layer; therefore, when the technical scheme provided by the invention is applied to the display device, the display device is more in line with the development requirements of high definition and high refresh frequency.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic diagram illustrating a metal material layer formed on a substrate according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a photoresist layer formed on a metal material layer according to an embodiment of the present invention;

FIG. 3 is a schematic view of a photoresist layer after exposure and development according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of forming a light-shielding pattern according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a buffer layer spanning a step according to an embodiment of the present invention;

fig. 6 is a schematic view of a first structure of an array substrate according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a step compensation pattern according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a buffer layer provided in an embodiment of the present invention not crossing a step;

fig. 9 is a schematic view of a second structure of the array substrate according to the embodiment of the invention;

FIG. 10 is a schematic diagram illustrating the operation of an anodization process provided by an embodiment of the present invention;

FIG. 11 is a schematic view of an exposure of a negative photoresist layer provided by an embodiment of the present invention;

FIG. 12 is a schematic view of a step compensation pattern formed by a negative photoresist layer according to an embodiment of the present invention;

fig. 13 is a schematic diagram of a capacitor structure according to an embodiment of the invention.

Reference numerals:

10-a substrate, 20-a layer of metallic material,

21-light-shielding pattern, 22-step difference compensation pattern,

30-photoresist layer, 40-buffer layer,

50-a second plate, 60-an interlayer insulating layer,

70-the third plate, 80-the passivation layer,

81-a planar layer, 82-an anode layer,

90-negative photoresist layer.

Detailed Description

In order to further explain the array substrate, the manufacturing method thereof and the display device provided by the embodiment of the invention, the following detailed description is made with reference to the accompanying drawings.

The invention provides a display panel, which comprises an array substrate and light-emitting units arranged on the array substrate, wherein the array substrate comprises pixel driving circuits distributed in an array manner, and the pixel driving circuits are used for driving the corresponding light-emitting units to emit light.

The pixel driving circuit generally includes a storage capacitor and a plurality of thin film transistors, and as shown in the figure, the storage capacitor may include: cst1+ Cst2, where Cst1 is composed of an active layer pattern, a buffer layer, and a light shielding pattern, Cst2 is composed of an active layer pattern, an interlayer insulating layer, and a source-drain metal pattern, and Cst1 and Cst2 are connected in parallel.

The process of manufacturing the storage capacitor in the display panel is as follows:

as shown in fig. 1, a metallic material layer 20 is deposited on a substrate 10 using a metallic material.

As shown in fig. 2 to 4, the metal material layer 20 is patterned by a patterning process to form a plurality of independent light-shielding patterns 21.

As shown in fig. 5, a buffer layer 40 is deposited on a side of the plurality of independent light-shielding patterns 21 facing away from the substrate 10, and the buffer layer 40 has a first thickness d 1.

As shown in fig. 6, an active layer pattern (e.g., as indicated by 50 in fig. 6), an interlayer insulating layer 60, a source/drain metal pattern (e.g., as indicated by 70 in fig. 6), a passivation layer 80, a planarization layer 81, and an anode layer 82 are formed on a side of the buffer layer 40 opposite to the substrate 10.

With the improvement of the resolution and the refresh rate of the display panel, the capacitance value of the storage capacitor in the pixel driving circuit needs to be continuously increased, and when the capacitance value of the storage capacitor is increased, the area of each polar plate of the storage capacitor can be increased, or the distance between each polar plate of the storage capacitor can be reduced; however, since the layout space inside the display panel is limited, it is difficult to increase the capacitance of the storage capacitor by increasing the area of each plate of the storage capacitor.

In more detail, taking a 55 Inch 8K OLED panel as an example, the pixel density (PPI) of the 55 Inch 8K OLED panel is 2 times that of the 55 Inch 4K OLED panel, and metal routing in the 55 Inch 8K OLED panel is denser, so that it is very difficult to increase the capacitance of the storage capacitor by increasing the plate area of the storage capacitor.

The inventor of the present invention has found that, since Cst1 is composed of the active layer pattern, the buffer layer 40, and the light-shielding pattern 21, the buffer layer 40 can be thinned to increase the capacitance of the storage capacitor. However, since the buffer layer 40 is generally formed by depositing an insulating material such as SiO, SiN, SiON, etc. by using a plasma enhanced chemical vapor deposition method, and the buffer layer 40 needs to cover the surface of the light-shielding pattern 21 facing away from the substrate 10 and the side surface of the light-shielding pattern 21, in order to better cover the side surface of the light-shielding pattern 21 (i.e., the vicinity of the step formed by the light-shielding pattern 21) and prevent the etching solution from penetrating into the light-shielding pattern 21 and damaging the light-shielding pattern 21 during the etching process of the active layer pattern, the thickness of the buffer layer 40 needs to be set to be equal to the thickness

The above.

Based on the above findings, the inventor of the present invention considers that the step difference generated by the light-shielding pattern 21 is compensated by providing the step difference compensation pattern 22, so that when the buffer layer 40 is formed subsequently, the buffer layer 40 can cover the light-shielding pattern 21 and the step difference compensation pattern 22 at the same time, that is, the buffer layer 40 does not need to cover the side surface of the light-shielding pattern 21, and therefore, the light-shielding pattern 21 can be covered well only by forming the thinner buffer layer 40, and the etching liquid is prevented from penetrating into the light-shielding pattern 21 to damage the light-shielding pattern 21 in the active layer pattern etching process.

Referring to fig. 9, an embodiment of the invention provides an array substrate, including: a substrate 10, and a light shielding layer, a buffer layer 40 and a driving circuit layer disposed on the substrate 10; the light-shielding layer includes a plurality of independent light-shielding patterns 21; the driving circuit layer comprises a plurality of pixel driving circuits distributed in an array, the pixel driving circuits correspond to the shading patterns 21 one by one, each pixel driving circuit comprises a capacitor structure, and the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate 50 are sequentially stacked along the direction far away from the substrate 10; the shading graph 21 is reused as a first polar plate in the corresponding pixel driving circuit, and the buffer layer 40 is reused as the dielectric layer;

the array substrate further includes: a step compensation pattern 22 disposed around each of the light-shielding patterns 21, wherein in a direction perpendicular to the substrate 10, a difference between a height of a surface of the step compensation pattern 22 facing away from the substrate 10 and a height of the surface of the light-shielding pattern 21 facing away from the substrate 10 is smaller than a first threshold; the orthographic projection of the buffer layer 40 on the substrate 10 is respectively overlapped with the orthographic projection of the shading pattern 21 on the substrate 10 and the orthographic projection of the level difference compensation pattern 22 on the substrate 10, and the thickness d2 of the buffer layer 40 in the direction perpendicular to the substrate 10 is smaller than a second threshold value.

Specifically, the material of the substrate 10 may be selected according to actual needs, and for example, the substrate 10 is a transparent and flexible substrate, but is not limited thereto.

The light shielding layer may include a plurality of light shielding patterns 21 independent of each other, the light shielding patterns 21 correspond to the pixel driving circuits included in the driving circuit layer one to one, and each light shielding pattern 21 is configured to shield the corresponding pixel driving circuit from light incident from the substrate side to irradiate the pixel driving circuit.

The driving circuit layer comprises a plurality of pixel driving circuits distributed in an array mode, the pixel driving circuits can specifically comprise a capacitor structure and a plurality of thin film transistors, and the capacitor structure and the thin film transistors work in a matched mode to generate driving signals for driving the light-emitting elements to emit light.

The specific structure of the capacitor structure is various, and for example, the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate 50 are sequentially stacked along the direction far away from the substrate 10; the first polar plate and the second polar plate 50 are both conductive polar plates, and the dielectric layer is an insulating material layer. The array substrate further comprises a buffer layer 40, the buffer layer 40 is located on one side, back to the substrate 10, of the shading pattern 21, the buffer layer 40 is made of an insulating material, the shading pattern 21 can be reused as a first polar plate in the corresponding pixel driving circuit, the buffer layer 40 is reused as the dielectric layer, and the second polar plate 50 of the capacitor structure is arranged on one side, back to the substrate 10, of the buffer layer 40.

The array substrate further comprises step compensation patterns 22 arranged on the periphery of each shading pattern 21, wherein the step compensation patterns 22 are used for compensating the step generated by the shading patterns 21, the step compensation patterns 22 are tightly attached to the adjacent shading patterns 21, namely, no gap exists between the step compensation patterns 22 and the adjacent shading patterns 21.

After the level difference of the light-shielding pattern 21 is compensated by the level difference compensation pattern 22, the difference between the height of the surface of the level difference compensation pattern 22 facing away from the substrate 10 and the height of the surface of the light-shielding pattern 21 facing away from the substrate 10 in the direction perpendicular to the substrate 10 is smaller than a first threshold value; the value range of the first threshold can be set according to actual needs, and exemplarily, the first threshold is set at

Between (which may include endpoint values).

After the step compensation pattern 22 is disposed in the array substrate, the orthographic projection of the buffer layer 40 on the substrate 10 may be overlapped with the orthographic projection of the light-shielding pattern 21 on the substrate 10 and the orthographic projection of the step compensation pattern 22 on the substrate 10, respectively, so that the buffer layer 40 completely covers the light-shielding pattern 21 and the step compensation pattern 22. Since the step difference compensation pattern 22 compensates the step difference generated by the light-shielding pattern 21, so that the buffer layer 40 does not need to cover the side surface of the light-shielding pattern 21, the thickness of the buffer layer 40 can be appropriately reduced and disposed in the direction perpendicular to the substrate 10, and the buffer layerThe thickness of layer 40 is less than a second threshold; illustratively, the second threshold is

But is not limited thereto.

As can be seen from the specific structure of the array substrate provided in the foregoing embodiment, in the array substrate provided in the embodiment of the present invention, the step compensation pattern 22 capable of compensating the step generated by the light shielding pattern 21 is disposed at the periphery of each light shielding pattern 21, so that the difference between the height of the surface of the step compensation pattern 22 facing away from the substrate 10 and the height of the surface of the light shielding pattern 21 facing away from the substrate 10 is smaller than the first threshold; meanwhile, the orthographic projection of the buffer layer 40 on the substrate 10 is arranged to overlap the orthographic projection of the light-shielding pattern 21 on the substrate 10 and the orthographic projection of the level difference compensation pattern 22 on the substrate 10, respectively, so that the buffer layer 40 completely covers the light-shielding pattern 21 and the level difference compensation pattern 22; because the level difference compensation pattern 22 compensates the level difference generated by the shading pattern 21, the buffer layer 40 does not need to cover the side surface of the shading pattern 21, so that the thickness of the buffer layer 40 in the direction perpendicular to the substrate 10 can be reduced, the shading pattern 21 can be well covered by only manufacturing the thinner buffer layer 40, and the etching liquid is prevented from permeating into the shading pattern 21 to damage the shading pattern 21 in the etching process of the active layer pattern.

Moreover, since the capacitance value of the capacitor structure is inversely proportional to the thickness of the buffer layer 40 (i.e., the dielectric layer), the capacitance value of the capacitor structure can be effectively increased by reducing the thickness of the buffer layer 40; therefore, when the array substrate provided by the embodiment of the invention is applied to a display device, the display device better meets the development requirements of high definition and high refresh rate.

In some embodiments, the light shielding pattern 21 is made of a metal material, and the level difference compensation pattern 22 is made of a metal oxide material corresponding to the metal material.

Specifically, the shading graph 21 is made of a metal material, so that the shading graph 21 has good conductivity under the condition of shading performance, and therefore the better guarantee that the shading graph 21 is reused as the first pole plate of the capacitor structure is achieved, and the capacitor structure can have good conductivity.

The segment difference compensation pattern 22 is made of a metal oxide material corresponding to the metal material, so that the segment difference compensation pattern 22 has good insulating property, short circuit between different shading patterns 21 caused by the segment difference compensation pattern 22 is avoided, and the working performance of stable capacitor structure is ensured. In addition, the level difference compensation pattern 22 may also serve as a part of the buffer layer 40.

When the light-shielding pattern 21 and the level difference compensation pattern 22 having the above-described structure are manufactured, the method may specifically include the following steps:

as shown in fig. 1, a metal material is deposited on the substrate 10 to form a metal material layer 20, and the metal material may be, for example, aluminum, but is not limited thereto.

As shown in fig. 2, a photoresist layer 30 is formed on a side of the metal material layer 20 opposite to the substrate 10.

As shown in fig. 3, the photoresist layer is exposed by using a mask plate including a light-transmitting region and a light-shielding region, and then the exposed photoresist layer 30 is developed by using a developing solution to form a photoresist retaining region corresponding to a region where the light-shielding pattern 21 is located and a photoresist removing region corresponding to other regions except the region where the light-shielding pattern 21 is located.

As shown in fig. 7, after forming the photoresist remaining region and the photoresist removing region, a portion of the metal material layer 20 for forming the light shielding pattern 21 is covered by the photoresist layer located in the photoresist remaining region, and a portion of the metal material layer 20 located in the photoresist removing region is exposed, and the metal material layer 20 located in the photoresist removing region may be oxidized, so that the metal material layer 20 located in the photoresist removing region is changed into a metal oxide layer, and the metal oxide layer is used as the level difference compensation pattern 22. Exemplary, when the metal material isWhen the material layer 20 is made of metal aluminum, the formed metal oxide layer can be AlO_x。

In the array substrate provided in the above embodiment, the light-shielding pattern 21 is made of a metal material, and the step compensation pattern 22 is made of a metal oxide material corresponding to the metal material, so that when the light-shielding pattern 21 is formed by using the metal material layer 20, a portion that is originally to be removed in the metal material layer 20 (i.e., the remaining portion of the metal material layer 20 except for the portion for forming the light-shielding pattern 21) can be retained, and the portion is oxidized to form the metal oxide layer, and the metal oxide layer is used as the step compensation pattern 22.

Due to the fact that the part which is originally removed in the metal material layer 20 is reserved, the shading graph 21 is prevented from being formed to generate a step, the step which needs the buffer layer 40 to cross is avoided from being generated at the edge of the shading graph 21, and therefore when the buffer layer 40 is formed in the follow-up process, the buffer layer 40 is only required to be arranged to have a thin thickness, the shading graph 21 can be well covered, and etching liquid is prevented from permeating into the shading graph 21 to damage the shading graph 21 when the second polar plate 50 is formed in the follow-up process through etching. Moreover, because the thickness of buffer layer 40 attenuate makes the capacitance value of capacitor structure effectively promotes.

Therefore, in the array substrate provided by the embodiment, the capacitance value of the capacitor structure is improved by reducing the thickness of the dielectric layer without increasing the area of the electrode plate of the capacitor structure, and when the array substrate provided by the embodiment is applied to a display device, the display device better meets the development requirements of high definition and high refresh frequency.

In some embodiments, the light shielding pattern 21 may be made of a metal material, and the step difference compensation pattern 22 may be made of a negative photoresist material.

Specifically, when the light-shielding pattern 21 and the level difference compensation pattern 22 having the above-described structure are manufactured, the following steps may be specifically included:

as shown in fig. 1, a metal material is deposited on the substrate 10 to form a metal material layer 20, and the metal material may be, for example, aluminum, but is not limited thereto.

As shown in fig. 2, a photoresist layer 30 is formed on a side of the metal material layer 20 opposite to the substrate 10.

As shown in fig. 3, the photoresist layer is exposed by using a mask plate including a light-transmitting region and a light-shielding region, and then the exposed photoresist layer is developed by using a developing solution to form a photoresist retention region and a photoresist removal region, wherein the photoresist retention region corresponds to a region where the light-shielding pattern 21 is located, and the photoresist removal region corresponds to other regions except the region where the light-shielding pattern 21 is located.

As shown in fig. 4, after forming a photoresist reserved region and a photoresist removed region, a portion of the metal material layer 20 used for forming the light-shielding pattern 21 is covered by a photoresist layer located in the photoresist reserved region, a portion of the metal material layer 20 located in the photoresist removed region is exposed, and the photoresist layer located in the photoresist reserved region is used as a mask, and an etching process is adopted to etch and remove the exposed metal material layer 20, and finally the photoresist layer located in the photoresist reserved region is stripped off, so as to form the plurality of independent light-shielding patterns 21.

As shown in fig. 11, a negative photoresist layer 90 is formed by using a negative photoresist material, and the negative photoresist layer 90 can cover the plurality of individual light-shielding patterns 21 and the peripheral region of each light-shielding pattern 21. It should be noted that, in the direction perpendicular to the substrate 10, the thickness of the negative photoresist layer 90 should be as close as possible to the thickness of the light-shielding pattern 21, so as to better compensate for the step difference generated by the light-shielding pattern 21.

As shown in fig. 11, the negative photoresist layer 90 is irradiated with light from the side of the substrate 10 to expose the negative photoresist layer 90, due to the light shielding effect of the light shielding pattern 21, the negative photoresist layer 90 on the surface of the light shielding pattern 21 opposite to the substrate 10 is not exposed, and according to the property of the negative photoresist layer 90, after exposure, the negative photoresist layer 90 on the surface of the light shielding pattern 21 opposite to the substrate 10 is removed with a developing solution, as shown in fig. 12, a negative photoresist layer removing region is formed, i.e. the negative photoresist layer removing region corresponds to the region where the light shielding pattern 21 is located, and the negative photoresist layer 90 on the periphery of the light shielding pattern 21 is retained, i.e. the negative photoresist layer retaining region corresponds to other regions except the region where the light shielding pattern 21 is located, the negative photoresist in the remaining region of the negative photoresist layer serves as the level difference compensation pattern 22.

In the array substrate provided in the above embodiment, the light-shielding pattern 21 is made of a metal material, and the step difference compensation pattern 22 is made of a negative photoresist material, so that the step difference compensation pattern 22 compensates for the step difference generated by the light-shielding pattern 21, and a step required to be spanned by the buffer layer 40 is prevented from being generated at the edge of the light-shielding pattern 21, so that when the buffer layer 40 is formed subsequently, the buffer layer 40 is only required to be set to have a relatively thin thickness, thereby realizing good coverage of the light-shielding pattern 21, and preventing an etching solution from permeating into the light-shielding pattern 21 and damaging the light-shielding pattern 21 when the second electrode plate 50 is formed by etching subsequently. Moreover, because the thickness of buffer layer 40 attenuate makes the capacitance value of capacitor structure effectively promotes.

Moreover, since the capacitance value of the capacitor structure is inversely proportional to the thickness of the buffer layer 40 (i.e., the dielectric layer), the capacitance value of the capacitor structure can be effectively increased by reducing the thickness of the buffer layer 40; therefore, when the array substrate provided by the embodiment of the invention is applied to a display device, the display device better meets the development requirements of high definition and high refresh rate.

In some embodiments, the buffer layer 40 may be provided at a thickness

Between (which may include endpoint values).

The buffer layer 40 is formed to have a thickness of

In the meantime, the buffer layer 40 ensures good coverage of the light-shielding pattern 21, and prevents etching liquid from permeating into the light-shielding pattern 21 when the second electrode plate 50 is formed by subsequent etching, so that the capacitance value of the capacitor structure is improved to the maximum extent on the premise that the light-shielding pattern 21 is damaged.

As shown in fig. 13, in some embodiments, the capacitor structure further comprises: and a third polar plate 70 positioned on a side of the second polar plate 50 opposite to the substrate 10, wherein an interlayer insulating layer 60 is arranged between the second polar plate 50 and the third polar plate 70.

Specifically, the capacitor structure may further include a third plate 70 located on a side of the second plate 50 opposite to the substrate 10, and an interlayer insulating layer 60 is disposed between the second plate 50 and the third plate 70.

In more detail, the first plate, the dielectric layer and the second plate 50 form a first capacitor, the second plate 50, the interlayer insulating layer 60 and the third plate 70 form a second capacitor, and the first capacitor and the second capacitor are connected in parallel to form the capacitor structure.

The array substrate may further include a passivation layer 80, a flat layer 81, and an anode layer 82 on a side of the third electrode plate 70 facing away from the substrate 10, where the passivation layer 80, the flat layer 81, and the anode layer 82 are sequentially stacked along a direction away from the substrate 10; the second plate 50 is included in the capacitor structure as a first end of the capacitor structure, and the first plate and the third plate 70 are coupled together as a second end of the capacitor structure, which may be coupled to the anode layer 82.

When the array substrate is used for forming a top emission display device, the anode layer 82 may be a reflective anode layer 82, so that the reflective anode layer 82 can better reflect light emitted by the organic light emitting material layer out of the display device, which is more beneficial to improving the light emitting efficiency of the display device. In addition, the planarization layer 81 may be provided using an organic siloxane polymer material (SOG), but is not limited thereto.

It should be noted that the second electrode plate 50 may be made of an active layer in the array substrate, and the third electrode plate 70 may be made of a source-drain metal layer in the array substrate.

The embodiment of the invention also provides a display device which comprises the array substrate provided by the embodiment.

In the array substrate provided in the above embodiment, the step compensation pattern 22 capable of compensating the step generated by the light shielding pattern 21 is disposed at the periphery of each light shielding pattern 21, so that the difference between the height of the surface of the step compensation pattern 22 facing away from the substrate 10 and the height of the surface of the light shielding pattern 21 facing away from the substrate 10 is smaller than the first threshold; meanwhile, the orthographic projection of the buffer layer 40 on the substrate 10 is arranged to overlap the orthographic projection of the light-shielding pattern 21 on the substrate 10 and the orthographic projection of the level difference compensation pattern 22 on the substrate 10, respectively, so that the buffer layer 40 completely covers the light-shielding pattern 21 and the level difference compensation pattern 22; because the level difference compensation pattern 22 compensates the level difference generated by the shading pattern 21, the buffer layer 40 does not need to cover the side surface of the shading pattern 21, so that the thickness of the buffer layer 40 in the direction perpendicular to the substrate 10 can be reduced, the shading pattern 21 can be well covered by only manufacturing the thinner buffer layer 40, and the etching liquid is prevented from permeating into the shading pattern 21 to damage the shading pattern 21 in the etching process of the active layer pattern. Moreover, since the capacitance value of the capacitor structure is inversely proportional to the thickness of the buffer layer 40 (i.e., the dielectric layer), the capacitance value of the capacitor structure can be effectively increased by reducing the thickness of the buffer layer 40; therefore, when the display device provided by the embodiment of the invention comprises the array substrate, the display device is more in line with the development requirements of high definition and high refresh rate.

The display device may be: any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer and the like.

The embodiment of the invention also provides a manufacturing method of the array substrate, which is used for manufacturing the array substrate provided by the embodiment, and the manufacturing method comprises the following steps:

manufacturing a plurality of independent light-shielding patterns 21 and step compensation patterns 22 located at the periphery of each light-shielding pattern 21 on a substrate 10, wherein in a direction perpendicular to the substrate 10, the difference between the height of the surface of the step compensation patterns 22 facing away from the substrate 10 and the height of the surface of the light-shielding patterns 21 facing away from the substrate 10 is smaller than a first threshold value;

manufacturing a buffer layer 40 on a side of the plurality of independent light-shielding patterns 21 facing away from the substrate 10, wherein orthographic projections of the buffer layer 40 on the substrate 10 are respectively overlapped with orthographic projections of the light-shielding patterns 21 on the substrate 10, and orthographic projections of the level difference compensation patterns 22 on the substrate 10, and in a direction perpendicular to the substrate 10, the thickness of the buffer layer 40 is smaller than a second threshold value;

manufacturing a driving circuit layer, wherein the driving circuit layer comprises a plurality of pixel driving circuits distributed in an array manner, the pixel driving circuits correspond to the shading patterns 21 one by one, each pixel driving circuit comprises a capacitor structure, and the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate 50 are sequentially stacked along the direction far away from the substrate 10; the shading patterns 21 are multiplexed as the first polar plates in the corresponding pixel driving circuits, and the buffer layer 40 is multiplexed as the dielectric layer.

Specifically, the material of the substrate 10 may be selected according to actual needs, and for example, the substrate 10 is a transparent and flexible substrate, but is not limited thereto.

The light shielding layer may include a plurality of light shielding patterns 21 independent of each other, the light shielding patterns 21 correspond to the pixel driving circuits included in the driving circuit layer one to one, and each light shielding pattern 21 is configured to shield the corresponding pixel driving circuit from light incident from the substrate side to irradiate the pixel driving circuit.

The driving circuit layer comprises a plurality of pixel driving circuits distributed in an array mode, the pixel driving circuits can specifically comprise a capacitor structure and a plurality of thin film transistors, and the capacitor structure and the thin film transistors work in a matched mode to generate driving signals for driving the light-emitting elements to emit light.

The specific structure of the capacitor structure is various, and for example, the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate 50 are sequentially stacked along the direction far away from the substrate 10; the first polar plate and the second polar plate 50 are both conductive polar plates, and the dielectric layer is an insulating material layer. The array substrate further comprises a buffer layer 40, the buffer layer 40 is located on one side, back to the substrate 10, of the shading pattern 21, the buffer layer 40 is made of an insulating material, the shading pattern 21 can be reused as a first polar plate in the corresponding pixel driving circuit, the buffer layer 40 is reused as the dielectric layer, and the second polar plate 50 of the capacitor structure is arranged on one side, back to the substrate 10, of the buffer layer 40.

The array substrate further comprises step compensation patterns 22 arranged on the periphery of each shading pattern 21, wherein the step compensation patterns 22 are used for compensating the step generated by the shading patterns 21, the step compensation patterns 22 are tightly attached to the adjacent shading patterns 21, namely, no gap exists between the step compensation patterns 22 and the adjacent shading patterns 21.

After the level difference of the light-shielding pattern 21 is compensated by the level difference compensation pattern 22, the difference between the height of the surface of the level difference compensation pattern 22 facing away from the substrate 10 and the height of the surface of the light-shielding pattern 21 facing away from the substrate 10 in the direction perpendicular to the substrate 10 is smaller than a first threshold value; the value range of the first threshold can be set according to actual needs, and exemplarily, the first threshold is set at

In the meantime.

After the step compensation pattern 22 is disposed in the array substrate, the orthographic projection of the buffer layer 40 on the substrate 10 may be overlapped with the orthographic projection of the light-shielding pattern 21 on the substrate 10 and the orthographic projection of the step compensation pattern 22 on the substrate 10, respectively, so that the buffer layer 40 is completely overlappedThe light-shielding pattern 21 and the level difference compensation pattern 22 are entirely covered. Since the step difference compensation pattern 22 compensates the step difference generated by the light-shielding pattern 21, so that the buffer layer 40 does not need to cover the side surface of the light-shielding pattern 21, the thickness of the buffer layer 40 can be appropriately reduced, and the buffer layer 40 is disposed in the direction perpendicular to the substrate 10, and the thickness of the buffer layer 40 is smaller than the second threshold value; illustratively, the second threshold is

But is not limited thereto.

In the array substrate manufactured by the manufacturing method provided by the embodiment of the invention, the step difference compensation pattern 22 capable of compensating the step difference generated by the shading pattern 21 is arranged at the periphery of each shading pattern 21, so that the difference between the height of the surface of the step difference compensation pattern 22, which is back to the substrate 10, and the height of the surface of the shading pattern 21, which is back to the substrate 10, is smaller than a first threshold value; meanwhile, the orthographic projection of the buffer layer 40 on the substrate 10 is arranged to overlap the orthographic projection of the light-shielding pattern 21 on the substrate 10 and the orthographic projection of the level difference compensation pattern 22 on the substrate 10, respectively, so that the buffer layer 40 completely covers the light-shielding pattern 21 and the level difference compensation pattern 22; because the level difference compensation pattern 22 compensates the level difference generated by the shading pattern 21, the buffer layer 40 does not need to cover the side surface of the shading pattern 21, so that the thickness of the buffer layer 40 in the direction perpendicular to the substrate 10 can be reduced, the shading pattern 21 can be well covered by only manufacturing the thinner buffer layer 40, and the etching liquid is prevented from permeating into the shading pattern 21 to damage the shading pattern 21 in the etching process of the active layer pattern.

Moreover, since the capacitance value of the capacitor structure is inversely proportional to the thickness of the buffer layer 40 (i.e., the dielectric layer), the capacitance value of the capacitor structure can be effectively increased by reducing the thickness of the buffer layer 40; therefore, when the array substrate manufactured by the manufacturing method provided by the embodiment of the invention is applied to a display device, the display device better meets the development requirements of high definition and high refresh rate.

In some embodiments, the step of forming a plurality of independent light-shielding patterns 21 and a step compensation pattern 22 around each of the light-shielding patterns 21 on the substrate 10 specifically includes:

forming a metal material layer 20 using a metal material;

manufacturing a photoresist layer on one side of the metal material layer 20, which faces away from the substrate 10;

carrying out exposure and development processes on the photoresist layer to form a photoresist reserved region and a photoresist removed region, wherein the photoresist reserved region corresponds to the region where the shading pattern 21 is located, and the photoresist removed region corresponds to other regions except the region where the shading pattern 21 is located;

and oxidizing the metal material layer 20 in the photoresist removing region to change the metal material layer 20 in the photoresist removing region into a metal oxide layer.

Specifically, the shading graph 21 is made of a metal material, so that the shading graph 21 has good conductivity under the condition of shading performance, and therefore the better guarantee that the shading graph 21 is reused as the first pole plate of the capacitor structure is achieved, and the capacitor structure can have good conductivity.

The segment difference compensation pattern 22 is made of a metal oxide material corresponding to the metal material, so that the segment difference compensation pattern 22 has good insulating property, short circuit between different shading patterns 21 caused by the segment difference compensation pattern 22 is avoided, and the working performance of stable capacitor structure is ensured. In addition, the level difference compensation pattern 22 may also serve as a part of the buffer layer 40.

When the light-shielding pattern 21 and the level difference compensation pattern 22 having the above-described structure are manufactured, the method may specifically include the following steps:

as shown in fig. 1, a metal material layer 20 is deposited on a substrate 10 by a magnetron sputtering apparatus, and the metal material may be, for example, aluminum, but is not limited thereto.

As shown in fig. 2, a photoresist layer 30 is formed on a side of the metal material layer 20 opposite to the substrate 10.

As shown in fig. 3, the photoresist layer is exposed by using a mask plate including a light-transmitting region and a light-shielding region, and then the exposed photoresist layer 30 is developed by using a developing solution to form a photoresist retaining region corresponding to a region where the light-shielding pattern 21 is located and a photoresist removing region corresponding to other regions except the region where the light-shielding pattern 21 is located.

As shown in fig. 7, after forming the photoresist remaining region and the photoresist removing region, a portion of the metal material layer 20 for forming the light shielding pattern 21 is covered by the photoresist layer located in the photoresist remaining region, and a portion of the metal material layer 20 located in the photoresist removing region is exposed, and the metal material layer 20 located in the photoresist removing region may be oxidized, so that the metal material layer 20 located in the photoresist removing region is changed into a metal oxide layer, and the metal oxide layer is used as the level difference compensation pattern 22. For example, when the metal material layer 20 is made of aluminum metal, the metal oxide layer formed may be AlO_x。

In the array substrate manufactured by the manufacturing method provided in the above embodiment, the light-shielding pattern 21 is made of a metal material, and the level difference compensation pattern 22 is made of a metal oxide material corresponding to the metal material, so that when the light-shielding pattern 21 is formed by using the metal material layer 20, a portion that is originally to be removed in the metal material layer 20 (i.e., the remaining portion of the metal material layer 20 except for the portion for forming the light-shielding pattern 21) can be retained, and the portion is oxidized to form the metal oxide layer, and the metal oxide layer is used as the level difference compensation pattern 22.

Due to the fact that the part which is originally removed in the metal material layer 20 is reserved, the shading graph 21 is prevented from being formed to generate a step, the step which needs the buffer layer 40 to cross is avoided from being generated at the edge of the shading graph 21, and therefore when the buffer layer 40 is formed in the follow-up process, the buffer layer 40 is only required to be arranged to have a thin thickness, the shading graph 21 can be well covered, and etching liquid is prevented from permeating into the shading graph 21 to damage the shading graph 21 when the second polar plate 50 is formed in the follow-up process through etching. Moreover, because the thickness of buffer layer 40 attenuate makes the capacitance value of capacitor structure effectively promotes.

Therefore, in the array substrate manufactured by the manufacturing method provided by the embodiment, the capacitance value of the capacitor structure is improved by reducing the thickness of the dielectric layer without increasing the area of the electrode plate of the capacitor structure, and when the array substrate manufactured by the manufacturing method provided by the embodiment is applied to a display device, the display device better meets the development requirements of high definition and high refresh frequency.

As shown in fig. 10, in some embodiments, the step of oxidizing the metal material layer 20 in the photoresist removing region specifically includes:

and oxidizing the metal material layer 20 in the photoresist removing area by adopting an anodic oxidation process.

Specifically, as shown in fig. 3, after forming a photoresist remaining region and a photoresist removing region, a portion of the metal material layer 20 for forming the light shielding pattern 21 is covered by the photoresist layer 30 located in the photoresist remaining region, and a portion of the metal material layer 20 located in the photoresist removing region is exposed.

Putting the structure shown in fig. 3 into an electrolytic cell a as an anode, wherein the electrolytic cell a contains an electrolyte B, and the electrolyte B can adopt an aqueous solution of ammonium tartrate and ethylene glycol, but is not limited to the above; the electrolytic cell A is also provided with a cathode, the anode and the cathode are respectively coupled with a direct current power supply, under a constant current mode, the anode generates an oxidation reaction, and the cathode generates a reduction reaction, so that the metal material layer 20 positioned in the photoresist removing area is oxidized, and the metal oxide layer positioned in the photoresist removing area is formed.

It should be noted that, in the anodic oxidation process, besides the constant current mode, a constant voltage first and then constant current mode, or a constant current first and then constant voltage mode may be adopted.

In some embodiments, the step of forming a plurality of independent light-shielding patterns 21 and a step compensation pattern 22 around each of the light-shielding patterns 21 on the substrate 10 specifically includes:

forming a metal material layer 20 using a metal material;

patterning the metal material layer 20 by using a patterning process to form a plurality of independent light-shielding patterns 21;

forming a negative photoresist layer 90 by using a negative photoresist material, wherein the negative photoresist layer 90 covers the plurality of independent light-shielding patterns 21 and the peripheral area of each light-shielding pattern 21;

exposing the negative photoresist layer 90 from the side where the substrate 10 is located to form a negative photoresist layer 90 reserved region and a negative photoresist layer 90 removed region, wherein the negative photoresist layer 90 removed region corresponds to the region where the light-shielding pattern 21 is located, and the negative photoresist layer 90 reserved region corresponds to other regions except the region where the light-shielding pattern 21 is located;

and removing the negative photoresist layer 90 in the removed region of the negative photoresist layer 90 by using a developing solution, and using the negative photoresist in the reserved region of the negative photoresist layer 90 as the step difference compensation pattern 22.

Specifically, when the light-shielding pattern 21 and the level difference compensation pattern 22 having the above-described structure are manufactured, the following steps may be specifically included:

as shown in fig. 1, a metal material is deposited on the substrate 10 to form a metal material layer 20, and the metal material may be, for example, aluminum, but is not limited thereto.

As shown in fig. 2, a photoresist layer 30 is formed on a side of the metal material layer 20 opposite to the substrate 10.

As shown in fig. 3, the photoresist layer is exposed by using a mask plate including a light-transmitting region and a light-shielding region, and then the exposed photoresist layer is developed by using a developing solution to form a photoresist retention region and a photoresist removal region, wherein the photoresist retention region corresponds to a region where the light-shielding pattern 21 is located, and the photoresist removal region corresponds to other regions except the region where the light-shielding pattern 21 is located.

As shown in fig. 4, after forming a photoresist reserved region and a photoresist removed region, a portion of the metal material layer 20 used for forming the light-shielding pattern 21 is covered by a photoresist layer located in the photoresist reserved region, a portion of the metal material layer 20 located in the photoresist removed region is exposed, and the photoresist layer located in the photoresist reserved region is used as a mask, and an etching process is adopted to etch and remove the exposed metal material layer 20, and finally the photoresist layer located in the photoresist reserved region is stripped off, so as to form the plurality of independent light-shielding patterns 21.

As shown in fig. 11, a negative photoresist layer 90 is formed by using a negative photoresist material, and the negative photoresist layer 90 can cover the plurality of individual light-shielding patterns 21 and the peripheral region of each light-shielding pattern 21. It should be noted that, in the direction perpendicular to the substrate 10, the thickness of the negative photoresist layer 90 should be as close as possible to the thickness of the light-shielding pattern 21, so as to better compensate for the step difference generated by the light-shielding pattern 21.

As shown in fig. 11, the negative photoresist layer 90 is irradiated with light from the side of the substrate 10 to expose the negative photoresist layer 90, due to the light shielding effect of the light shielding pattern 21, the negative photoresist layer 90 on the surface of the light shielding pattern 21 opposite to the substrate 10 is not exposed, and according to the property of the negative photoresist layer 90, after exposure, the negative photoresist layer 90 on the surface of the light shielding pattern 21 opposite to the substrate 10 is removed with a developing solution, as shown in fig. 12, a negative photoresist layer removing region is formed, i.e. the negative photoresist layer removing region corresponds to the region where the light shielding pattern 21 is located, and the negative photoresist layer 90 on the periphery of the light shielding pattern 21 is retained, i.e. the negative photoresist layer retaining region corresponds to other regions except the region where the light shielding pattern 21 is located, the negative photoresist in the remaining region of the negative photoresist layer serves as the level difference compensation pattern 22.

In the array substrate manufactured by the manufacturing method provided by the embodiment, the shading pattern 21 is made of a metal material, and the step difference compensation pattern 22 is made of a negative photoresist material, so that the step difference compensation pattern 22 compensates for the step difference generated by the shading pattern 21, and a step needing to be spanned by the buffer layer 40 is avoided being generated at the edge of the shading pattern 21, and thus when the buffer layer 40 is formed subsequently, the buffer layer 40 is only required to be arranged with a thinner thickness, so that the shading pattern 21 can be well covered, and the shading pattern 21 is prevented from being damaged due to the fact that etching liquid can permeate into the shading pattern 21 when the second electrode plate 50 is formed by etching subsequently. Moreover, because the thickness of buffer layer 40 attenuate makes the capacitance value of capacitor structure effectively promotes.

Moreover, since the capacitance value of the capacitor structure is inversely proportional to the thickness of the buffer layer 40 (i.e., the dielectric layer), the capacitance value of the capacitor structure can be effectively increased by reducing the thickness of the buffer layer 40; therefore, when the array substrate manufactured by the manufacturing method provided by the embodiment of the invention is applied to a display device, the display device better meets the development requirements of high definition and high refresh rate.

In some embodiments, the step of fabricating the capacitor structure further comprises:

manufacturing an interlayer insulating layer 60 on one side of the second plate 50, which faces away from the substrate 10;

a third plate 70 is formed on the side of the interlayer insulating layer 60 facing away from the substrate 10.

Specifically, the capacitor structure may further include a third plate 70 located on a side of the second plate 50 opposite to the substrate 10, and an interlayer insulating layer 60 is disposed between the second plate 50 and the third plate 70.

In more detail, the first plate, the dielectric layer and the second plate 50 form a first capacitor, the second plate 50, the interlayer insulating layer 60 and the third plate 70 form a second capacitor, and the first capacitor and the second capacitor are connected in parallel to form the capacitor structure.

The array substrate may further include a passivation layer 80, a flat layer 81, and an anode layer 82 on a side of the third electrode plate 70 facing away from the substrate 10, where the passivation layer 80, the flat layer 81, and the anode layer 82 are sequentially stacked along a direction away from the substrate 10; the second plate 50 is included in the capacitor structure as a first end of the capacitor structure, and the first plate and the third plate 70 are coupled together as a second end of the capacitor structure, which may be coupled to the anode layer 82.

When the array substrate is used for forming a top emission display device, the anode layer 82 may be a reflective anode layer 82, so that the reflective anode layer 82 can better reflect light emitted by the organic light emitting material layer out of the display device, which is more beneficial to improving the light emitting efficiency of the display device. In addition, the planarization layer 81 may be provided using an organic siloxane polymer material (SOG), but is not limited thereto.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (11)

1. An array substrate, comprising: the light-shielding layer, the buffer layer and the driving circuit layer are arranged on the substrate;

the light shielding layer comprises a plurality of independent light shielding patterns;

the driving circuit layer comprises a plurality of pixel driving circuits distributed in an array mode, the pixel driving circuits correspond to the shading graphs one by one, each pixel driving circuit comprises a capacitor structure, and the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate are sequentially stacked along the direction far away from the substrate;

the shading patterns are multiplexed into corresponding first polar plates in the pixel driving circuit, and the buffer layer is multiplexed into the dielectric layer;

the array substrate further includes:

the step difference compensation patterns are arranged on the periphery of each shading pattern, and in the direction perpendicular to the substrate, the difference value between the height of the surface, back to the substrate, of each step difference compensation pattern and the height of the surface, back to the substrate, of each shading pattern is smaller than a first threshold value;

the orthographic projection of the buffer layer on the substrate is respectively overlapped with the orthographic projection of the shading pattern on the substrate, and the orthographic projection of the step difference compensation pattern on the substrate, and the thickness of the buffer layer is smaller than a second threshold value in the direction perpendicular to the substrate.

2. The array substrate of claim 1, wherein the light-shielding pattern is made of a metal material, and the step compensation pattern is made of a metal oxide material corresponding to the metal material.

3. The array substrate of claim 1, wherein the light-shielding pattern is made of a metal material, and the step compensation pattern is made of a negative photoresist material.

4. The array substrate of claim 1, wherein the buffer layer has a thickness of

In the meantime.

5. The array substrate of claim 1, wherein the capacitor structure further comprises:

and the third polar plate is positioned on one side of the second polar plate, which is opposite to the substrate, and an interlayer insulating layer is arranged between the second polar plate and the third polar plate.

6. A display device, comprising: the array substrate according to any one of claims 1 to 5.

7. A manufacturing method of an array substrate, which is used for manufacturing the array substrate according to any one of claims 1 to 5, the manufacturing method comprising:

manufacturing a plurality of independent shading graphs and segment difference compensation graphs positioned at the periphery of each shading graph on a substrate, wherein in the direction vertical to the substrate, the difference value between the height of the surface of the segment difference compensation graph back to the substrate and the height of the surface of the shading graph back to the substrate is smaller than a first threshold value;

manufacturing a buffer layer on one side of the plurality of independent shading graphs, which faces away from the substrate, wherein orthographic projections of the buffer layer on the substrate are respectively overlapped with orthographic projections of the shading graphs on the substrate, and orthographic projections of the step difference compensation graphs on the substrate, and the thickness of the buffer layer is smaller than a second threshold value in a direction perpendicular to the substrate;

making a driving circuit layer, wherein the driving circuit layer comprises a plurality of pixel driving circuits distributed in an array, the pixel driving circuits correspond to the shading graphs one by one, each pixel driving circuit comprises a capacitor structure, and the capacitor structure comprises: the first polar plate, the dielectric layer and the second polar plate are sequentially stacked along the direction far away from the substrate; the shading patterns are multiplexed into the corresponding first polar plates in the pixel driving circuit, and the buffer layer is multiplexed into the dielectric layer.

8. The method for manufacturing an array substrate according to claim 7, wherein the step of manufacturing a plurality of independent light-shielding patterns and step compensation patterns around each of the light-shielding patterns on a substrate specifically comprises:

forming a metal material layer by using a metal material;

manufacturing a photoresist layer on one side of the metal material layer back to the substrate;

carrying out exposure and development processes on the photoresist layer to form a photoresist reserved region and a photoresist removed region, wherein the photoresist reserved region corresponds to the region where the shading pattern is located, and the photoresist removed region corresponds to other regions except the region where the shading pattern is located;

and oxidizing the metal material layer in the photoresist removing area to change the metal material layer in the photoresist removing area into a metal oxide layer.

9. The method for manufacturing the array substrate according to claim 8, wherein the step of oxidizing the metal material layer in the photoresist removing region specifically comprises:

and oxidizing the metal material layer in the photoresist removing area by adopting an anodic oxidation process.

10. The method for manufacturing an array substrate according to claim 7, wherein the step of manufacturing a plurality of independent light-shielding patterns and step compensation patterns around each of the light-shielding patterns on a substrate specifically comprises:

forming a metal material layer by using a metal material;

patterning the metal material layer by adopting a composition process to form a plurality of independent shading patterns;

forming a negative photoresist layer by using a negative photoresist material, wherein the negative photoresist layer covers the plurality of independent shading patterns and the peripheral area of each shading pattern;

exposing the negative photoresist layer from one side of the substrate to form a negative photoresist layer reserved area and a negative photoresist layer removed area, wherein the negative photoresist layer removed area corresponds to the area where the shading pattern is located, and the negative photoresist layer reserved area corresponds to other areas except the area where the shading pattern is located;

and removing the negative photoresist layer in the negative photoresist layer removing region by using a developing solution, wherein the negative photoresist in the negative photoresist layer reserving region is used as the step difference compensation pattern.

11. The method for manufacturing the array substrate according to claim 7, wherein the step of manufacturing the capacitor structure further comprises:

manufacturing an interlayer insulating layer on one side of the second plate, which is opposite to the substrate;

and manufacturing a third polar plate on one side of the interlayer insulating layer, which is opposite to the substrate.

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