CN108022953B

CN108022953B - Display device with auxiliary electrode

Info

Publication number: CN108022953B
Application number: CN201711033244.XA
Authority: CN
Inventors: 沈成斌; 金惠淑
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2016-10-31
Filing date: 2017-10-30
Publication date: 2021-11-02
Anticipated expiration: 2037-10-30
Also published as: US10269879B2; US20180122876A1; KR20180047578A; CN108022953A

Abstract

The present disclosure relates to a display device having an auxiliary electrode, and provides a display device capable of preventing or reducing luminance unevenness due to a voltage drop by using an auxiliary electrode. The display device may include a bank insulating layer forming an undercut region for connecting the auxiliary electrode to the upper electrode of the light emitting structure. The bank insulating layer may include a first bank penetration hole overlapping the auxiliary electrode and a second bank penetration hole spaced apart from the first bank penetration hole. The second bank penetration hole may overlap with a lower penetration hole of a lower passivation layer disposed between the auxiliary electrode and the bank insulating layer. The lower through hole may overlap the auxiliary electrode.

Description

Display device with auxiliary electrode

Cross Reference to Related Applications

This application claims priority from korean patent application No. 10-2016-0143863, filed on 31/10/2016, which is hereby incorporated by reference as if fully set forth herein.

Technical Field

The present disclosure relates to a display device capable of preventing or reducing luminance unevenness due to voltage drop by using an auxiliary electrode.

Background

Many electronic devices such as monitors, TVs, notebook computers, and digital cameras include a display device for implementing or displaying images. For example, the display device may include a liquid crystal display device or an organic light emitting display device.

The display device may include a light emitting structure for realizing a specific color. For example, the light emitting structure may include a lower electrode, a light emitting layer, and an upper electrode, which are sequentially stacked.

The display device may use the auxiliary electrode to prevent voltage drop and brightness unevenness due to the resistance of the upper electrode. The auxiliary electrode may be spaced apart from the light emitting structure. For example, the auxiliary electrode may be disposed outside a data line that supplies a data signal to the light emitting structure. The auxiliary electrode may be electrically connected to the upper electrode of the light emitting structure.

In the display device, various structures may be used to connect the upper electrode and the auxiliary electrode. For example, in a display device, an undercut region may be formed on the auxiliary electrode using a bank insulating layer covering an edge of the lower electrode so that a portion of the auxiliary electrode may be exposed through the light emitting layer. Therefore, in the display device, the upper electrode formed through the process having better step coverage than the light emitting layer may be electrically connected to a portion of the auxiliary electrode where the light emitting layer is not deposited.

However, since the vertical distance of the undercut region (under-cut region) formed by the bank insulating layer is not large, the adhesive layer used in the process of attaching the upper substrate to the lower substrate formed with the upper electrode may not sufficiently flow to the undercut region, so that a void may be formed in the undercut region. In the display device, the gap formed between the auxiliary electrode and the bank insulating layer may be regarded as a spot on the screen. Therefore, in the display device, the void may reduce the quality of the image. In addition, in the display device, since external moisture may permeate through the gap, luminance unevenness is generated due to a reduction in characteristics of some thin film transistors.

Disclosure of Invention

Accordingly, the present disclosure is directed to a display device having auxiliary electrodes that substantially obviates one or more problems due to limitations and disadvantages of the related art.

In various embodiments, the present disclosure provides a display device capable of preventing generation of a void due to an adhesive layer in an undercut region.

In various embodiments, the present disclosure provides a display device in which an undercut region between an auxiliary electrode and a bank insulating layer may be completely filled with an adhesive layer used in an attachment process.

Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, there is provided in one or more embodiments a display device including an auxiliary electrode on a first substrate. The passivation layer is disposed on the auxiliary electrode. The first hole extends through the passivation layer and overlaps at least a portion of the auxiliary electrode. A bank insulating layer is disposed on the passivation layer. The first bank layer hole extends through the bank insulating layer and partially overlaps the first hole. A second bank aperture extends through the bank insulating layer and overlaps the first aperture, and the second bank aperture is spaced apart from the first bank aperture. An upper cladding layer is disposed between the passivation layer and the bank insulating layer.

In one embodiment, a side surface of the second bank hole may overlap the first hole.

In one embodiment, the planar size of the second bank layer hole may be smaller than the planar size of the first bank layer hole.

In one embodiment, the second bank layer hole may be positioned adjacent to a side surface of the first bank layer hole.

In one embodiment, the planar shape of the second bank hole may be a polygon of the same type as the planar shape of the first bank hole.

In one embodiment, the planar shape of the first bank hole and the second bank hole may be a rectangular shape.

In one embodiment, the first bank layer hole may have a rectangular shape, and the second bank layer hole may be positioned adjacent to the first and second sides of the first bank layer hole.

In one embodiment, a second substrate may be disposed on the bank insulating layer. An adhesive layer may be disposed between the bank insulating layer and the second substrate. The adhesive layer may extend between the auxiliary electrode and the bank insulating layer through the first bank layer hole and the second bank layer hole.

In one embodiment, a light emitting layer may be disposed on a first portion of the auxiliary electrode in the first hole, a second electrode may be disposed on the light emitting layer, and the second electrode may contact a second portion of the auxiliary electrode in the first hole.

In one embodiment, the light emitting layer may be discontinuous in an undercut region between the bank insulating layer and the auxiliary electrode.

In further embodiments of the present disclosure, a display device includes an auxiliary electrode on a substrate. The passivation layer is disposed on the auxiliary electrode. The first hole extends through the passivation layer and exposes the auxiliary electrode. A bank insulating layer is disposed on the passivation layer. The second hole extends through the bank insulating layer and overlaps the auxiliary electrode, and a periphery of the second hole overlaps the first hole. The perimeter of the second aperture includes one or more protrusions that extend the perimeter of the second aperture outward relative to adjacent portions of the perimeter of the second aperture.

In one embodiment, the first aperture may include a side surface adjacent to one or more protrusions of the perimeter of the second aperture. The side surface of the first aperture may extend linearly adjacent to the one or more projections.

In one embodiment, a thin film transistor may be disposed between the substrate and the passivation layer. The thin film transistor may be spaced apart from the auxiliary electrode. The auxiliary electrode may include the same material as one of a gate electrode, a source electrode, and a drain electrode of the thin film transistor.

In one embodiment, the first electrode may be coupled to a drain electrode of the thin film transistor. A light emitting layer may be disposed on the first electrode. The second electrode may be disposed on the light emitting layer, and the second electrode contacts the auxiliary electrode in the first hole.

In further embodiments, the present disclosure provides a display device including a first substrate. An auxiliary electrode is provided on the first substrate. A passivation layer is disposed on the auxiliary electrode, and the auxiliary electrode is exposed through a first hole extending through the passivation layer. A bank insulating layer is disposed on the passivation layer. The second hole extends through the bank insulating layer over the first portion of the auxiliary electrode. An undercut region is formed between the bank insulating layer and the second portion of the auxiliary electrode, and the bank insulating layer has a surface facing the second portion of the auxiliary electrode in the undercut region. The third hole extends through the bank insulating layer in the undercut region.

In one embodiment, a plurality of third holes may extend through the bank insulating layer in the undercut region.

In one embodiment, a first portion of the plurality of third apertures may be disposed adjacent a first side of a second aperture and a second portion of the plurality of third apertures may be disposed adjacent a second side of the second aperture.

In one embodiment, a second substrate may be disposed on the bank insulating layer. An adhesive layer may be disposed between the bank insulating layer and the second substrate, and the adhesive layer may extend into the undercut region through the second hole and the third hole.

In one embodiment, a transistor may be provided on the first electrode. The first electrode may be coupled to the transistor. A light emitting layer may be disposed on the first electrode, and a second electrode may be disposed on the light emitting layer. The second electrode may contact a second portion of the auxiliary electrode in the undercut region.

In one embodiment, the light emitting layer may be discontinuous in the undercut region.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

fig. 1 is a plan view schematically illustrating a display device according to one or more embodiments of the present disclosure;

FIG. 2 is an enlarged view of region P shown in FIG. 1;

FIG. 3A is a cross-sectional view taken along line I-I' of FIG. 1;

FIG. 3B is a sectional view taken along line II-II' of FIG. 2;

FIG. 3C is a cross-sectional view taken along line III-III' of FIG. 2;

fig. 4 is a plan view illustrating a region P of a display device according to another embodiment of the present disclosure;

fig. 5 is a plan view illustrating a region P of a display device according to another embodiment of the present disclosure;

fig. 6 is a sectional view taken along line IV-IV' of fig. 5.

Detailed Description

Hereinafter, details related to the above-described objects, technical structures, and operational effects of the embodiments of the present disclosure will be clearly understood through the following detailed description with reference to the accompanying drawings showing some embodiments of the present disclosure. Here, the embodiments of the present disclosure are provided in order to allow the technical spirit of the present disclosure to be satisfactorily transferred to those skilled in the art, and thus the present disclosure may be embodied in other forms without being limited to the following embodiments.

In addition, the same or similar elements may be denoted by the same reference numerals throughout the specification, and in the drawings, the length and thickness of layers and regions may be exaggerated for convenience. It will be understood that when a first element is referred to as being "on" a second element, a third element may be interposed between the first and second elements, although the first element may be disposed on the second element so as to be in contact with the second element.

Herein, terms such as "first" and "second" may be used to distinguish any one element from another element. However, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art without departing from the technical spirit of the present disclosure.

Certain terminology is used in the description of the disclosure for the purpose of describing particular embodiments only and is not intended to limit the scope of the disclosure. For example, an element described in the singular is intended to comprise a plurality of elements, unless the context clearly dictates otherwise. Furthermore, in the description of the present disclosure, it will be further understood that the terms "comprises" and "comprising" specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a plan view schematically illustrating a display device according to one or more embodiments of the present disclosure. Fig. 2 is an enlarged view of the region P shown in fig. 1. Fig. 3A is a sectional view taken along line I-I' of fig. 1. Fig. 3B is a sectional view taken along line II-II' of fig. 2. Fig. 3C is a sectional view taken along line III-III' of fig. 2.

Referring to fig. 1, 2 and 3A to 3C, a display device according to an embodiment of the present disclosure may include a lower substrate 110, thin film transistors Tr1 and Tr2, a lower passivation layer 130, an upper cladding layer 140, an auxiliary electrode 200, a light emitting structure 300, a bank insulating layer 350, an upper substrate 500, and an adhesive layer 600.

The lower substrate 110 may support the thin film transistors Tr1 and Tr2, the auxiliary electrode 200, and the light emitting structure 300. The lower substrate 110 may include an insulating material. For example, the lower substrate 110 may include glass or plastic.

A plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VDD may be disposed on the lower substrate 110. The data line DL may intersect the gate line GL. The power line VDD may be parallel to the gate line GL or the data line DL. For example, the power line VDD may intersect the gate line GL. As used herein, the term "intersect" does not require a physical connection or contact between the intersecting elements. Rather, the elements may intersect one another in an overlapping manner with one or more elements disposed therebetween.

The gate line GL, the data line DL, and the power line VDD may define a pixel region. For example, each pixel region may be at least partially surrounded by the gate line GL, the data line DL, and the power supply line VDD. A circuit for controlling the light emitting structure 300 may be disposed in each pixel region. For example, a selection thin film transistor Tr1, a driving thin film transistor Tr2, and a storage capacitor Cst may be disposed in each pixel region.

The selection thin film transistor Tr1 may turn on/off the driving thin film transistor Tr2 according to a gate signal applied through the gate line GL. The driving thin film transistor Tr2 may supply a driving current to the corresponding light emitting structure 300 according to a signal of the selection thin film transistor Tr 1. For example, the selection thin film transistor Tr1 may have the same structure as the driving thin film transistor Tr 2. The storage capacitor Cst may maintain a signal applied to the selection thin film transistor Tr1 of the driving thin film transistor Tr2 for a predetermined time.

The driving thin film transistor Tr2 may include a semiconductor pattern 210, a gate insulating layer 220, a gate electrode 230, an interlayer insulating layer 240, a source electrode 250, and a drain electrode 260.

The semiconductor pattern 210 may be disposed close to the lower substrate 110. The semiconductor pattern 210 may include a semiconductor material. For example, the semiconductor pattern 210 may include amorphous silicon or polysilicon. For example, the semiconductor pattern 210 may include an oxide semiconductor material such as Indium Gallium Zinc Oxide (IGZO). The semiconductor pattern 210 may include a source region, a drain region, and a channel region. The channel region may be disposed between the source region and the drain region.

The display device according to the embodiment of the present disclosure may further include a buffer layer 120 between the lower substrate 110 and the semiconductor pattern 210. The buffer layer 120 may extend beyond the thin film transistors Tr1 and Tr 2. For example, the buffer layer 120 may cover the entire surface of the lower substrate 110. The buffer layer 120 may include an insulating material. For example, the buffer layer 120 may include silicon oxide.

The gate insulating layer 220 may be disposed on the semiconductor pattern 210. The gate insulating layer 220 may overlap a channel region of the semiconductor pattern 210. The gate insulating layer 220 may include an insulating material. For example, the gate insulating layer 220 may include silicon oxide and/or silicon nitride. The gate insulating layer 220 may include a high-K material. For example, the gate insulating layer 220 may include hafnium oxide (HfO) or titanium oxide (TiO). The gate insulating layer 220 may have a multi-layered structure.

The gate electrode 230 may be disposed on the gate insulating layer 220. The gate electrode 230 may overlap with a channel region of the semiconductor pattern 210. For example, the gate insulating layer 220 may include a side surface continuous with a side surface of the gate electrode 230. The gate electrode 230 may include a conductive material. For example, the gate electrode 230 may include a metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), and tungsten (W).

A gate insulating layer 240 may be disposed on the semiconductor pattern 210 and the gate electrode 230. The gate insulating layer 240 may extend beyond the semiconductor pattern 210. The gate insulating layer 220 and the gate electrode 230 may be completely surrounded by the interlayer insulating layer 240. For example, the interlayer insulating layer 240 may be in direct contact with the buffer layer 120 at the outer edge of the semiconductor pattern 210. The interlayer insulating layer 240 may include an insulating material. For example, the interlayer insulating layer 240 may include silicon oxide and/or silicon nitride. The interlayer insulating layer 240 may have a multi-layer structure.

The source electrode 250 and the drain electrode 260 may be disposed on the interlayer insulating layer 240. The drain electrode 260 may be spaced apart from the source electrode 250. The source electrode 250 may be electrically connected to the source region of the semiconductor pattern 210. The drain electrode 260 may be electrically connected to the drain region of the semiconductor pattern 210. For example, contact holes may extend through the interlayer insulating layer 240 to expose source and drain regions of the semiconductor pattern 210, and the source and drain

electrodes

250 and 260 may extend through the contact holes to contact the source and drain regions, respectively.

The source electrode 250 and the drain electrode 260 may include a conductive material. For example, the source electrode 250 and the drain electrode 260 may include a metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), and tungsten (W). The drain electrode 260 may include the same material as the source electrode 250. For example, the drain electrode 260 may be formed by the same etching process as the source electrode 250. The gate electrode 230 may include a material different from that of the source electrode 250 and the drain electrode 260.

The display device according to the embodiment of the present disclosure is described in the case where the semiconductor pattern 210 of each of the thin film transistors Tr1 and Tr2 is disposed close to the lower substrate 110. However, in the display device according to another embodiment of the present disclosure, the semiconductor pattern 210 of each of the thin film transistors Tr1 and Tr2 may be disposed between the gate electrode 230 and the source/

drain electrodes

250 and 260.

The auxiliary electrode 200 may be disposed on the lower substrate 110. The auxiliary electrode 200 may be spaced apart from the thin film transistors Tr1 and Tr 2. The auxiliary electrode 200 may be parallel to the gate line GL and/or the data line DL. For example, as shown in fig. 1, the auxiliary electrode 200 may be parallel to the data line DL. The auxiliary electrode 200 may be disposed outside the data line DL. That is, as shown, the data line DL may be between the auxiliary electrode 200 and the thin film transistor Tr 1.

The auxiliary electrode 200 may include the same material as one of the conductive materials constituting the thin film transistors Tr1 and Tr 2. For example, the auxiliary electrode 200 may be formed using a process of forming the thin film transistors Tr1 and Tr 2. The auxiliary electrode 200 may include the same material as one of the gate electrode 230, the source electrode 250, and the drain electrode 260 of the thin film transistors Tr1 and Tr 2. For example, the auxiliary electrode 200 may include the same material as the source and drain

electrodes

250 and 260 of the thin film transistors Tr1 and Tr 2. The auxiliary electrode 200 may be disposed on the interlayer insulating layer 240.

The lower passivation layer 130 may be disposed on the thin film transistors Tr1 and Tr2 and the auxiliary electrode 200. The lower passivation layer 130 may include an insulating material. For example, the lower passivation layer 130 may include silicon oxide and/or silicon nitride. The lower passivation layer 130 may have a multi-layered structure.

The first contact hole CH1 and the lower through hole 130h may be formed through the lower passivation layer 130.

As shown in fig. 3A, the first contact hole CH1 of the lower passivation layer 130 may overlap the driving thin film transistor Tr 2. For example, the first contact hole CH1 of the lower passivation layer 130 may expose the drain electrode 260 of the driving thin film transistor Tr 2.

As shown in fig. 3B, the lower through hole 130h of the lower passivation layer 130 may overlap the auxiliary electrode 200. The auxiliary electrode 200 may be exposed by the lower through hole 130h of the lower passivation layer 130. The lower passivation layer 130 may cover the edge of the auxiliary electrode 200.

An upper cladding layer 140 may be disposed on the lower passivation layer 130. The upper clad layer 140 may remove a thickness difference caused by the thin film transistors Tr1 and Tr 2. The upper cladding layer 140 may include an organic insulating material. For example, upcoating 140 may comprise a thermoset type resin.

The light emitting structure 300 may implement a specific color. For example, the light emitting structure may include a lower electrode 310, a light emitting layer 320, and an upper electrode 330, which are sequentially stacked.

The light emitting structure 300 may be controlled by the thin film transistors Tr1 and Tr 2. For example, the lower electrode 310 of the light emitting structure 300 may be electrically connected to the drain electrode 260 of the driving thin film transistor Tr 2. The light emitting structure 300 may be disposed on the upper cladding layer 140. For example, as shown in fig. 3A, the second contact hole CH2 may be formed through the upper cladding layer 140, and the second contact hole CH2 may be aligned with the first contact hole CH1 of the lower passivation layer 130. The lower electrode 310 may extend into the first and second contact holes CH1 and CH2, and may contact side surfaces of the first and second contact holes CH1 and CH 2. As shown in fig. 3A, the upper cladding layer 140 may form side surfaces of the first and second contact holes CH1 and CH 2.

The lower electrode 310 may include a conductive material. The lower electrode 310 may include a material having high reflectivity. For example, the lower electrode 310 may include a metal such as aluminum (Al) and silver (Ag). The lower electrode 310 may have a multi-layered structure. For example, the lower electrode 310 may include the following structure: in this structure, a reflective electrode including a material having a high reflectance is disposed between transparent electrodes including a transparent conductive material such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).

The light emitting layer 320 may generate light having a luminance corresponding to a voltage difference between the lower electrode 310 and the upper electrode 330. For example, the light emitting layer 320 may include an Emitting Material Layer (EML) having an emitting material. The emissive material may comprise an organic material, an inorganic material, or a hybrid material. For example, the display device according to the embodiment of the present disclosure may be an organic light emitting display device having the organic light emitting layer 320.

In order to improve the light emitting efficiency, the light emitting layer 320 may have a multi-layered structure. For example, the light emitting layer 320 may further include at least one of a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL).

The upper electrode 330 may include a conductive material. The upper electrode 330 may include a different material than the lower electrode 310. For example, the upper electrode 330 may include only a transparent material. Accordingly, in the display device according to the embodiment of the present disclosure, light generated by the light emitting layer 320 may be emitted to the outside through the upper electrode 330.

The bank insulating layer 350 may insulate each lower electrode 310 from an adjacent pixel region. For example, the bank insulating layer 350 may cover one or more edges of the lower electrode 310. A pixel penetration hole 351h may be formed through the bank insulating layer 350, and the pixel penetration hole 351h may expose a portion of the lower electrode 310. The light emitting layer 320 and the upper electrode 330 may be stacked on the surface of the lower electrode 310 exposed by the pixel penetration hole 351h of the bank insulating layer 350.

A first bank penetration hole 352h and a second bank penetration hole 353h may also be formed through the bank insulating layer 350. As shown in fig. 2 and 3B, the first and second bank penetration holes 352h and 353h may overlap the auxiliary electrode 200. The second bank penetration hole 353h may be spaced apart from the first bank penetration hole 352 h. As shown in fig. 2, a plurality of second bank penetration holes 353h may be provided.

The first bank penetration hole 352h may partially expose a side surface of the lower penetration hole 130 h. For example, the first bank penetration hole 352h may include a side surface overlapping the upper clad layer 140 and a side surface disposed on the lower penetration hole 130 h. The first bank penetration hole 352h may include a side surface intersecting with a side surface of the lower penetration hole 130 h. For example, as shown in the plan view of fig. 2, the first bank penetration hole 352h may partially overlap the lower penetration hole 130h such that a side surface of the first bank penetration hole 352h includes a portion overlapping the lower penetration hole 130h and other portions not overlapping the lower penetration hole 130 h.

An end portion of the bank insulating layer 350 disposed near a side surface of the first bank penetration hole 352h disposed to overlap the lower penetration hole 130h may overlap the auxiliary electrode 200 and may not overlap the lower passivation layer 130. That is, as shown in fig. 3B and 3C, the first bank penetration hole 352h may extend between the first side of the bank insulating layer 350 and the second side of the bank insulating layer 350, as shown by a bracket indicating the first bank penetration hole 352 h. As shown in fig. 3C, an end portion of the bank insulating layer 350 forming a second side (e.g., right side) of the bank insulating layer 350 overlaps the auxiliary electrode 200 in the region of the lower through hole 130h in which the auxiliary electrode 200 is not covered by the lower passivation layer 130. An end portion of the bank insulating layer 350 disposed near a side surface of the first bank penetration hole 352h disposed to overlap the lower penetration hole 130h may include an undercut region UC on a lower surface of the bank insulating layer 350 facing the auxiliary electrode 200. The lower surface of the bank insulating layer 350 may be exposed through the lower passivation layer 130 in the undercut region UC.

The planar shape of the first bank penetration hole 352h may be the same as that of the lower penetration hole 130 h. The planar size of the first bank penetration hole 352h may be the same as the planar size of the lower penetration hole 130h, however, as shown in fig. 2, the first bank penetration hole 352h may be positioned in an offset manner with respect to the lower penetration hole 130h such that the first bank penetration hole 352h only partially overlaps the lower penetration hole 130 h. For example, the center of the first bank penetration hole 352h is different from the center of the lower penetration hole 130 h. The first bank penetration hole 352h may be a polygon of the same type as the planar shape of the lower penetration hole 130 h. For example, the first penetration hole 352h and the lower penetration hole 130h may each have a rectangular shape.

As shown in fig. 2, the second bank penetration hole 353h may overlap the lower penetration hole 130 h. The side surface of the second bank penetration hole 353h may be disposed to overlap the lower penetration hole 130 h. The second bank penetration hole 353h may partially penetrate the undercut region UC formed by the first bank penetration hole 352h, such that the undercut region UC is partitioned into undercuts UC' by the second bank penetration hole 353h (fig. 3B). A structure 355 including a portion of the bank insulating layer 150 and layers formed thereon is formed between the first bank penetration hole 352h and the second bank penetration hole 353 h. The horizontal distance of the undercut region UC formed by the first bank penetration hole 353h may be reduced due to the second bank penetration hole 352h, so that the undercut region UC includes only the undercut portion UC' in the region adjacent to the second bank penetration hole.

As shown in fig. 2, the planar size of the second bank penetration hole 353h may be smaller than the planar size of the first bank penetration hole 352 h. The plane size of the second bank penetration hole 353h may be smaller than the plane size of the lower penetration hole 130 h. For example, the display device according to the embodiment of the present disclosure may include a plurality of second bank penetration holes 353h disposed adjacent to one or more side surfaces of the first bank penetration hole 352 h. The second bank penetration hole 353h may have the same type of polygon as the planar shape of the first bank penetration hole 353 h. For example, the second bank penetration hole 353h may have a rectangular shape.

The light emitting layer 320 and the upper electrode 330 may extend onto the bank insulating layer 350. The light emitting layer 320 and the upper electrode 330 may extend onto the auxiliary electrode 200 through the first bank penetration hole 352 h.

The light emitting layer 320 may be cut off in the undercut region UC due to the undercut of the bank insulating layer 350, so that the light emitting layer 320 is discontinuous in the undercut region UC between the bank insulating layer 350 and the auxiliary electrode 200. The lower surface of the bank insulating layer 350 in the undercut region UC may not be covered with the light emitting layer 320. In the undercut region UC, the light emitting layer 320 may not be formed on the surface of the auxiliary electrode 200 overlapping the bank insulating layer 350. The auxiliary electrode 200 overlapping the bank insulating layer 350 may be exposed through the light emitting layer 320 in the undercut region UC.

The upper electrode 330 may extend along the light emitting layer 320. The upper electrode 330 may have better step coverage than the light emitting layer 320. For example, the upper electrode 330 may extend to the lower surface of the bank insulating layer 350 in the undercut region UC. In the undercut region UC, the upper electrode 330 may cover a surface of the auxiliary electrode 200 overlapping the bank insulating layer 350. The surface of the auxiliary electrode 200 exposed by the light emitting layer 320 may be covered by the upper electrode 330. The auxiliary electrode 200 may be connected to the upper electrode 330 due to an undercut region UC where the upper electrode 330 contacts the auxiliary electrode 200.

The upper substrate 500 may be disposed on the light emitting structure 300. The upper substrate 500 may be disposed opposite to the lower substrate 110. The upper substrate 500 may include an insulating material. The upper substrate 500 may include a transparent material. For example, the upper substrate 500 may include glass or plastic.

The adhesive layer 600 may be disposed between the lower substrate 110 and the upper substrate 500. The upper substrate 500 may be coupled to the lower substrate 110 through an adhesive layer 600. The adhesive layer 600 may include an adhesive material. For example, the adhesive layer 600 may include a curable material. For example, the adhesive layer 600 may include a thermosetting resin.

The adhesive layer 600 may fill a space between the lower substrate 110 and the upper substrate 500. The adhesive layer 600 may directly contact the upper electrode 330 on the auxiliary electrode 200 through the lower penetration hole 130h and the first bank penetration hole 352 h. The adhesive layer 600 may extend into the undercut region UC formed by the bank insulating layer 350. The adhesive layer 600 may extend into the undercut region UC through the second bank penetration hole 353 h.

In the display device according to the embodiment of the present disclosure, the second bank penetration hole 353h may be disposed in the undercut region UC formed by the first bank penetration hole 352 h. Accordingly, in the display device according to the embodiment of the present disclosure, the horizontal distance of the undercut region UC may be partially reduced due to the second bank penetration hole 353 h. Accordingly, in the display device according to the embodiment of the present disclosure, the adhesive layer 600 for attaching the upper substrate 500 to the lower substrate 110 may relatively easily fill the undercut region UC. Further, in the display device according to the embodiment of the present disclosure, since the adhesive layer 600 may flow to the undercut region UC through the first and second bank penetration holes 352h and 353h, an inflow path of the adhesive layer 600 into the undercut region UC may be diversified, so that the adhesive layer 600 may quickly fill the undercut region UC. Accordingly, in the display device according to the embodiment of the present disclosure, the generation of voids caused by the adhesive layer 600 may be prevented or reduced.

The display device according to the embodiment of the present disclosure may further include an upper passivation layer 400 between the light emitting structure 300 and the adhesive layer 600. The upper passivation layer 400 may prevent or otherwise reduce the influence of external impact and moisture on the thin film transistors Tr1 and Tr2 and the light emitting structure 300. The upper passivation layer 400 may include an insulating material. For example, the upper passivation layer 400 may include silicon oxide and/or silicon nitride. The upper passivation insulating layer 400 may have a multi-layered structure.

A display device according to an embodiment of the present disclosure may be described as including a plurality of second bank penetration holes 353h disposed along or adjacent to one or more side surfaces of the first bank penetration hole 352 h. However, as shown in fig. 4, a display device according to another embodiment of the present disclosure may include a single second bank penetration 353h extending along or adjacent to one or more side surfaces of the first bank penetration 352 h. As shown, the planar shape of the second bank penetration hole 353h may be different from the planar shape of the first bank penetration hole 352 h. The planar shape of the second bank penetration hole 353h may be a polygon of the same type as the planar shape of the first bank penetration hole 352 h.

Accordingly, in the display device according to the embodiment of the present disclosure, since the adhesive layer 600 may rapidly and easily flow into the undercut region UC through the second bank penetration hole 353h, which partially penetrates the undercut region UC formed by the first bank penetration hole 352h of the bank insulating layer 350 in order to connect the auxiliary electrode 200 to the upper electrode 330, due to the adhesive layer 600, the generation of voids at the undercut region UC may be reduced or prevented, and thus, the quality degradation and the luminance unevenness may be reduced or prevented.

The display device according to the embodiment of the present disclosure has been described such that the horizontal distance of the undercut region UC is reduced by the second bank penetration hole 353h of the bank insulating layer 350 overlapping the lower penetration hole 130 h. However, as shown in fig. 5 and 6, in a display device according to another embodiment of the present disclosure, the circumference of the first bank penetration hole 352h of the bank insulating layer 350 arranged to overlap the lower penetration hole 130h may have one or more protrusions 353 p. The protrusions 353p extend the periphery of the first bank penetration hole 352h outward beyond the adjacent peripheral portion, so that the periphery of the first bank penetration hole 352h has a stepped shape with an alternating arrangement of protrusions 353p and non-protrusions. The side surface of the lower penetration hole 130h adjacent to the periphery of the first bank penetration hole 352h having the protrusion 353p may have a linear shape. Accordingly, in the display device according to the embodiment of the present disclosure, the undercut region UC formed by the first bank penetration hole 352h of the bank insulating layer 350 may include regions having a relatively short horizontal length and regions having a relatively long horizontal length, which are repeatedly or alternately arranged. That is, in the display device according to one or more embodiments of the present disclosure, since the periphery of the first bank penetration hole 352h may have a step shape, the adhesive layer 600 may flow into a region of the undercut region UC having a relatively long horizontal length through a region of the undercut region UC having a relatively short horizontal length. Thereby, in the display device according to another embodiment of the present disclosure, quality degradation and luminance unevenness due to the unfilled area of the adhesive layer 600 may be prevented.

Thus, the display device according to the embodiment of the present disclosure may include the undercut region in which the region having the relatively short horizontal length is repeatedly arranged, so that the adhesive layer for attaching the upper substrate to the lower substrate may easily flow into the undercut region. Accordingly, in the display device according to the embodiment of the present disclosure, the generation of voids caused by the adhesive layer in the undercut region may be prevented or reduced. Thus, in the display device according to the embodiment of the present disclosure, the quality degradation and the luminance unevenness due to the unfilled region of the adhesive layer can be effectively prevented or reduced.

The above embodiments may be combined to provide further embodiments.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

1. A display device, comprising:

an auxiliary electrode on the first substrate;

a passivation layer on the auxiliary electrode;

a first hole extending through the passivation layer and overlapping at least a portion of the auxiliary electrode;

a bank insulating layer on the passivation layer;

a first bank layer hole extending through the bank insulating layer and partially overlapping the first hole;

a second bank hole extending through the bank insulating layer and overlapping the first hole, and spaced apart from the first bank hole; and

an upper cladding layer between the passivation layer and the bank insulating layer.

2. The display device according to claim 1, wherein a side surface of the second bank hole overlaps the first hole.

3. The display device according to claim 1, wherein a planar size of the second bank layer hole is smaller than a planar size of the first bank layer hole.

4. The display device of claim 3, wherein the second bank layer aperture is positioned adjacent to a side surface of the first bank layer aperture.

5. The display device according to claim 1, wherein a planar shape of the second bank hole is a polygon of the same type as a planar shape of the first bank hole.

6. The display device according to claim 5, wherein a planar shape of the first bank layer hole and the second bank layer hole is a rectangular shape.

7. The display device of claim 1, wherein the first bank layer aperture has a rectangular shape and the second bank layer aperture is positioned adjacent to a first side and a second side of the first bank layer aperture.

8. The apparatus of claim 1, further comprising:

a second substrate on the bank insulating layer; and

an adhesive layer between the bank insulating layer and the second substrate,

wherein the adhesive layer extends between the auxiliary electrode and the bank insulating layer through the first bank layer hole and the second bank layer hole.

9. The apparatus of claim 1, further comprising:

a light emitting layer on a first portion of the auxiliary electrode in the first hole; and

a second electrode on the light emitting layer, the second electrode contacting a second portion of the auxiliary electrode in the first hole.

10. The apparatus of claim 9, wherein the light emitting layer is discontinuous in an undercut region between the bank insulating layer and the auxiliary electrode.

11. A display device, comprising:

an auxiliary electrode on the substrate;

a passivation layer on the auxiliary electrode;

a first hole extending through the passivation layer and exposing the auxiliary electrode;

a bank insulating layer on the passivation layer; and

a second hole extending through the bank insulating layer and overlapping the auxiliary electrode,

wherein a perimeter of the second aperture includes a portion that overlaps the first aperture,

wherein the portion of the perimeter of the second aperture that overlaps the first aperture comprises one or more protrusions that extend the perimeter of the second aperture outwardly relative to adjacent portions of the perimeter such that the perimeter of the second aperture has a stepped shape with an alternating arrangement of protrusions and non-protrusions.

12. The display device of claim 11, wherein the first aperture comprises a side surface adjacent to the one or more protrusions of the perimeter of the second aperture, and

wherein the side surface of the first aperture extends in a straight line adjacent to the one or more protrusions.

13. The display device according to claim 11, further comprising a thin film transistor between the substrate and the passivation layer,

wherein the thin film transistor is spaced apart from the auxiliary electrode, an

Wherein the auxiliary electrode comprises the same material as one of a gate electrode, a source electrode, and a drain electrode of the thin film crystal.

14. The display device according to claim 13, further comprising:

a first electrode coupled to a drain electrode of the thin film transistor;

a light emitting layer on the first electrode; and

a second electrode on the light emitting layer, the second electrode contacting the auxiliary electrode in the first hole.

15. A display device, comprising:

a first substrate;

an auxiliary electrode on the first substrate;

a passivation layer on the auxiliary electrode, the auxiliary electrode being exposed through a first hole extending through the passivation layer;

a bank insulating layer on the passivation layer;

a second hole extending through the bank insulating layer over a first portion of the auxiliary electrode;

an undercut region between the bank insulating layer and a second portion of the auxiliary electrode, the bank insulating layer having a portion overlapping the second portion of the auxiliary electrode in the undercut region; and

a third hole extending through the bank insulating layer in the undercut region.

16. The display device of claim 15, further comprising a plurality of third holes extending through the bank insulating layer in the undercut region.

17. The display device of claim 16, wherein a first portion of the plurality of third apertures is disposed adjacent a first side of the second aperture and a second portion of the plurality of third apertures is disposed adjacent a second side of the second aperture.

18. The display device according to claim 15, further comprising:

a second substrate on the bank insulating layer; and

an adhesive layer between the bank insulating layer and the second substrate, the adhesive layer extending into the undercut region through the second hole and the third hole.

19. The display device according to claim 15, further comprising:

a transistor on the first substrate;

a first electrode coupled to the transistor;

a light emitting layer on the first electrode; and

a second electrode on the light emitting layer, the second electrode contacting the second portion of the auxiliary electrode in the undercut region.

20. The display device of claim 19, wherein the light emitting layer is discontinuous in the undercut region.