CN111223456B

CN111223456B - Grid drive circuit of display panel, display panel and display device

Info

Publication number: CN111223456B
Application number: CN201911075898.8A
Authority: CN
Inventors: 奚苏萍
Original assignee: Suzhou China Star Optoelectronics Technology Co Ltd
Current assignee: Suzhou China Star Optoelectronics Technology Co Ltd
Priority date: 2019-11-06
Filing date: 2019-11-06
Publication date: 2021-06-22
Anticipated expiration: 2039-11-06
Also published as: CN111223456A

Abstract

The invention discloses a grid driving circuit of a display panel, the display panel and a display device, wherein the grid driving circuit comprises a clock signal wire for providing a clock signal; a plurality of cascaded gate driving units receiving the clock signal, each stage of the gate driving units being configured to drive one scan line; a reset signal line for providing a reset signal to the gate driving unit; the electrostatic protection device is connected with the reset signal line at one end and connected to the discharge circuit of the display panel at the other end, and releases static in the reset signal line to the discharge circuit.

Description

Grid drive circuit of display panel, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a gate driving circuit of a display panel, the display panel and a display device.

Background

With the development and progress of science and technology, flat panel displays have become mainstream products of displays due to thin bodies, power saving, low radiation and other hot spots, and are widely used. The flat panel display includes a Thin Film Transistor-Liquid Crystal display (TFT-LCD), an Organic Light-Emitting Diode (OLED) display, and the like. The GOA (Gate Driver on Array) technology is a driving method that can use the Array process of the liquid crystal display panel to fabricate the Gate driving circuit on the Array substrate to scan the Gate line by line. The GOA technology can reduce the welding (bonding) process of an external IC, has the opportunity of improving the productivity and reducing the product cost, and can ensure that the liquid crystal display panel is more suitable for manufacturing narrow-frame or frameless display products.

In the GOA, because signal lines are numerous and densely arranged, charges are easily accumulated, when the charges are accumulated to a certain degree, the grid driving circuit is easy to have the risk of explosion injury, and the display abnormality of the panel is caused.

Disclosure of Invention

The invention provides a gate driving circuit of a display panel, the display panel and a display device, which improve electrostatic protection capability.

The invention provides a display panel grid drive circuit, comprising:

a clock signal line for supplying a clock signal; a plurality of cascaded gate driving units receiving the clock signal, each stage of the gate driving units being configured to drive one scan line; a reset signal line for providing a reset signal to the gate driving unit, and an electrostatic discharge protection device configured to discharge static electricity in the reset signal line; one end of the electrostatic protection device is connected with the reset signal line, and the other end of the electrostatic protection device is connected to a discharge circuit of the display panel.

Optionally, the plurality of cascaded gate driving units are divided into a start-stage gate driving unit and a non-start-stage gate driving unit, and the non-start-stage gate driving unit includes a reset switch connected to the reset signal line; the gate drive unit without the reset switch is the initial gate drive unit; the number of the electrostatic protection devices is at least one, and the electrostatic protection devices are connected with the reset signal line at the positions corresponding to the initial stage gate drive units.

Optionally, there are at least two start-stage gate driving units, and the number of the electrostatic protection devices is the same as that of the start-stage gate driving units; the plurality of electrostatic protection devices are respectively connected with the reset signal line at the position corresponding to each initial stage gate drive unit in a one-to-one correspondence mode.

Optionally, the position of the reset switch in the start-stage gate driving unit corresponding to the non-start-stage gate driving unit is a blank region, and the electrostatic protection device is correspondingly disposed in the blank region of the start-stage gate driving unit.

Optionally, there are eight clock signal lines; the first eight stages of the gate driving units are the initial stage gate driving units, and the gate driving units after the ninth stage and the ninth stage are the non-initial stage gate driving units.

Optionally, the electrostatic protection device includes a first thin film transistor and a second thin film transistor, and a drain of the first thin film transistor is connected to a source of the second thin film transistor; the source electrode of the first thin film transistor is connected with the drain electrode of the second thin film transistor; the drain electrode and the grid electrode of the first thin film transistor are connected with the reset signal line; and the source electrode and the grid electrode of the second thin film transistor are connected with the discharge circuit.

Optionally, the drain of the first thin film transistor is connected to the reset signal line through a via hole; the grid electrode of the second thin film transistor is connected to the discharge line through a through hole.

Optionally, the discharge line is a common signal line.

The invention also discloses a display panel comprising the gate driving circuit of any display panel.

The invention also discloses a display device which comprises the display panel.

For the scheme that does not have electrostatic protection device, this application is through increasing electrostatic protection device on initial stage gate drive unit, connects between reset signal line and discharge circuit, improves reset signal's electrostatic protection ability to effectively reduce the fried risk of hindering of reset signal line, improve GOA's stability.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a schematic diagram of an exemplary circuit block of a gate driving unit according to an embodiment of the present invention;

FIG. 2 is a diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 3 is a schematic diagram of an initial gate driving circuit without an electrostatic discharge protection device according to an embodiment of the present invention;

FIG. 4 is an enlarged schematic view of the area of the electrostatic protection device of FIG. 1;

FIG. 5 is a schematic diagram of an equivalent principle of an electrostatic discharge protection apparatus according to an embodiment of the present invention;

FIG. 6 is a comparative graph of discharge current after an ESD protection device is added in an embodiment of the present invention;

FIG. 7 is a schematic diagram of a film structure according to an embodiment of the present invention;

FIG. 8 is a schematic view of a via connection according to an embodiment of the present invention;

FIG. 9 is a timing diagram of the signals of the gate driving circuit of the present invention;

FIG. 10 is a diagram of a display panel according to another embodiment of the present invention;

fig. 11 is a schematic diagram of a display device according to another embodiment of the invention.

100, a gate driving circuit; 110. a gate driving unit; 111. a pull-up control module; 112. a pull-up module; 113. a pull-down maintenance module; 114. a pull-down module; 115. a signal transmission module; 116. a boost capacitor; 117. a reset switch; 118. a start-level gate driving unit; 119. a non-initial stage gate driving unit; 120. a reset signal line; 121. a blank region; 130. an electrostatic protection device; 140. a discharge line; 150. a via hole; 160. a transparent conductive circuit; 170. a clock signal line; 200. a display panel; 300. a display device; 400. a substrate; 410. a first metal layer; 420. a gate insulating layer; 430. an active layer; 440. doping layer; 450. a second metal layer; 460. and a passivation layer.

Detailed Description

Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present application. This application may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, the term "multistage" means two or more stages unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two-stage element can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of the two-stage element. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The invention will be further elucidated with reference to the drawings and alternative embodiments.

Static electricity refers to excess or insufficient relative static charges on the surface of an object, and is an expression of electric energy, and unbalanced charges form a measurable electric field, namely an electrostatic field, which can influence other objects within a certain distance to enable the objects to be charged inductively. Electrostatic discharge (ESD) is the charge transfer of an object with different electrostatic potential. The following measures against electrostatic protection are available: static dissipation and grounding/static neutralization/electrostatic shielding and grounding. The grounding is a measure of electrostatic protection, and usually the largest area metal in the circuit (or panel) is used as the ground, and is directly connected under the allowable condition. The purpose of ESD protection is to discharge static electricity (similar to grounding effect), which may damage other signal lines if connected.

The Gate Driver On Array (GOA) is one of the mainstream driving methods, and the Gate line scan driving signal circuit is fabricated On the Array substrate by using the Array substrate process in the existing thin film transistor liquid crystal display to realize the line-by-line scan driving of the scan lines.

The gate driving circuit includes a plurality of gate driving units, and fig. 1 is a schematic diagram of an exemplary circuit module of a gate driving unit. Each stage of the gate driving unit includes a pull-up control module (pull-up control circuit)111, a pull-up module (pull-up circuit)112, a pull-down maintaining module (pull-down circuit) 113, a pull-down circuit 114, a signal transmission module (signal transmission circuit)115, and a boost capacitor (boost capacitor) 116, the pull-up control module 111 receives the stage transfer signal (STn-4) and the scan signal (Gn-4) of the gate driving unit 110 of the nth-4 stage of the upper stage, and electrically connected to the first node (Qn), the pull-up module 112 is connected to the clock signal (CKn) and electrically connected to the first node (Qn), the signal transmission module 115 outputs a stage transmission signal (STn), and the pull-down maintaining module 112 accesses the scan signal (Gn) and the low potential signal (Vss) and is electrically connected to the first node (Qn); the pull-down module 114 receives a scan signal (Gn +4) of the gate driving unit 110 of the nth +4 th stage of the lower four stages, where n is a positive integer greater than 4.

In the multi-stage gate driving unit, the first-stage to nth-stage gate driving units are initial-stage gate driving units, the (N + 1) th-stage gate driving unit and the subsequent gate driving units are non-initial-stage gate driving units, the non-initial-stage gate driving units are connected with thin film transistors, the thin film transistors are connected with reset signal lines and used for driving the pull-down maintaining module to reset, and other circuits are completely consistent with the initial-stage gate driving units. Therefore, the initial stage gate driving unit has a blank region corresponding to the position of the thin film transistor. The number of N is consistent with the number of clock signal lines, and the clock signal lines are connected to a time sequence driving circuit of the display panel.

Referring to fig. 2, an embodiment of the invention discloses a gate driving circuit 100, which includes 8 clock signal lines 170, which are CK1, CK2, and CK3 … … CK8 from left to right; the first eight stages of the gate driving units 110 are initial stage gate driving units 118, and the gate driving units 110 after the ninth stage and the ninth stage are non-initial stage gate driving units 119. The first gate driving unit 110 is an eighth-stage driving unit, the first eight-stage driving units are all initial-stage gate driving units 118, the ninth-stage driving unit is a non-initial-stage gate driving unit 119, and the access reset switch 117 is connected to the reset signal line 120 to provide a reset signal for the gate driving unit 110. The gate driving unit 110 is configured to drive one scan line per stage.

Fig. 2 is a cross-sectional view of two cascaded gate driving units as an example, where the first gate driving unit is an initial gate driving unit 118, the second gate driving unit is a non-initial gate driving unit 119, a reset switch 117 is present in the non-initial gate driving unit 119 for connecting to a reset signal line, the corresponding initial gate driving unit 118 is not provided with the reset switch 117, the initial gate driving unit 118 is provided with an electrostatic protection device 130, one end of the electrostatic protection device 130 is connected to the reset signal line 120, and the other end is connected to a discharge line 140 of the display panel. Only the initial stage gate driving unit 118 is provided with the esd protection device 130, one esd protection device 130 may be provided in a plurality of initial stage gate driving units 118, or a plurality of esd protection devices 130 may be provided in a plurality of initial stage gate driving units 118, but the number of the esd protection devices 130 does not exceed the number of the initial stage gate driving units 118, so that the circuit design cost can be reduced, and the static electricity in the reset signal line 120 can be removed through the esd protection device 130.

Of course, the present invention is not limited to the gate driver circuit applied to the clock signal line of 8clk, and may be applied to the gate driver circuit of the clock signal line of 3clk, 4clk, or the like.

Because signal lines in the GOA circuit are numerous and densely arranged, the circuit has both direct current signals and alternating current signals, charges are easy to accumulate, and when the charges are accumulated to a certain degree, a large potential difference is generated, so that the accumulated charges have enough energy to leave the original position and neutralize the charges with opposite polarities, and a large current is generated, and the risk of explosion injury can be caused. The reset signal line 120 is easy to generate charge accumulation, the scheme connects the reset signal line 120 to the electrostatic protection device 130, and connects the static in the reset signal line to the discharge circuit 140 of the display panel through the electrostatic protection device 130, so that the static in the reset signal line 120 is released, the risk of electrostatic explosion of the reset signal line 120 is effectively reduced, and the stability of the GOA circuit is improved.

The discharge line 140 may be a common signal line, which provides a reference voltage for the display panel, and the electrostatic discharge protection device 130 is connected to the reset signal line 120 and the common signal line to remove static electricity generated in the electrostatic discharge protection device 130. The common signal line is closer to the gate driving unit 110, and the wiring is more convenient. In addition, the discharge line 140 may be a ground line or other lines as long as the normal operation of the GOA driving circuit is not affected.

Referring to fig. 2 and 3, the position of the reset switch in the start-stage gate driving unit corresponding to the non-start-stage gate driving unit is a blank region, and the esd protection device is correspondingly disposed in the blank region of the start-stage gate driving unit. The relative position of the esd protection device 130 and the corresponding start-stage gate driving unit corresponds to the position of the reset switch 117 in the non-start-stage gate driving unit. The position of the reset switch 117 corresponds to that of the electrostatic protection device 130 in the gate driving unit, when the initial gate driving unit is not connected to the electrostatic protection device 130, the area corresponding to the position of the reset switch 117 in the non-initial gate driving unit is a blank area, the electrostatic protection device 130 is connected to the blank area, the blank area is well utilized, the wiring design of other adjacent elements is not required to be changed, the wiring is more convenient, the space can be saved while the static electricity in the reset signal line 120 is ensured to be removed, and the design of the narrow frame of the display panel is more facilitated.

Each of the initial stage gate driving units 118 is correspondingly provided with one esd protection device 130, that is, the number of the esd protection devices 130 is the same as the number of the initial stage gate driving units 118, and the plurality of esd protection devices 130 are respectively connected to the reset signal line 120 at the position corresponding to each of the initial stage gate driving units 118 in a one-to-one correspondence manner. The one-to-one scheme of disposing the esd protection devices 130 can more effectively utilize all the blank regions 121 of the start gate driving unit 118 without the reset switch 117, and maximally utilize the blank regions 121, so as to provide a path for esd by disposing as many esd protection devices 130 as possible on the premise of avoiding rewiring of adjacent elements.

Referring to the enlarged schematic diagram of the electrostatic discharge protection apparatus shown in fig. 4, the electrostatic discharge protection apparatus 130 is composed of two thin film transistors, including a first thin film transistor T1 and a second thin film transistor T2, and the drain D of the first thin film transistor T1 is connected to the source S of the second thin film transistor T2; the source S of the first TFT T1 is connected to the drain D of the second TFT T2; the drain D and the gate G of the first thin film transistor T1 are connected to the reset signal line 120, wherein the gate G of T1 is located at the same level as the reset signal line 120 and may be directly connected; the drain D of T1 needs to be connected to the reset signal line 120 through the via 150.

Correspondingly, the source S and the gate G of the second thin film transistor T2 are connected to the discharge line 140; the drain D of T2 is located at the same level as the reset signal line 120 and can be directly connected; the gate G of T2 needs to be connected to the discharge line 140 through the via 150.

Referring to fig. 5, the esd protection device is similar to two diodes with their anodes and cathodes interconnected and then connected to the reset signal line 120 and the discharge line 140, respectively.

Referring to FIG. 6, normally, the on voltage of the reset signal line is between + V1 and-V1, no current is generated, and a large current is generated only when the voltage exceeds + V1 and-V1, as shown by the dashed curve. After the ESD protection device is added, the voltage is required to exceed + V2 and-V2, so that the current is large, as shown by the solid curve. Therefore, the release time can be prolonged after the electrostatic protection device is added, the voltage of large current is increased, namely, electrostatic breakdown is effectively avoided, and meanwhile, conduction in the normal working voltage range of the reset signal line is avoided, and misoperation is prevented.

Referring to the schematic diagrams of the display panel shown in fig. 7 and 8, the display panel includes a substrate 400, a first metal layer 410, a gate insulating layer 420, an active layer 430, a doped layer 440, a second metal layer 450, and a passivation layer 460 from bottom to top, wherein the transparent conductive line 160 is located on the passivation layer 460, the reset signal line, the discharge line, the gate G of the first thin film transistor T1, and the gate G of the second thin film transistor T2 are located on the first metal layer 410, the drain D and the source S of the first thin film transistor T1, and the source S and the drain D of the second thin film transistor T2 are located on the second metal layer 450, the electrostatic protection device 130 and the discharge line 140 are connected through the transparent conductive circuit 160 to release the static electricity in the reset signal line 120, and the transparent conductive circuit 160 can be made of Indium Tin Oxide (ITO), and is connected to the discharge line 140 through an ITO trace, so that the manufacturing is simple and convenient. The electrostatic discharge protection device 130 is connected to the reset signal line 120 through a via 150, so as to introduce the static electricity of the electrostatic discharge protection device 130 into the electrostatic discharge protection device 130; the electrostatic protection device 130 is also connected to the transparent conductive trace 160 through the via 150.

Of course, metal wires can be used instead of the transparent conductive traces 160, and the transparent conductive traces 160 can be replaced by metal wires and connected to the discharge lines 140 through the metal wires; the esd protection device 130 is connected to the metal trace through the via 150, and the metal trace is located on the passivation layer. As an alternative material, the use of metal traces may reduce leakage current.

Referring to fig. 9, a timing diagram of the gate driving circuit of the present invention is provided, where the STV signal and the reset signal (reset) are the same signal, but the reset signal line and the STV signal line belong to different signal lines, and when a problem occurs in one of the STV signal line and the reset signal line, the circuit may also have a problem as a whole, which may cause the circuit to fail to operate normally. In one period, the reset signal (reset) is started preferentially, wherein the peak value of the reset signal is 28V, the valley value of the reset signal is-8V, after 2.05H, the first stage gate driving unit signal (CK1) is started periodically, after the first stage driving unit signal is started, the second stage gate driving unit signal (CK2) is started periodically, and then the gate driving unit signals are started periodically in turn.

As another embodiment of the present invention, referring to fig. 10, a display panel 200 is further disclosed, which includes the gate driving circuit 100 of the display panel in any of the embodiments described above, and two gate driving circuits 100 may be respectively located at two sides of the display panel 200.

As another embodiment of the present invention, referring to fig. 11, there is also disclosed a display device 300 including the display panel 200 as described above.

The technical scheme of the invention can be widely applied to flat panel displays such as Thin Film Transistor-Liquid Crystal displays (TFT-LCDs) and Organic Light-Emitting diodes (OLED) displays.

The foregoing is a more detailed description of the invention in connection with specific alternative embodiments, and the practice of the invention should not be construed as limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A gate driving circuit of a display panel, comprising:

a clock signal line providing a clock signal;

a plurality of cascaded gate driving units receiving the clock signal, each stage of the gate driving units being configured to drive one scan line;

a reset signal line for providing a reset signal to the gate driving unit; and

one end of the electrostatic protection device is connected with the reset signal line, the other end of the electrostatic protection device is connected to a discharge circuit of the display panel, and the electrostatic protection device releases static in the reset signal line to the discharge circuit;

the plurality of cascaded gate driving units are divided into a start-stage gate driving unit and a non-start-stage gate driving unit, and the non-start-stage gate driving unit comprises a reset switch connected to the reset signal line; the grid driving unit without the reset switch is the initial grid driving unit;

the number of the electrostatic protection devices is at least one, and the electrostatic protection devices are connected with the reset signal line at positions corresponding to the initial stage gate drive unit.

2. The gate driving circuit of claim 1, wherein the number of the initial gate driving units is at least two, and the number of the esd protection devices is the same as the number of the initial gate driving units;

the plurality of electrostatic protection devices are respectively connected with the reset signal line at the position corresponding to each initial stage gate drive unit in a one-to-one correspondence mode.

3. The gate driving circuit of claim 2, wherein the position of the start-stage gate driving unit corresponding to the reset switch of the non-start-stage gate driving unit is a blank region, and the ESD protection device is correspondingly disposed in the blank region of the start-stage gate driving unit.

4. The gate driving circuit of claim 2, wherein the number of the clock signal lines is eight; the first eight stages of the gate driving units are the initial stage gate driving units, and the gate driving units after the ninth stage and the ninth stage are the non-initial stage gate driving units.

5. The gate driving circuit of claim 1, wherein the electrostatic discharge protection device comprises a first thin film transistor and a second thin film transistor, and a drain of the first thin film transistor is connected to a source of the second thin film transistor; the source electrode of the first thin film transistor is connected with the drain electrode of the second thin film transistor; the drain electrode and the grid electrode of the first thin film transistor are connected with the reset signal line; and the source electrode and the grid electrode of the second thin film transistor are connected with the discharge circuit.

6. The gate driver circuit of a display panel according to claim 5, wherein a drain of the first thin film transistor is connected to the reset signal line through a via hole; the grid electrode of the second thin film transistor is connected to the discharge line through a through hole.

7. The gate driving circuit of claim 1, wherein the discharge line is a common signal line.

8. A display panel comprising the gate driver circuit of the display panel according to any one of claims 1 to 7.

9. A display device characterized by comprising the display panel according to claim 8.