CN103227173B - Array base palte and manufacture method, display unit - Google Patents
Array base palte and manufacture method, display unit Download PDFInfo
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- CN103227173B CN103227173B CN201310123359.3A CN201310123359A CN103227173B CN 103227173 B CN103227173 B CN 103227173B CN 201310123359 A CN201310123359 A CN 201310123359A CN 103227173 B CN103227173 B CN 103227173B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
Abstract
The invention provides a kind of array base palte and manufacture method, display unit, belong to Display Technique field.Wherein, described array base palte is formed connect low level current potential the first conductive pattern and data carry signal STV holding wire with the second conductive pattern of layer, the insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, wherein, the position of corresponding described second conductive pattern of described STV holding wire is formed towards the conductive tip of described second conductive pattern.Technical scheme of the present invention can when not affecting display effect, the electrostatic effectively release STV holding wire accumulated.
Description
Technical field
The present invention relates to Display Technique field, refer to a kind of array base palte and manufacture method, display unit especially.
Background technology
Along with Thin Film Transistor-LCD (Thinfilmtransistorliquidcrystaldisplay, TFTLCD) development of industry, the competition of TFTLCD product, each producer is all by employing new technology the cost reducing product, thus improve its product competitiveness commercially, array base palte row cutting (GateDriveronArray, GOA) technology is exactly the Typical Representative of these new technologies.
GOA technology is integrated on array (Array) substrate by grid (Gate) switching circuit, thus grid-driving integrated circuit (GateDriverIC) part can be saved, the object reducing product cost can be reached from material cost and processing step two aspects.STV(data carry signal) holding wire is only connected with the first row (or first few lines) GOA unit due to its cabling, as other cabling, electric charge cannot be spread once produce electrostatic in STV holding wire, as comparatively large then easy in first GOA unit place outburst in assembled electric charge, cause associated electrical bad.
Existing STV electrostatic prevention structure accessed capacitor before STV input point, and static guiding is walked by the collapse electric current produced utilize high voltage in technical process under, as shown in Figure 1, this capacitor by formed STV holding wire grid metal level, form V
sSthe source and drain metal level of holding wire and gate insulation layer composition.But there is the characteristic of stored charge due to capacitor, and this characteristic produces signal attenuation under causing the situation normally worked at cabling, finally cause abnormal show (Abnormaldisplay).
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and manufacture method, display unit, can when not affecting display effect, the electrostatic effectively release STV holding wire accumulated.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
On the one hand, a kind of array base palte is provided, described array base palte is formed connect low level current potential the first conductive pattern and data carry signal STV holding wire with the second conductive pattern of layer, the insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, wherein, the position of corresponding described second conductive pattern of described STV holding wire is formed towards the conductive tip of described second conductive pattern.
Further, in above-mentioned array base palte, the position of the corresponding described STV holding wire of described second conductive pattern is formed towards the conductive tip of described STV holding wire.
Further, in above-mentioned array base palte, described first conductive pattern is formed for adopting source and drain metal level, and described second conductive pattern, described conductive tip and described STV holding wire are formed for adopting grid metal level.
Further, in above-mentioned array base palte, source electrode, the electric leakage of described first conductive pattern and array base palte are very formed by a patterning processes simultaneously; The gate electrode of described second conductive pattern, described conductive tip, described STV holding wire and array base palte, grid line are for be formed by a patterning processes simultaneously.
The embodiment of the present invention additionally provides a kind of display unit, comprises array base palte as above.
The embodiment of the present invention additionally provides a kind of manufacture method of array base palte, described array base palte is formed with the first conductive pattern connecting low level current potential, with second conductive pattern of data carry signal STV holding wire with layer, insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, wherein, described manufacture method comprises: formed towards the conductive tip of described second conductive pattern in the position of corresponding described second conductive pattern of described STV holding wire.
Further, described manufacture method also comprises: formed towards the conductive tip of described STV holding wire in the position of the corresponding described STV holding wire of described second conductive pattern.
Further, described manufacture method comprises:
Source and drain metal level is adopted to form described first conductive pattern; Grid metal level is adopted to form described second conductive pattern, described conductive tip and described STV holding wire.
Further, described manufacture method comprises: utilize source and drain metal level to form source electrode, the drain electrode of described first conductive pattern and array base palte by a patterning processes simultaneously; Formed gate electrode, the grid line of described second conductive pattern, described conductive tip, described STV holding wire and array base palte by patterning processes simultaneously.
Embodiments of the invention have following beneficial effect:
In such scheme, first conductive pattern, insulating barrier and the second conductive pattern have overlapping region to form storage capacitance, the position of corresponding second conductive pattern of STV holding wire is formed towards the conductive tip of the second conductive pattern, when display floater normally works, electric charge on STV holding wire can not be input in storage capacitance, thus also can not cause abnormal show; And when accumulation on STV holding wire has larger electrostatic, electrostatic can be discharged on the second conductive pattern by conductive tip, thus reaches the object of Electro-static Driven Comb.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of STV holding wire electrostatic preventing structure in existing GOA circuit;
Fig. 2 is the schematic diagram of STV holding wire electrostatic preventing structure in embodiment of the present invention array base palte;
Fig. 3 is the schematic diagram of another electrostatic preventing structure of STV holding wire in embodiment of the present invention array base palte;
Current status schematic diagram when Fig. 4 is the input of embodiment of the present invention array base palte normal signal;
Electrostatic when Fig. 5 is the generation of embodiment of the present invention array base palte electrostatic transmits schematic diagram.
Reference numeral
1V
sSholding wire 2STV holding wire 3 second conductive pattern 4 first GOA unit 5 first conductive pattern 6 conductive tip
Embodiment
For embodiments of the invention will be solved technical problem, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Embodiments of the invention are accessed capacitor before STV input point for existing STV electrostatic prevention structure, because capacitor exists the characteristic of stored charge, and this characteristic produces signal attenuation under causing the situation normally worked at cabling, finally cause the problem of abnormal show, a kind of array base palte and manufacture method, display unit are provided, can when not affecting display effect, the electrostatic effectively release STV holding wire accumulated.
Array base palte of the present invention is formed connect low level current potential the first conductive pattern and data carry signal STV holding wire with the second conductive pattern of layer, the insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, wherein, the position of corresponding described second conductive pattern of described STV holding wire is formed towards the conductive tip of described second conductive pattern.
Array base palte of the present invention can be top-gate type structure also can be bottom-gate type configuration, when array base palte of the present invention is top-gate type structure, first conductive pattern can for be formed by grid metal level, second conductive pattern and STV holding wire can be formed by source and drain metal level, there is overlapping region to form storage capacitance in the first conductive pattern, gate insulation layer and the second conductive pattern, and adopts source and drain metal level to form conductive tip; When array base palte of the present invention is bottom-gate type configuration, first conductive pattern can be formed by source and drain metal level, second conductive pattern and STV holding wire can be formed by grid metal level, there is overlapping region to form storage capacitance in the first conductive pattern, gate insulation layer and the second conductive pattern, and adopts grid metal level to form conductive tip.
Further, the insulating barrier adopting gate insulation layer to form storage capacitance is not limited in array base palte of the present invention, as long as the insulating barrier be between the first conductive pattern and the second conductive pattern all can in order to form the insulating barrier of storage capacitance.
Further, array base palte of the present invention is not limited to horizontal electric field type array base palte, can also be vertical electric field type array base palte, if can connect low level current potential the first conductive pattern and and second conductive pattern of STV holding wire with layer between form storage capacitance.
Further, when the first conductive pattern is for adopting source and drain metal level to be formed, source electrode, the drain electrode of described first conductive pattern and array base palte can be formed by a patterning processes simultaneously; When the second conductive pattern, described conductive tip and described STV holding wire are for adopting grid metal level to be formed, gate electrode, the grid line of described second conductive pattern, described conductive tip, described STV holding wire and array base palte can be formed by a patterning processes simultaneously.Technical scheme of the present invention can be realized like this under the prerequisite not increasing patterning processes number of times.
Further, for array base palte of the present invention for bottom-gate type configuration, array base palte of the present invention specifically can comprise:
Substrate;
Be positioned at described second conductive pattern, described conductive tip, gate electrode and grid line that described substrate is formed by grid metal level;
Be positioned at the gate insulation layer on the substrate being formed with described public electrode and gate electrode, grid line;
Be positioned at described first conductive pattern, source electrode and drain electrode that described gate insulation layer is formed by source and drain metal level.
The embodiment of the present invention additionally provides a kind of manufacture method of above-mentioned array base palte, described array base palte is formed with the first conductive pattern connecting low level current potential, with second conductive pattern of data carry signal STV holding wire with layer, insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, wherein, described manufacture method comprises: formed towards the conductive tip of described second conductive pattern in the position of corresponding described second conductive pattern of described STV holding wire.
Array base palte of the present invention can be top-gate type structure also can be bottom-gate type configuration, when array base palte of the present invention is top-gate type structure, first conductive pattern can for be formed by grid metal level, second conductive pattern and STV holding wire can be formed by source and drain metal level, there is overlapping region to form storage capacitance in the first conductive pattern, gate insulation layer and the second conductive pattern, and adopts source and drain metal level to form conductive tip; When array base palte of the present invention is bottom-gate type configuration, first conductive pattern can be formed by source and drain metal level, second conductive pattern and STV holding wire can be formed by grid metal level, there is overlapping region to form storage capacitance in the first conductive pattern, gate insulation layer and the second conductive pattern, and adopts grid metal level to form conductive tip.
Further, the insulating barrier adopting gate insulation layer to form storage capacitance is not limited in array base palte of the present invention, as long as the insulating barrier be between the first conductive pattern and the second conductive pattern all can in order to form the insulating barrier of storage capacitance.
Further, array base palte of the present invention is not limited to horizontal electric field type array base palte, can also be vertical electric field type array base palte, if can connect low level current potential the first conductive pattern and and second conductive pattern of STV holding wire with layer between form storage capacitance.
Further, in order to not increase the number of times of patterning processes, when the first conductive pattern is for adopting source and drain metal level to be formed, source electrode, the drain electrode of described first conductive pattern and array base palte can be formed by a patterning processes simultaneously; When the second conductive pattern, described conductive tip and described STV holding wire are for adopting grid metal level to be formed, gate electrode, the grid line of described second conductive pattern, described conductive tip, described STV holding wire and array base palte can be formed by a patterning processes simultaneously.
Further, for array base palte of the present invention for bottom-gate type configuration, described manufacture method specifically comprises:
One substrate is provided;
By first time patterning processes, form described second conductive pattern be made up of grid metal level, described conductive tip, described STV holding wire and gate electrode and grid line on the substrate;
By second time patterning processes, the substrate through described first time patterning processes forms gate insulation layer and active layer pattern;
By third time patterning processes, the substrate through described second time patterning processes forms described first conductive pattern, source electrode and the drain electrode that are made up of source and drain metal level.Preferably, the figure forming data wire is also comprised;
Further, after the storage capacitance needed for formation and conductive tip, the pixel electrode needed for array base palte can also be made, specifically comprise:
By the 4th patterning processes, the substrate through described third time patterning processes forms the figure including the insulating barrier of pixel electrode via hole;
By the 5th patterning processes, described insulating barrier forms the figure of the pixel electrode be made up of transparency conducting layer, described pixel electrode is connected with described drain electrode by described pixel electrode via hole.
In array base palte of the present invention, first conductive pattern, insulating barrier and the second conductive pattern have overlapping region to form storage capacitance, the position of corresponding second conductive pattern of STV holding wire is formed towards the conductive tip of the second conductive pattern, when display floater normally works, electric charge on STV holding wire can not be input in storage capacitance, thus also can not cause abnormal show; And when accumulation on STV holding wire has larger electrostatic, electrostatic can be discharged on the second conductive pattern by conductive tip, thus reaches the object of Electro-static Driven Comb.
Below in conjunction with accompanying drawing 2-5, array base palte of the present invention is described in detail:
Fig. 2 is the structural representation of array base palte of the present invention, as shown in Figure 2, connects the V of low level current potential
sSholding wire 1 is connected with the first conductive pattern 5, storage capacitance is formed between second conductive pattern 3 and the first conductive pattern 5, STV holding wire 2 is connected with the first GOA unit 4, unlike the prior art, STV holding wire 2 is connected with the second conductive pattern 3 not by cabling, but conductive tip 6 is set in the position of STV holding wire 2 corresponding second conductive pattern 3, towards the second conductive pattern 3, and there is certain distance between conductive tip 6 and the second conductive pattern 3 in the tip of conductive tip 6.
Further, in order to optimize the efficiency of Electro-static Driven Comb, as shown in Figure 3, also can also arrange conductive tip in the position of the corresponding STV holding wire 2 of the second conductive pattern 3, wherein, the tip of the conductive tip be connected with the second conductive pattern 3 is towards STV holding wire 2.
As shown in Figure 4, when display floater normally works, electric charge can not be input to storage capacitance, flow of charge first GOA unit 4 on STV holding wire 2.And when accumulation on STV holding wire has larger electrostatic time, as shown in Figure 5, electrostatic can be discharged into the bottom crown (i.e. the second conductive pattern 3) of storage capacitance by conductive tip 6, and flow of charge is made to connect the V of low level current potential by storage capacitance
sSholding wire 1, thus the object reaching Electro-static Driven Comb.
Array base palte of the present invention effectively utilizes the character of point discharge, is formed towards the conductive tip of the second conductive pattern in the position of corresponding second conductive pattern of STV holding wire.Conductive tip combines with storage capacitance by technical scheme of the present invention, the setting of conductive tip can not produce again too much RC load while reinforcement Electro-static Driven Comb effect, when display floater normally works, electric charge on STV holding wire can not be input in storage capacitance, thus also can not cause abnormal show; And when accumulation on STV holding wire has larger electrostatic, electrostatic can be discharged on the second conductive pattern by conductive tip, slow releasing electric charge after storage capacitance stored charge in the energized state, under no power state, utilize high pressure to make in storage capacitance, to produce collapse electric current static guiding is walked, thus reach the object of Electro-static Driven Comb.
The embodiment of the present invention additionally provides a kind of display unit, comprises array base palte as above.This display unit can be: liquid crystal panel, Electronic Paper, OLED(OrganicLightEmittingDiode, Organic Light Emitting Diode) panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any Presentation Function.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. an array base palte, described array base palte is formed with the first conductive pattern connecting low level current potential, with second conductive pattern of data carry signal STV holding wire with layer, insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, it is characterized in that, the position of corresponding described second conductive pattern of described STV holding wire is formed towards the conductive tip of described second conductive pattern, described conductive tip is positioned at the side of described STV holding wire, the electrostatic that described STV holding wire accumulates can be discharged on the second conductive pattern by described conductive tip.
2. array base palte according to claim 1, is characterized in that, the position of the corresponding described STV holding wire of described second conductive pattern is formed towards the conductive tip of described STV holding wire.
3. array base palte according to claim 1, is characterized in that, described first conductive pattern is formed for adopting source and drain metal level, and described second conductive pattern, described conductive tip and described STV holding wire are formed for adopting grid metal level.
4. array base palte according to claim 3, is characterized in that, source electrode, the electric leakage of described first conductive pattern and array base palte are very formed by a patterning processes simultaneously; The gate electrode of described second conductive pattern, described conductive tip, described STV holding wire and array base palte, grid line are for be formed by a patterning processes simultaneously.
5. a display unit, is characterized in that, comprises the array base palte according to any one of Claims 1 to 4.
6. the manufacture method of an array base palte, described array base palte is formed with the first conductive pattern connecting low level current potential, with second conductive pattern of data carry signal STV holding wire with layer, insulating barrier between described first conductive pattern and described second conductive pattern, described first conductive pattern, described insulating barrier and described second conductive pattern have overlapping region to form storage capacitance, it is characterized in that, described manufacture method comprises: formed towards the conductive tip of described second conductive pattern in the position of corresponding described second conductive pattern of described STV holding wire, described conductive tip is positioned at the side of described STV holding wire, the electrostatic that described STV holding wire accumulates can be discharged on the second conductive pattern by described conductive tip.
7. the manufacture method of array base palte according to claim 6, is characterized in that, described manufacture method also comprises: formed towards the conductive tip of described STV holding wire in the position of the corresponding described STV holding wire of described second conductive pattern.
8. the manufacture method of array base palte according to claim 6, is characterized in that, described manufacture method comprises:
Source and drain metal level is adopted to form described first conductive pattern; Grid metal level is adopted to form described second conductive pattern, described conductive tip and described STV holding wire.
9. the manufacture method of array base palte according to claim 8, is characterized in that, described manufacture method comprises: utilize source and drain metal level to form source electrode, the drain electrode of described first conductive pattern and array base palte by a patterning processes simultaneously; Formed gate electrode, the grid line of described second conductive pattern, described conductive tip, described STV holding wire and array base palte by patterning processes simultaneously.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310123359.3A CN103227173B (en) | 2013-04-10 | 2013-04-10 | Array base palte and manufacture method, display unit |
| US14/348,652 US9224760B2 (en) | 2013-04-10 | 2013-06-13 | Array substrate and fabrication method thereof, and display device |
| PCT/CN2013/077177 WO2014166153A1 (en) | 2013-04-10 | 2013-06-13 | Array substrate, method for manufacture thereof and display device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310123359.3A CN103227173B (en) | 2013-04-10 | 2013-04-10 | Array base palte and manufacture method, display unit |
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| Publication Number | Publication Date |
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| CN103227173A CN103227173A (en) | 2013-07-31 |
| CN103227173B true CN103227173B (en) | 2016-03-30 |
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| CN201310123359.3A Active CN103227173B (en) | 2013-04-10 | 2013-04-10 | Array base palte and manufacture method, display unit |
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|---|---|
| US (1) | US9224760B2 (en) |
| CN (1) | CN103227173B (en) |
| WO (1) | WO2014166153A1 (en) |
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|---|---|---|---|---|
| CN104090436B (en) * | 2014-06-26 | 2017-03-22 | 京东方科技集团股份有限公司 | Gate line drive circuit of array substrate and display device |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2014166153A1 (en) | 2014-10-16 |
| US20150162347A1 (en) | 2015-06-11 |
| CN103227173A (en) | 2013-07-31 |
| US9224760B2 (en) | 2015-12-29 |
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