CN111221399A - Loongson CPU-based peripheral system circuit and system - Google Patents
Loongson CPU-based peripheral system circuit and system Download PDFInfo
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Abstract
The embodiment of the invention provides a peripheral system circuit and a system based on a Loongson CPU, wherein the peripheral system circuit at least comprises a system power supply circuit connected with the Loongson CPU, the system power supply circuit comprises two power supply chips, a fourth path of time sequence control signal end of one power supply chip is connected with a first path of enable control signal end of the other power supply chip, and the power supply chips are chips with input voltage of 4-14V, output voltage of 0.65-5.5V and 4 paths of voltage output. Therefore, the peripheral system circuit based on the Loongson CPU can supply power to the Loongson CPU, and the safety and the stability of the Loongson CPU are improved. Besides, the scheme also provides other functional circuits except for power supply, and the safety and the stability of the Loongson CPU are further improved.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a peripheral system circuit and a peripheral system based on a Loongson CPU.
Background
Therefore, how to provide a peripheral system circuit based on the Loongson CPU to improve the safety and stability of the Loongson CPU is a great technical problem to be solved by technical personnel in the field.
Disclosure of Invention
In view of this, embodiments of the present invention provide a peripheral system circuit based on a Loongson CPU, which can improve the security and stability of the Loongson CPU.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a Loongson CPU-based peripheral system circuit, comprising: a system power supply circuit connected with the Loongson CPU,
the system power supply circuit comprises two power supply chips, wherein a fourth path of time sequence control signal end of one power supply chip is connected with a first path of enable control signal end of the other power supply chip, and the power supply chip is a chip with 4-14V input voltage, 0.65-5.5V output voltage and 4 paths of voltage output.
Optionally, the method further includes: a Pmon starting circuit connected with the Loongson CPU,
the Pmon starting circuit comprises a two-bit dial switch, and the two-bit dial switch is used for switching the SPI interface and the SDIO interface.
Optionally, the method further includes: a DDR circuit connected with the Loongson CPU,
the DDR circuit is a memory with a memory of 4Gb and a bit width data of 16 bits.
Optionally, the method further includes: an Ethernet circuit connected with the Loongson CPU,
the Ethernet circuit is a PHY chip with three interfaces of MII, GMII and RGMII.
Optionally, the method further includes: a PCIE circuit connected with the Loongson CPU,
the PCIE circuit is a PCIE circuit with the transmission rate of 2.5G/S.
Optionally, the method further includes: an RTC circuit connected with the Loongson CPU,
the RTC circuit is an FM38025T chip.
Optionally, the method further includes: an RS485 circuit connected with the Loongson CPU,
the RS485 circuit is a communication module with the communication speed of 115200 bps.
Optionally, the method further includes: EJTAG circuit connected with the Loongson CPU,
the EJTAG circuit is a circuit with a Loongson CPU standard interface.
Optionally, the method further includes: and the system reset circuit is connected with the Loongson CPU and is used for resetting the Loongson CPU.
A system comprising a Loongson CPU and any one of the above peripheral system circuits.
Based on the technical scheme, the embodiment of the invention provides a peripheral system circuit and a system based on a Loongson CPU, wherein the peripheral system circuit at least comprises a system power supply circuit connected with the Loongson CPU, the system power supply circuit comprises two power supply chips, a fourth path of time sequence control signal end of one power supply chip is connected with a first path of enable control signal end of the other power supply chip, and the power supply chip is a chip with 4-14V input voltage, 0.65-5.5V output voltage and 4 paths of voltage output. Therefore, the peripheral system circuit based on the Loongson CPU can supply power to the Loongson CPU, and the safety and the stability of the Loongson CPU are improved. Besides, the scheme also provides other functional circuits except for power supply, and the safety and the stability of the Loongson CPU are further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of another structure of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of another configuration of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of another configuration of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of another configuration of a Loongson CPU-based peripheral system circuit according to an embodiment of the present invention;
fig. 13 is a schematic diagram of another structure of a peripheral system circuit based on a Loongson CPU according to an embodiment of the present invention;
fig. 14 is a schematic diagram of another structure of a peripheral system circuit based on a Loongson CPU according to an embodiment of the present invention;
fig. 15 is a schematic diagram of another structure of a peripheral system circuit based on a Loongson CPU according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of a peripheral system circuit based on a Loongson CPU according to an embodiment of the present invention.
Detailed Description
As background art shows, with the increasing requirements of industries in the domestic core field such as industrial control on safety, reliability and confidentiality, a completely autonomous and controllable Loongson CPU is an indispensable choice, and a set of stable, safe and reliable peripheral circuit is designed for the Loongson CPU, so that high processing capacity of the Loongson CPU can be better exerted, wider industrial field application is realized, higher system scheme stability is realized, and the requirements of high safety, high reliability and high confidentiality are met.
Based on this, the embodiment of the present invention provides a loongson CPU-based peripheral system circuit, as shown in fig. 1, including main parts such as power supply, NOR flash (Pmon boot), DDR, ethernet, PCIE, RTC, RS485, EJATG, system reset, and the like.
Specifically, the loongson CPU-based peripheral system circuit includes: a system power supply circuit connected with the Loongson CPU,
the system power supply circuit comprises two power supply chips, wherein a fourth path of time sequence control signal end of one power supply chip is connected with a first path of enable control signal end of the other power supply chip, and the power supply chip is a chip with 4-14V input voltage, 0.65-5.5V output voltage and 4 paths of voltage output.
Schematically, in combination with fig. 2 and fig. 3, for the timing requirement of the Loongson, a scheme based on a highly reliable integrated chip is selected, which provides a wide voltage input of 4-14V, an adjustable voltage output of 0.65V-5.5V, 4 voltage outputs, and 4A current output capacity of each path, so that the timing of each power output can be controlled, the power supply timing requirement of the Loongson CPU is met, and the output accuracy of the chip is +/-1.5%.
The power supply of the Loongson RSM domain and the power supply of the CORE domain need 8 paths of power supply totally, two 4 paths of voltage output chips are matched for use to meet the requirement of the whole peripheral power supply, and the fourth path of time sequence control PWGOOD signal of the 1 st chip is connected to the first path of enable control RUN signal of the second chip to complete the time sequence integral control of a Loongson CPU consisting of the two chips.
The power-on sequence is as follows:
(1) RTC Power-on first (RTC _ VDD, 2.5V)
(2) RSM domain power supply power-on
a. 1.1V Power-on (VDD _ RSM)
b. 2.5V Power supply (GMAC _2V5)
c. 3.3V Power supply (USB _ A3V3/RSM3V3)
(3) On the CORE domain power supply
a. 3.3V IO Power supply (VDDE3V3)
b. 1.8V/1.5V power supply
c. The 1.1V core CPU power supply and the 1.2V PCIE/SATA power supply (VDD _ SOC/PEST _1V1) need to be described in the following, where the power-up interval is greater than 1us, but the power-up sequence is not mandatory here, and may be in other manners.
In addition, the peripheral system circuit provided in the embodiment of the present invention may further include: and the Pmon starting circuit is connected with the Loongson CPU and comprises a two-position dial switch, and the two-position dial switch is used for switching the SPI interface and the SDIO interface.
Schematically, in conjunction with fig. 4-7, the inventor considers that the Pmon start-up of loongson supports 4 forms, which are: SPI starts, SDIO starts, and NAND starts, and LIO starts, and the most that uses wherein is SPI starts and SDIO starts, consequently, this embodiment is based on these two kinds of starting methods, and these two kinds of mode start is nimble, stable and safe.
Specifically, the scheme adopts a two-position dial switch mode to realize the switching selection starting mode of the SPI interface and the SDIO interface of the Pmon, the SPI interface mode is selected to start by dialing the dial switch to the SPI NOR FLASH (domestic mega easy GD25Q127CSIGR) starting mode, when the godson starts, the information of the Pmon is read from the SPI NOR FLASH (domestic mega easy GD25Q127CSIGR) and is actively loaded and started, and the whole hardware function and the initialization of the interface are realized. The starting is carried out by dialing the dial switch to the SDIO, and when the Loongson is electrified and started, Pmon information of the Loongson is actively read from the SDIO and is actively loaded, so that the starting is finished.
It should be noted that, the SDIO mode of the present scheme is a reserved redundancy tooling scheme, and the Pmon start mode mainly selects the SPI mode to start.
In addition, the peripheral system circuit provided in the embodiment of the present invention may further include: and the DDR circuit is connected with the Loongson CPU and is a memory with a memory of 4Gb and a bit width data of 16 bits.
Illustratively, as shown in fig. 8, considering that the loongson supports a 64bit DDR3 controller, the maximum operating frequency 533 Mhz. Command scheduling is supported and configurations are supported for use with 32 bits and 16 bits.
The design is 32-bit based on an OS operating system, and a scheme for operating by using 32-bit-width data is selected in consideration of the optimal use effect and cost of bit width.
The DDR3 single-chip memory size 4Gb (512MB) is adopted to support 16-bit data bit width operation and 16-bit address bit width operation. The 32bit scheme needs to use 2 DDR3 chips to form a 1G-size memory scheme, and various data processing and cache support are realized.
In addition, the peripheral system circuit provided in the embodiment of the present invention may further include: and the Ethernet circuit is a PHY chip with three interfaces of MII, GMII and RGMII.
Illustratively, as shown in fig. 9 and fig. 10, considering that the Loongson CPU supports two 10/100/1000Mbps adaptive Ethernet MAC controllers, both dual network cards are compatible with IEEE 802.3, and an RGMII interface, half-duplex/full-duplex adaptation, is implemented for the external PHY.
Therefore, the embodiment adopts the PHY chip with three interfaces of MII, GMII and RGMII, and supports 10/100/1000Mbps adaptive Ethernet; the LED display function is provided, and the Link and ACT state programming indication function is supported. Because the Loongson supports the RGMII interface, the scheme realizes the functions of two paths of network ports and adopts the RGMII interface mode to realize communication with the Loongson CPU.
In addition, the peripheral system circuit provided in the embodiment of the present invention further includes: and the PCIE circuit is connected with the Loongson CPU and is a PCIE circuit with the transmission rate of 2.5G/S.
Illustratively, as shown in fig. 11, in consideration of a loongson compatible PCIE 2.0, the backplane has dual independent X4 interfaces, where one path of X4 interface may be configured as 4X1 interfaces, and another path of X4 interface may be configured as 2X 1 interfaces, so that the scheme adopts an X4 interface that can be divided into 4X1 interfaces, and the X4 interface is used as 4X1 interfaces, so as to implement high-speed backplane communication of PCIE.
The CPU supports 4X1 PCIE peripherals, namely 1 channel and 1 peripheral, wherein the data transmission rate of each channel is 2.5G/S, and 4 channels can reach 10G/S; through the PCIE buffer chip, 4 peripherals can be connected, and the data transmission rate of each peripheral is 2.5G/S, which is enough for data interaction of a high-speed module; all LK224 modules are compatible with 2-slot, 4-slot high speed peripheral (high speed module) applications.
PCIE belongs to high-speed and low-voltage signals, has high requirements on the quality of a power supply, and adopts a same-source clock in clock design to ensure that receiving and sending master and slave devices use the same clock.
In addition, the peripheral system circuit provided in the embodiment of the present invention further includes: and the RTC circuit is connected with the Loongson CPU.
Schematically, as shown in fig. 12, when the module is powered down, for an application requiring a clock, power can be supplied to an external battery and an external large-capacitance accessory. When a lithium battery is adopted for power supply, the power failure can normally work for 1 year; when a large capacitor is adopted for power supply, the power failure can normally work for 7 days. The module design is compatible with battery and capacitor accessories for power supply, and the client can choose and match the module as required.
In addition, the peripheral system circuit provided in the embodiment of the present invention further includes: and the RS485 circuit is connected with the Loongson CPU, and the RS485 circuit is a communication module with the communication speed of 115200 bps.
Illustratively, as shown in fig. 13, the RS485 circuit connects the CPU module and the expansion module together, the communication rate is 115200bps, the routing is short, and the number of the connection modules is at most 5.
In addition, the peripheral system circuit provided in the embodiment of the present invention further includes: and the EJTAG circuit is connected with the Loongson CPU and is a circuit with a Loongson CPU standard interface.
Illustratively, as shown in fig. 14, EJTAG adopts a Loongson standard interface, which is mainly used for downloading and erasing of the Pmon program, and for online debug and debugging functions of the Pmon program. The standard JTAG interface is not illustrated.
In addition, the peripheral system circuit provided in the embodiment of the present invention further includes: and the system reset circuit is connected with the Loongson CPU and is used for resetting the Loongson CPU.
Schematically, as shown in fig. 15 and 16, fig. 15 is a system reset, a watchdog reset is reserved in the design, fig. 16 is a power-on reset, a main power supply of the CPU is monitored, and the reset is performed when any power supply is abnormal (under-voltage).
The CPU power-on sequence can know that the system is reset before, and the CPU can be normally started after the power-on reset. The reset time is maximum 280mS, and the reset time is adjustable according to the capacitance;
when 0.1UF is selected according to the formula, the reset time is 460.8mS.
When a 0.1UF capacitor is selected, the correct reset timing cannot be guaranteed in consideration of device differences and temperature influences. In this embodiment, in order to ensure the reset timing, 3 capacitors of 0.1UF are used, and therefore the minimum reset time is 225 × 3 — 675mS, and the power-on timing can be ensured.
On the basis of the above embodiments, an embodiment of the present invention further provides a system, which includes a loongson CPU and any one of the above peripheral system circuits. The working principle of the system is described in the above embodiments of the system circuit, and will not be described repeatedly.
To sum up, the embodiment of the present invention provides a loongson CPU-based peripheral system circuit and a loongson CPU-based peripheral system circuit, where the peripheral system circuit at least includes a system power supply circuit connected to the loongson CPU, where the system power supply circuit includes two power supply chips, a fourth path of time sequence control signal end of one power supply chip is connected to a first path of enable control signal end of another power supply chip, and the power supply chip is a chip with an input voltage of 4-14V, an output voltage of 0.65-5.5V, and 4 paths of voltage output. Therefore, the peripheral system circuit based on the Loongson CPU can supply power to the Loongson CPU, and the safety and the stability of the Loongson CPU are improved. Besides, the scheme also provides other functional circuits except for power supply, and the safety and the stability of the Loongson CPU are further improved.
The present application has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a device includes one or more processors (CPUs), memory, and a bus. The device may also include input/output interfaces, network interfaces, and the like.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A Loongson CPU-based peripheral system circuit, comprising: a system power supply circuit connected with the Loongson CPU,
the system power supply circuit comprises two power supply chips, wherein a fourth path of time sequence control signal end of one power supply chip is connected with a first path of enable control signal end of the other power supply chip, and the power supply chip is a chip with 4-14V input voltage, 0.65-5.5V output voltage and 4 paths of voltage output.
2. The peripheral system circuit of claim 1, further comprising: a Pmon starting circuit connected with the Loongson CPU,
the Pmon starting circuit comprises a two-bit dial switch, and the two-bit dial switch is used for switching the SPI interface and the SDIO interface.
3. The peripheral system circuit of claim 1, further comprising: a DDR circuit connected with the Loongson CPU,
the DDR circuit is a memory with a memory of 4Gb and a bit width data of 16 bits.
4. The peripheral system circuit of claim 1, further comprising: an Ethernet circuit connected with the Loongson CPU,
the Ethernet circuit is a PHY chip with three interfaces of MII, GMII and RGMII.
5. The peripheral system circuit of claim 1, further comprising: a PCIE circuit connected with the Loongson CPU,
the PCIE circuit is a PCIE circuit with the transmission rate of 2.5G/S.
6. The peripheral system circuit of claim 1, further comprising: an RTC circuit connected with the Loongson CPU,
the RTC circuit is an FM38025T chip.
7. The peripheral system circuit of claim 1, further comprising: an RS485 circuit connected with the Loongson CPU,
the RS485 circuit is a communication module with the communication speed of 115200 bps.
8. The peripheral system circuit of claim 1, further comprising: EJTAG circuit connected with the Loongson CPU,
the EJTAG circuit is a circuit with a Loongson CPU standard interface.
9. The peripheral system circuit of claim 1, further comprising: and the system reset circuit is connected with the Loongson CPU and is used for resetting the Loongson CPU.
10. A system comprising a Loongson CPU and the peripheral system circuitry of any of claims 1-9.
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