CN111221390A

CN111221390A - Backboard compatible with time-sharing connection of CPU and Tri mode card and implementation method

Info

Publication number: CN111221390A
Application number: CN201911415246.4A
Authority: CN
Inventors: 唐传贞
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-06-02

Abstract

The invention provides a backboard compatible with time-sharing connection of a CPU (Central processing Unit) and a Tri mode card and an implementation method thereof. And identifying whether the card is directly connected with the tri mode or the CPU directly connected with the dial switch when the CPLD code is developed. The dial switch is connected with the GPIO pin of the CPLD, and can inform the GPIO pin of high or low. The CPU direct connection or the tri mode card direct connection is identified through different high and low level CPLDs, two back plates are not required to be designed, and development workload and labor cost are reduced. Aiming at the front-end customer service maintenance, when the configuration of a customer is changed, a back plate does not need to be replaced, and the maintainability of the product is improved. Aiming at the front-end customer service maintenance, when the configuration of a customer is changed, a back plate does not need to be replaced, and the maintainability of the product is improved.

Description

Backboard compatible with time-sharing connection of CPU and Tri mode card and implementation method

Technical Field

The invention relates to the technical field of servers, in particular to a backboard compatible with time-sharing connection of a CPU (Central processing Unit) and a Tri mode card and an implementation method.

Background

With the continuous development of cloud computing, each large internet operator has more and more requirements on the configuration of server products, and the configuration of hard disks in the server products is indispensable. Some operators want to connect the back board with NVME hard disk through the CPU on the main board in the server. Some operators want to connect a backplane with NVME hard disks via a tri mode card. The difference between a CPU connection backplane and a tri mode card connection backplane is that: when the CPU is connected to the backplane, the number of PCIE channels of each CPU can support connection of more than 10 NVME hard disks (four PCIE channels are connected to one NVME hard disk), one CPU supports one VPP channel, and a lighting signal carried in one VPP channel includes all the hard disks connected to the CPU. The lighting information of all the hard disks is notified to the CPLD on the backboard by one VPP channel of the CPU for signal analysis. The CPU connector needs to have a VPP address to distinguish which PCIE port of the CPU is connected to the backplane. A tri mode card is characterized in that each PCIE port connector contains an I2C signal similar to VPP, each I2C corresponds to each hard disk, and different PCIE ports do not need to be distinguished by addresses. Aiming at different connection conditions of a tri mode card connection backboard and a mainboard CPU connection backboard, two different backboard are designed to be matched respectively in the past. Double development labor and cost are required, and two different back plates are required to be maintained, so that maintenance cost is increased.

The flexibility of the prior art is lower, two different backboards need to be maintained, firstly, the development quantity of the backboards is increased, and more development manpower and cost are invested. And secondly, different back plates need to be replaced when the front-end client is modified on site, so that the maintenance cost is increased.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a backplane compatible with a time-sharing connection CPU and a Tri mode card, which comprises: the device comprises a programmable logic device, a hard disk interface, a connecting assembly and a state acquisition module; the connecting component is provided with a connector;

the programmable logic device is respectively connected with the hard disk interface, the connector and the state acquisition module;

the programmable logic device acquires the current connection information of the connection component through the state information of the state acquisition module;

when the programmable logic device obtains the first logic information of the state obtaining module, the programmable logic device confirms that the connector is connected with the first module; the first module is connected with the hard disk interface;

and when the programmable logic device acquires the second logic information of the state acquisition module, the programmable logic device confirms that the connector is connected with the second module, and the second module is connected with the hard disk interface.

It is further noted that the first module is a CPU;

the connecting assembly is also provided with a VPP connector;

the connector is connected with the data output end of the CPU;

the VPP connector is connected with a VPP end of the CPU;

and when the state acquisition module acquired by the programmable logic device is the first logic information, the programmable logic device confirms that the CPU is connected with the memory through the connector and the hard disk interface.

It is further noted that the second module is a tri mode card;

the connector is connected with a tri mode card;

and when the programmable logic device acquires the second logic information of the state acquisition module, the programmable logic device confirms that the tri mode card is connected with the memory through the connector and the hard disk interface.

The invention also provides a method for realizing the compatible time-sharing connection of the CPU and the Tri mode card, which comprises the following steps:

the programmable logic device acquires the logic information of the state acquisition module;

and judging the current connected module of the connecting component according to the logic information.

It should be further noted that the programmable logic device analyzes the state of the communication signal between the connecting component and the connecting component, and controls the display state of the display lamp.

It should be further noted that the programmable logic device confirms logic information according to the high and low levels of the state acquisition module.

According to the technical scheme, the invention has the following advantages:

the invention supports a tri mode card and a mainboard CPU to be directly connected with a programmable logic device, a one-bit dial switch is added on the programmable logic device, and the dial switch is connected with the programmable logic device through signals. And identifying whether the card is directly connected with the tri mode or the CPU directly connected with the dial switch when the CPLD code is developed. The dial switch is connected with the GPIO pin of the CPLD, and can inform the GPIO pin of high or low. The CPU direct connection or the tri mode card direct connection is identified through different high and low level CPLDs, two back plates are not required to be designed, and development workload and labor cost are reduced. Aiming at the front-end customer service maintenance, when the configuration of a customer is changed, a back plate does not need to be replaced, and the maintainability of the product is improved. Aiming at the front-end customer service maintenance, when the configuration of a customer is changed, a back plate does not need to be replaced, and the maintainability of the product is improved.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a backplane compatible with time-sharing connection of a CPU and a Tri mode card;

FIG. 2 is a schematic diagram of an embodiment of a backplane compatible with time-sharing connection of a CPU and a Tri mode card;

fig. 3 is a flow chart of an implementation method.

Detailed Description

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.

The Memory or hard disk referred to in the present invention may be NVME (Non-Volatile Memory express). The hard disk interface can be a logic device interface specification and is a novel hard disk interface.

The Programmable Logic device may be a cpld (complex Programmable Logic device), a complex Programmable Logic device. And a power supply which is commonly used on the server is powered on and powered off, and the backboard is used for lighting the control unit.

A bus interface of a VPP (virtual pin port) CPU is also involved, like the I2C bus.

As an embodiment of the present invention, a backplane compatible with time-sharing connection between a CPU11 and a Tri mode card 12 is shown in fig. 1 and fig. 2, and the backplane is configured in a server by modifying the backplane port design, and modules, such as the CPU11 or the Tri mode card 12, can be connected as needed. The method specifically comprises the following steps: the device comprises a programmable logic unit 1, a hard disk interface 2, a connecting assembly 3 and a state acquisition module; the connecting component is provided with a connector;

the programmable logic device 1 is respectively connected with the hard disk interface 2, the connector and the state acquisition module;

the programmable logic device 1 acquires the current connection information of the connector through the state information of the state acquisition module;

when the programmable logic device 1 acquires that the state acquisition module is the first logic information, the connector is confirmed to be connected with the first module; the first module is connected with the hard disk interface 2;

when the state acquisition module is the second logic information, the programmable logic device 1 confirms that the connector is connected with the second module, and the second module is connected with the hard disk interface 2.

The logic information is set based on the system pre-configuration, and the state acquisition module can provide high and low levels for the programmable logic device 1 to confirm the logic information. For example, the status acquisition module adopts the dial switch 4. The encoding module may also be adapted to validate based on differences in the encoded values. The specific form is not limited. As the connector, a slim connector 6; the programmable logic device 1 adopts a CPLD chip and peripheral circuits thereof.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

In an exemplary embodiment, the present invention is directed to a backplane that supports connection of a tri mode card 12 and a connection motherboard CPU11, and that multiplexes two of the VPP address pins and I2C required by the tri mode card 12 in the same PCIE port connector. A one-bit dial switch 4 is added on the backboard, and the dial switch 4 is connected with the CPLD through signals. During CPLD code development, whether the front end of the PCIE port connector is connected with the tri mode card 12 or the mainboard CPU11 needs to be identified through the dial switch 4. The dial switch 4 is connected with a GPIO pin of the CPLD, and the dial can inform the GPIO pin of high or low. The CPLD with different high and low levels is used for identifying whether the CPU11 or the tri mode card 12 is connected, and different analysis actions are carried out on VPP and I2C, so that the aim of normally lighting the hard disk is fulfilled.

The first module is the CPU 11; the connecting assembly is also provided with a VPP connector 7; the connector is connected with a data output end of the CPU 11; the VPP connector is connected with a VPP end of the CPU 11; when the programmable logic device 1 acquires the first logic information of the state acquisition module, it is confirmed that the CPU11 is connected to the memory 5 through the connection component and the hard disk interface 2.

The second module is a tri mode card 12; the connector is connected with the tri mode card 12; when the programmable logic device 1 acquires the second logic information of the state acquisition module, the state acquisition module confirms that the tri mode card 12 is connected with the memory 5 through the connecting component and the hard disk interface 2.

The invention is further illustrated by specific embodiments with reference to fig. 1, table 1 and table 2 below:

1) here, we take two NVME hard disk interface backplanes as an example for explanation. The backplane is connected to the motherboard, and the backplane is connected to the trimode card through a cable, where the cable interface is, for example, a slim line connector (the connector is the PCIE port connector mentioned above, and a high-speed signal going on each slim line corresponds to a signal required by an NVME hard disk) commonly used in the industry at present, and other connectors are the same. As in table 1, is the definition of each pin of the slim connector, wherein the pink portion is the high-speed signal portion (PCIE signal), and the gray portion is the shielding ground for the high-speed signal. High speed signals and ground cannot change design, which is an industry specification. The yellow part is a sideband signal and belongs to a low-speed signal. The sideband signals may have different signal definitions depending on the source. Table 2 shows the specific definition of the multiplexing signal in different connections. When the Slimline connector is connected to the CPU, the four pins A8, A9, A10 and A12 are defined as ADDR1, ADDR2, ADDR3 and ADDR4, which are the aforementioned VPP addresses. The four pins are connected to the CPLD, and the CPLD can judge which specific PCIE port of the CPU is connected according to the four pins. When the Slimline connector is connected with a tri mode card, two pins A8 and A9 are in multiplex design and are set as an I2C path connected with the tri mode card, and I2C consists of two signals, one is DATA and the other is Clock. I2C and address pin multiplexing are designed in each Slimline connector on the corresponding back panel of the invention.

Table 1: slimline connector interface definition

TABLE 2 sideband Signal definition

Pin	Connecting CPU	Connecting tri mode card
			A8	Address 1	Clock
A9	Address 2	Data
			A10	Address 3	Need not use
A12	Address	4				Is different

Therefore, the direct connection of the CPU and the tri mode card can be realized through compatible support of the back boards, two back boards are not required to be designed, and the development workload and the labor cost are reduced. Aiming at the front-end customer service maintenance, when the configuration of a customer is changed, a back plate does not need to be replaced, and the maintainability of the product is improved.

Based on the above-mentioned backplane compatible with time-sharing connection of the CPU and the Tri mode card, the present invention further provides a method for implementing compatible time-sharing connection of the CPU and the Tri mode card, as shown in fig. 3, the method includes:

s11, the programmable logic device obtains the logic information of the state obtaining module;

and S12, judging the current connected module of the connecting component according to the logic information.

In an exemplary embodiment, two NVME backplanes are taken as an example, and two NVME hard disk interfaces, two Slimline connectors, one VPP connector, and one dial switch are provided in the backplanes. The dial switch design can be pulled up to power and down to ground. The NVME hard disk lighting signal is controlled by the CPLD. When the backboard is connected with the CPU, the two slim line connectors and the VPP connector are both connected to the mainboard CPU, a PCIE signal of the CPU is connected to an NVME hard disk interface through the slim line connectors, a VPP address of the CPU is connected to the CPLD through the slim line, a VPP signal of the CPU is connected to the CPLD through the VPP connector, and one CPU only has one group of VPP signals. When the back board is connected with the tri mode card, PCIE signals and I2C signals on the tri mode card are connected to the NVME hard disk interface and the CPLD of the back board through the slim line connector. When the dial switch is dialed to a power supply end, and the CPLD recognizes that the GPIO is at a high level, the CPLD recognition backboard is connected to the CPU, and the pin of the Slimline connector connected to the CPLD is recognized as an address pin. The lighting signal of the hard disk is based on the signal on the VPP connector, and the specific PCIE port connected with the CPU is determined by judging the address pin in each slim line connector. When the dial switch is dialed to the ground, the GPIO is identified as a low level. The CPLD identification back plate is connected to the tri mode card, and one I2C corresponds to one NVME hard disk on the basis that the Slimline connector is connected to the I2C signal of the CPLD. And the CPLD analyzes the I2C signal and lights up corresponding to each hard disk interface. Through the design mode of the back panel, the compatibility of the back panel with a time-sharing connection main board CPU and a connection tri mode card is realized.

The method of the invention controls the display state of the display lamp based on the communication signal state between the programmable logic device analysis and the connection component.

The purpose of normally lighting the hard disk is achieved by identifying whether the CPLD is connected with the CPU or the tri mode card through different high and low levels and performing different analysis actions aiming at VPP and I2C.

Therefore, the pins in the connecting component are multiplexed, the pins are multiplexed into an address function and an I2C function, the dial switch is added to be connected to the back plate CPLD, and the specific function of the multiplexing pins is informed to the back plate CPLD through the dial switch.

And improving CPLD development, adding a judgment function in a CPLD code, judging whether a source end is connected with a mainboard CPU directly or a tri mode card directly through a dial switch, and selecting to analyze a VPP signal input by an independent VPP connector or an I2C signal in a slim connector according to different identified source ends. The method can be used on all server products, is not limited to two-way NVME backplanes, is not limited to slim line connectors, and other backplanes and connectors are also suitable.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A backplane compatible with time-sharing connection between a CPU and a Tri mode card, comprising: the device comprises a programmable logic device, a hard disk interface, a connecting assembly and a state acquisition module; the connecting component is provided with a connector;

the programmable logic device acquires the current connection information of the connector through the state information of the state acquisition module;

2. The backing sheet of claim 1,

the first module is a CPU;

the connecting assembly is also provided with a VPP connector;

the connector is connected with the data output end of the CPU;

the VPP connector is connected with a VPP end of the CPU;

3. The backing sheet of claim 1,

the second module is a tri mode card;

the connector is connected with a tri mode card;

4. A backsheet according to claim 2 or 3,

the state acquisition module adopts a dial switch, and confirms logic information based on the high and low levels of the dial switch.

5. A backsheet according to claim 2 or 3,

and a display lamp is connected between the hard disk interface and the programmable logic device.

6. A backsheet according to claim 2 or 3,

the programmable logic device and the connector are connected by an I2C bus.

7. A backsheet according to claim 2 or 3,

the connector adopts a slim line connector;

the programmable logic device adopts a CPLD chip and a peripheral circuit thereof.

8. A compatible time-sharing connection CPU and Tri mode card implement method, characterized by that, the method comprises:

9. The implementation method of claim 8,

the programmable logic device analyzes the state of the communication signal between the connecting component and controls the display state of the display lamp.

10. The implementation method of claim 8,

and the programmable logic device confirms logic information according to the high and low levels of the state acquisition module.