CN111210766B - Inverter and driving method thereof, gate driving circuit and display device - Google Patents
Inverter and driving method thereof, gate driving circuit and display device Download PDFInfo
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- CN111210766B CN111210766B CN202010113201.8A CN202010113201A CN111210766B CN 111210766 B CN111210766 B CN 111210766B CN 202010113201 A CN202010113201 A CN 202010113201A CN 111210766 B CN111210766 B CN 111210766B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The embodiment of the invention provides an inverter, a driving method of the inverter, a grid driving circuit and a display device, relates to the technical field of display, simplifies the manufacturing process and reduces the design size. The inverter includes: an input signal terminal and an output signal terminal; the control module is respectively connected with the input signal end, the high potential signal end, the low potential signal end and the first node; the output module comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are P-type transistors; the grid electrode of the first transistor is connected with the input signal end, the first pole of the first transistor is connected with the high-potential signal end, and the second pole of the first transistor is connected with the output signal end; the grid electrode of the second transistor is connected with the first node, the first pole of the second transistor is connected with the low-potential signal end, and the second pole of the second transistor is connected with the output signal end; the control module is used for: the input signal terminal outputs a high level when it provides a low level, and outputs a low level when it provides a high level.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to an inverter, a driving method of the inverter, a grid driving circuit and a display device.
[ background of the invention ]
In order to drive the display device to normally emit light, a grid driving circuit for providing scanning signals for the grid lines is arranged in a frame area of the display device, and an inverter is arranged in the grid driving circuit. Because the frame area of the display device still needs to be provided with other circuit structures, the setting space, the manufacturing cost and the process are limited, therefore, how to optimize the circuit of the inverter is constructed for the purpose of the problem to be solved at present.
[ summary of the invention ]
In view of this, embodiments of the present invention provide an inverter, a driving method thereof, a gate driving circuit, and a display device, which can simplify a manufacturing process of the inverter and reduce a design size of the inverter.
In one aspect, an embodiment of the present invention provides an inverter, including:
an input signal terminal and an output signal terminal;
the control module is electrically connected with the input signal end, the high potential signal end, the low potential signal end and the first node respectively;
the output module comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are both P-type transistors; the grid electrode of the first transistor is electrically connected with the input signal end, the first electrode of the first transistor is electrically connected with the high-potential signal end, and the second electrode of the first transistor is electrically connected with the output signal end; a grid electrode of the second transistor is electrically connected with the first node, a first electrode of the second transistor is electrically connected with the low-potential signal end, and a second electrode of the second transistor is electrically connected with the output signal end;
the control module is used for: outputting a high level to the first node when the input signal terminal provides a low level, and outputting a low level to the first node when the input signal terminal provides a high level.
On the other hand, an embodiment of the present invention provides a driving method for an inverter, which is applied to the inverter, and the driving method includes:
when the input signal end provides a low level, the first transistor is conducted, so that the high level provided by the high-potential signal end is transmitted to the output signal end, and the control module outputs the high level to the first node, so that the second transistor is cut off;
when the input signal end provides a high level, the control module outputs a low level to the first node, controls the second transistor to be conducted, and enables the low level provided by the low level signal end to be transmitted to the output signal end.
In another aspect, an embodiment of the present invention provides a gate driving circuit, which includes the inverter.
In another aspect, an embodiment of the invention provides a display device, which includes the gate driving circuit.
One of the above technical solutions has the following beneficial effects:
in the technical solution provided by the embodiment of the present invention, by setting the control module, both the first transistor and the second transistor of the output transistor can be set as P-type transistors, and the first transistor and the second transistor are in a conducting state and the other is in a blocking state at the same time under the control of the control module, thereby ensuring the normal operation of the inverter. Compared with the prior art, the output transistors in the inverter provided by the embodiment of the invention are all P-type transistors, and N-type transistors are not required, so that the manufacturing process is simplified, and the manufacturing cost is reduced. In addition, because the P-type transistor has stronger driving capability, two output transistors in the inverter are both set as the P-type transistors, the driving capability of the inverter can be further improved, and the working performance of the inverter is optimized.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an inverter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another structure of an inverter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another structure of an inverter according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another structure of an inverter according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another structure of an inverter according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another structure of an inverter according to an embodiment of the present invention;
FIG. 7 is a flowchart of a driving method according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe transistors in embodiments of the present invention, these transistors should not be limited to these terms. These terms are only used to distinguish transistors from one another. For example, a first transistor may also be referred to as a second transistor, and similarly, a second transistor may also be referred to as a first transistor, without departing from the scope of embodiments of the present invention.
The inventor finds in the research process that the inverter can be formed by two output transistors, and the two output transistors can adopt the following two setting modes, namely: adopting a P-type transistor and an N-type transistor as two output transistors respectively, and adopting a second type: a P-type transistor and an Indium Gallium Zinc Oxide (IGZO) transistor are respectively used as two output transistors. However, the inventor further studies and finds that the first inverter has a complicated manufacturing process and a relatively high manufacturing cost, and the second inverter has a weak driving capability of the IGZO transistor, so that the IGZO transistor needs to be designed to have a large size when used as an output tube, which results in the inverter occupying a large space and is not favorable for designing a narrow frame of a display device. For this reason, the inventors further propose an inverter structure as follows:
an embodiment of the present invention provides an inverter, as shown IN fig. 1, fig. 1 is a schematic structural diagram of an inverter provided IN an embodiment of the present invention, where the inverter includes an input signal terminal IN, an output signal terminal OUT, a control module 1, and an output module 2; the control module 1 is electrically connected with an input signal end IN, a high-potential signal end VGH, a low-potential signal end VGL and a first node N1 respectively; the output module 2 comprises a first transistor M1 and a second transistor M2, wherein the first transistor M1 and the second transistor M2 are both P-type transistors; the gate of the first transistor M1 is electrically connected to the input signal terminal IN, the first pole of the first transistor M1 is electrically connected to the high-potential signal terminal VGH, and the second pole of the first transistor M1 is electrically connected to the output signal terminal OUT; a gate of the second transistor M2 is electrically connected to the first node N1, a first pole of the second transistor M2 is electrically connected to the low potential signal terminal VGL, and a second pole of the second transistor M2 is electrically connected to the output signal terminal OUT. The control module 1 is used for: when the input signal terminal IN is supplied with a low level, a high level is output to the first node N1, and when the input signal terminal IN is supplied with a high level, a low level is output to the first node N1.
Specifically, when the input signal terminal IN provides a low level, the first transistor M1 is turned on by the low level, and a high level provided by the high-level signal terminal VGH is transmitted to the output signal terminal OUT through the turned-on first transistor M1, so that the output signal terminal OUT outputs a high-level signal opposite to the input signal level, and at the same time, the control module 1 outputs a high level to the first node N1, so that the second transistor M2 is turned off, thereby preventing the second transistor M2 from transmitting a signal to the output signal terminal OUT, and improving the stability of the output signal terminal OUT outputting the high level; when the input signal terminal IN provides a high level, the control module 1 outputs a low level to the first node N1, the second transistor M2 is turned on by the low level of the first node N1, and the low level provided by the low level signal terminal VGL is transmitted to the output signal terminal OUT via the turned-on second transistor M2, so that the output signal terminal OUT outputs a low level signal opposite to the input signal level; based on the above working principle, the inverter realizes an inverting function.
In the inverter provided by the embodiment of the invention, by arranging the control module 1, the first transistor M1 and the second transistor M2 of the output transistor can be both arranged as P-type transistors, and one of the first transistor M1 and the second transistor M2 is in an on state and the other is in an off state at the same time under the control of the control module 1, so that the normal operation of the inverter is ensured. Compared with the prior art, the output transistors in the inverter provided by the embodiment of the invention are all P-type transistors, and no N-type transistor is required, so that the manufacturing process is simplified, and the manufacturing cost is reduced. In addition, because the P-type transistor has stronger driving capability, two output transistors in the inverter are both set as the P-type transistors, the driving capability of the inverter can be further improved, and the working performance of the inverter is optimized.
In addition, it should be noted that, in the circuit structure of the inverter, since the requirement on the driving capability of the output transistor is high, the design size of the output transistor is much larger than that of the common control transistor, and therefore, in the embodiment of the present invention, even if some control transistors are additionally arranged in the control module 1, the design sizes of the control transistors are small compared with those of the output transistor, and therefore, the overall design size of the inverter is not greatly affected.
Alternatively, as shown in fig. 2, fig. 2 is another schematic structural diagram of an inverter according to an embodiment of the present invention, and the control module 1 includes a third transistor M3 and a fourth transistor M4; the third transistor M3 is a P-type transistor, the gate of the third transistor M3 is electrically connected to the input signal terminal IN, the first pole of the third transistor M3 is electrically connected to the high potential signal terminal VGH, and the second pole of the third transistor M3 is electrically connected to the first node N1; the fourth transistor M4 is an N-type transistor, the gate of the fourth transistor M4 is electrically connected to the input signal terminal IN, the first pole of the fourth transistor M4 is electrically connected to the low potential signal terminal VGL, and the second pole of the fourth transistor M4 is electrically connected to the first node N1.
Specifically, when the input signal terminal IN provides a low level, the third transistor M3 is turned on by the low level, and the high level provided by the high potential signal terminal VGH is transmitted to the first node N1 via the turned-on third transistor M3, so that the second transistor M2 is ensured to be IN a turned-off state IN the period, thereby ensuring that the output signal terminal OUT outputs a stable high level; when the input signal terminal IN provides a high level, the fourth transistor M4 is turned on by the high level, and a low level provided by the low level signal terminal VGL is transmitted to the first node N1 through the turned-on fourth transistor M4, so that the second transistor M2 is turned on by the low level, and the output signal terminal OUT outputs a stable low level.
Based on the mutual cooperation of the third transistor M3 and the fourth transistor M4, the first node N1 can receive a high level when the input signal terminal IN provides a low level, the second transistor M2 is controlled to be turned off, the first node N1 receives a low level when the input signal terminal IN provides a high level, the second transistor M2 is controlled to be turned on, and the reliability of the output signal terminal OUT is improved.
IN addition, since the first pole of the fourth transistor M4 is electrically connected to the low potential signal terminal VGL, when the input signal terminal IN provides a high level, the stability of the low level received by the first node N1 is high, thereby improving the stability of the operating state of the second transistor.
Optionally, the fourth transistor M4 is an oxide transistor, for example, the fourth transistor M4 is an Indium Gallium Zinc Oxide (IGZO) transistor. Based on the characteristic that the drain current is low when the oxide transistor is in an off state, the fourth transistor M4 is set to be the oxide transistor, and when the fourth transistor M4 is turned off, the influence of the drain current on the potential of the first node N1 can be improved, so that the stability of the operating state of the second transistor M2 is improved, and the stability of the circuit operation is improved.
Optionally, as shown in fig. 3, fig. 3 is a schematic diagram of another structure of the inverter according to the embodiment of the present invention, and the control module 1 further includes a capacitor C, a first plate of the capacitor C is electrically connected to the first node N1, and a second plate of the capacitor C is electrically connected to the output signal terminal OUT. Since the capacitor C has a characteristic of maintaining a constant voltage difference between both ends, when the output signal terminal OUT outputs a stable high level or low level, the capacitor C can stabilize the potential of the first node N1, thereby improving the stability of the operating state of the second transistor M2.
Further, referring to fig. 3 again, the control module 1 further includes a fifth transistor M5, wherein the second pole of the third transistor M3 and the second pole of the fourth transistor M4 are electrically connected to the first node N1 through the fifth transistor M5, respectively, the gate of the fifth transistor M5 is electrically connected to a control signal terminal CL, and the control signal terminal CL is used for providing a turn-on level for driving the fifth transistor M5 to turn on, for example, when the fifth transistor M5 is an N-type transistor, the control signal terminal CL is used for providing a high level, and when the fifth transistor M5 is a P-type transistor, the control signal terminal CL is used for providing a low level. Based on the arrangement of the fifth transistor M5, on one hand, when the input signal terminal IN provides a high level, even if the potential of the first node N1, i.e., the second pole of the fifth transistor M5 fluctuates due to the influence of the leakage current, the first pole of the fifth transistor M5 receives a stable low level, so that the output signal terminal OUT can be ensured to output a low level, and the potential of the low level is not higher than VGL-VTH(ii) a On the other hand, when the level output by the output signal terminal OUT changes from high level to low level, the potential of the first node N1 is pulled down accordingly, when the potential of the first node N1 is pulled down to be less than the gate potential of the fifth transistor M5, the fifth transistor M5 is turned off, and the path between the first node N1 and the second node N2 is broken, so that the second transistor M2 is turned on more completely under the action of the lower low level pulled down by the first node N1, and the low level provided by the low-level signal terminal VGL is better transmitted to the output signal terminal OUT, thereby optimizing the signal output capability of the output signal terminal OUT.
Optionally, referring to fig. 3 again, the fifth transistor M5 is a P-type transistor, and the control signal terminal CL is multiplexed as the low-potential signal terminal VGL. With the arrangement, on one hand, the manufacturing process of the P-type transistor is simpler than that of the N-type transistor, and the process complexity of the inverter can be simplified by arranging the fifth transistor M5 as the P-type transistor; on the other hand, when the fifth transistor M5 is a P-type transistor, its on level is low, so the low level signal terminal VGL is only required to be multiplexed as the control signal terminal CL, and an additional control signal terminal CL is not required to be provided, thereby reducing the overall design size of the inverter.
Further, referring to fig. 3 again, in order to improve the operation stability of the fifth transistor M5, the fifth transistor M5 includes a first sub-transistor M51 and a second sub-transistor M52 connected in series, wherein a gate of the first sub-transistor M51 is shared with a gate of the second sub-transistor M52, or a gate of the first sub-transistor M51 and a gate of the second sub-transistor M52 are electrically connected to the same control signal terminal CL.
Alternatively, as shown in fig. 4, fig. 4 is a schematic diagram of another structure of the inverter according to the embodiment of the invention, the low-potential signal terminal VGL includes a first low-potential signal terminal VGL1 and a second low-potential signal terminal VGL2, and the voltage of the first low-potential signal provided by the first low-potential signal terminal VGL1 is VL1The voltage of the second low potential signal provided by the second low potential signal terminal VGL2 is VL2，VL1＜VL2(ii) a A first electrode of the fourth transistor M4 is electrically connected to the first low potential signal terminal VGL1, and a first electrode of the second transistor M2 is electrically connected to the second low potential signal terminal VGL 2. With this arrangement, when the input signal terminal IN provides a high level, the first node N1 can receive the first low signal with a lower level, so that the second transistor M2 is turned on more fully, and the second low signal is transmitted to the output signal terminal OUT better.
Optionally, as shown IN fig. 5, fig. 5 is another structural schematic diagram of the inverter according to the embodiment of the present invention, the inverter further includes an auxiliary output module 3, the auxiliary output module 3 is electrically connected to the input signal terminal IN, the low potential signal terminal VGL, and the output signal terminal OUT, and when the input signal terminal IN provides a high level, the auxiliary output module 3 transmits the low level provided by the low potential signal terminal VGL to the output signal terminal OUT. When the input signal terminal IN provides a high level, if the potential of the first node N1 changes due to the influence of leakage and other factors, the second transistor M2 is turned off, and by providing the auxiliary output module 3, the auxiliary output module 3 can be used to transmit a low level to the output signal terminal OUT, so that the output signal terminal OUT can still output a low level, and the working stability of the inverter is improved.
Alternatively, as shown IN fig. 6, fig. 6 is a schematic diagram of another structure of the inverter according to the embodiment of the invention, the auxiliary output module 3 includes a sixth transistor M6, the sixth transistor M6 is an N-type transistor, a gate of the sixth transistor M6 is electrically connected to the input signal terminal IN, a first pole of the sixth transistor M6 is electrically connected to the low-potential signal terminal VGL, and a second pole of the sixth transistor M6 is electrically connected to the output signal terminal OUT. Specifically, when the input signal terminal IN provides a high level, the sixth transistor M6 is turned on by the high level, and a low level provided by the low potential signal terminal VGL is transmitted to the output signal terminal OUT via the turned-on sixth transistor M6, thereby improving the reliability of the output signal terminal OUT outputting a low level.
Alternatively, the sixth transistor M6 is an oxide transistor, for example, the sixth transistor M6 is an Indium Gallium Zinc Oxide (IGZO) transistor. By providing the sixth transistor M6 as an oxide transistor based on the characteristic that the leakage current is low when the oxide transistor is in the off state, the influence of the leakage current on the signal output from the output signal terminal OUT can be improved when the sixth transistor M6 is in the off state.
An embodiment of the present invention further provides a driving method of an inverter, which is applied to the inverter, as shown in fig. 7, where fig. 7 is a flowchart of the driving method provided in the embodiment of the present invention, and the driving method includes:
step S1: when the input signal terminal IN provides a low level, the first transistor M1 is turned on, so that the high level provided by the high-level signal terminal VGH is transmitted to the output signal terminal OUT, and the control module 1 outputs a high level to the first node N1, so that the second transistor M2 is turned off.
Step S2: when the input signal terminal IN provides a high level, the control module 1 outputs a low level to the first node N1 to control the second transistor M2 to be turned on, so that the low level provided by the low level signal terminal VGL is transmitted to the output signal terminal OUT.
By adopting the driving method provided by the embodiment of the invention, on the premise of realizing the phase inversion function, the first transistor M1 and the second transistor M2 which are used as output transistors in the inverter can be both set as P-type transistors, compared with the prior art, the output transistors do not need to be set as N-type transistors, the manufacturing process is simplified, and the manufacturing cost is reduced, and moreover, because the mobility and the driving capability of the P-type transistors are higher, the design sizes of the first transistor M1 and the second transistor M2 do not need to be additionally increased, so that the influence of the first transistor M1 and the second transistor M2 on the whole design size of the inverter is avoided, and the narrow-frame design of the display device is more favorably realized.
The embodiment of the present invention further provides a gate driving circuit, which includes the inverter, wherein a specific structure of the inverter has been described in detail in the above embodiment, and is not described herein again.
Because the gate driving circuit provided by the embodiment of the invention comprises the inverter, the gate driving circuit provided by the embodiment of the invention can simplify the manufacturing process, reduce the manufacturing cost and reduce the overall design size.
As shown in fig. 8, fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device includes the gate driving circuit 100. Of course, the display device shown in fig. 8 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
Since the display device provided by the embodiment of the invention includes the gate driving circuit 100, the display device provided by the embodiment of the invention simplifies the manufacturing process, reduces the manufacturing cost, reduces the overall design size, and is beneficial to the narrow frame design of the display device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. An inverter, comprising:
an input signal terminal and an output signal terminal;
the control module is electrically connected with the input signal end, the high potential signal end, the low potential signal end and the first node respectively;
the output module comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are both P-type transistors; the grid electrode of the first transistor is electrically connected with the input signal end, the first electrode of the first transistor is electrically connected with the high-potential signal end, and the second electrode of the first transistor is electrically connected with the output signal end; a grid electrode of the second transistor is electrically connected with the first node, a first electrode of the second transistor is electrically connected with the low-potential signal end, and a second electrode of the second transistor is electrically connected with the output signal end;
the control module is used for: outputting a high level to the first node when the input signal terminal provides a low level, and outputting a low level to the first node when the input signal terminal provides a high level;
further comprising:
and the auxiliary output module is respectively electrically connected with the input signal end, the low potential signal end and the output signal end, and when the input signal end provides a high level, the auxiliary output module enables a low level provided by the low potential signal end to be transmitted to the output signal end.
2. The inverter according to claim 1, wherein the control module comprises:
a third transistor, wherein the third transistor is a P-type transistor, a gate of the third transistor is electrically connected to the input signal terminal, a first electrode of the third transistor is electrically connected to the high potential signal terminal, and a second electrode of the third transistor is electrically connected to the first node;
the fourth transistor is an N-type transistor, a grid electrode of the fourth transistor is electrically connected with the input signal end, a first electrode of the fourth transistor is electrically connected with the low-potential signal end, and a second electrode of the fourth transistor is electrically connected with the first node.
3. The inverter according to claim 2, wherein the fourth transistor is an oxide transistor.
4. The inverter of claim 2, wherein the control module further comprises:
and the first pole plate of the capacitor is electrically connected with the first node, and the second pole plate of the capacitor is electrically connected with the output signal end.
5. The inverter of claim 4, wherein the control module further comprises:
and a second pole of the third transistor and a second pole of the fourth transistor are electrically connected to the first node through the fifth transistor, respectively, a gate of the fifth transistor is electrically connected to a control signal terminal, and the control signal terminal is used for providing a conduction level for driving the fifth transistor to be conducted.
6. The inverter according to claim 5, wherein the fifth transistor is a P-type transistor, and the control signal terminal is multiplexed as the low potential signal terminal.
7. The inverter according to claim 5, wherein the fifth transistor comprises a first sub-transistor and a second sub-transistor connected in series, wherein a gate of the first sub-transistor is common to a gate of the second sub-transistor, or wherein the gate of the first sub-transistor and the gate of the second sub-transistor are electrically connected to the same control signal terminal.
8. The inverter according to claim 2,
the low potential signal terminal comprises a first low potential signal terminal and a second low potential signal terminal, and the voltage of a first low potential signal provided by the first low potential signal terminal is VL1The voltage of the second low potential signal provided by the second low potential signal terminal is VL2，VL1＜VL2；
A first electrode of the fourth transistor is electrically connected to the first low potential signal terminal, and a first electrode of the second transistor is electrically connected to the second low potential signal terminal.
9. The inverter of claim 8, wherein the auxiliary output module comprises:
the sixth transistor is an N-type transistor, a gate of the sixth transistor is electrically connected with the input signal end, a first electrode of the sixth transistor is electrically connected with the low potential signal end, and a second electrode of the sixth transistor is electrically connected with the output signal end.
10. The inverter according to claim 9, wherein the sixth transistor is an oxide transistor.
11. A driving method of an inverter, applied to the inverter according to claim 1, the driving method comprising:
when the input signal end provides a low level, the first transistor is conducted, so that the high level provided by the high-potential signal end is transmitted to the output signal end, and the control module outputs the high level to the first node, so that the second transistor is cut off;
when the input signal end provides a high level, the control module outputs a low level to the first node, controls the second transistor to be conducted, and enables the low level provided by the low level signal end to be transmitted to the output signal end.
12. A gate drive circuit comprising the inverter according to any one of claims 1 to 10.
13. A display device comprising the gate driver circuit according to claim 12.
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| CN112785959B (en) * | 2021-02-05 | 2024-05-10 | 厦门天马微电子有限公司 | Inverter, driving method thereof, driving circuit and display panel |
| CN117176138A (en) * | 2022-05-27 | 2023-12-05 | 华为技术有限公司 | Logic gate circuit, integrated circuit and electronic device |
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| JP4785271B2 (en) * | 2001-04-27 | 2011-10-05 | 株式会社半導体エネルギー研究所 | Liquid crystal display device, electronic equipment |
| JP5008032B2 (en) * | 2007-08-30 | 2012-08-22 | ソニーモバイルディスプレイ株式会社 | Delay circuit, semiconductor control circuit, display device, and electronic device |
| JP5678730B2 (en) * | 2010-03-30 | 2015-03-04 | ソニー株式会社 | Inverter circuit and display device |
| KR101674690B1 (en) * | 2010-03-30 | 2016-11-09 | 가부시키가이샤 제이올레드 | Inverter circuit and display |
| CN103268749B (en) * | 2012-11-21 | 2015-04-15 | 上海天马微电子有限公司 | Phase inverter, AMOLED (Active Matrix/Organic Light Emitting Diode) compensating circuit and display panel |
| US20160240159A1 (en) * | 2013-10-08 | 2016-08-18 | Sharp Kabushiki Kaisha | Shift register and display device |
| CN104134425B (en) * | 2014-06-30 | 2017-02-01 | 上海天马有机发光显示技术有限公司 | OLED phase inverting circuit and display panel |
| CN104517571B (en) * | 2014-12-16 | 2017-06-16 | 上海天马有机发光显示技术有限公司 | Phase inverter and drive circuit, display panel, display device |
| WO2016183687A1 (en) * | 2015-05-20 | 2016-11-24 | Nikolaos Papadopoulos | Circuit, system and method for thin-film transistor logic gates |
| CN104883181B (en) * | 2015-06-10 | 2018-03-16 | 京东方科技集团股份有限公司 | OR-NOT circuit, shift register, array base palte and display device |
| KR102613407B1 (en) * | 2015-12-31 | 2023-12-13 | 엘지디스플레이 주식회사 | display apparatus, gate driving circuit and driving method thereof |
| CN106782399A (en) * | 2017-01-11 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
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