CN111208862B

CN111208862B - Three-dimensional maximum power point tracking method

Info

Publication number: CN111208862B
Application number: CN202010038263.7A
Authority: CN
Inventors: 周泽坤; 王佳文; 李响; 石跃; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-01-14
Filing date: 2020-01-14
Publication date: 2021-07-02
Anticipated expiration: 2040-01-14
Also published as: CN111208862A

Abstract

A three-dimensional maximum power point tracking method is suitable for an energy collection system of a power stage using a charge pump, after the energy collection system is started, an output capacitor is periodically charged through the charge pump, and the gain, the inter-stage capacitance value and the working frequency of the charge pump are adjusted through a hill climbing algorithm in each period; the charge pump charges an output capacitor with maximum gain in the first period, the interstage capacitance value and the working frequency of the charge pump are sequentially adjusted through a hill climbing algorithm, and the gain, the interstage capacitance value and the working frequency of the charge pump are sequentially adjusted through the hill climbing algorithm from the second period according to the comparison result of the output voltage peak values of the energy collection system in the current period and the previous period; meanwhile, judging whether the system is frozen or not in each period; after the system is frozen for the standby time, the next period is adjusted; and setting the gain, the interstage capacitance value and the working frequency of the charge pump obtained according to the last period as final maximum power point parameters.

Description

Three-dimensional maximum power point tracking method

Technical Field

The invention belongs to the field of energy collection, and particularly relates to a three-dimensional maximum power point tracking method based on a hill climbing algorithm.

Background

With the rise of emerging technologies for portable devices such as wireless sensors, automotive electronics, security systems, environmental detection sensors, etc., energy harvesting systems have become one of the most efficient solutions to reduce the power consumption of these systems and increase their standby time. Because all batteries have certain internal resistance, when the equivalent input impedance of the rear-stage circuit is matched with the internal resistance of the batteries, the rear-stage circuit can obtain the most energy, and the concept of maximum power point tracking is introduced. Through a proper maximum power point tracking algorithm, the system can work at the maximum power point, so that the efficiency of the energy collection system is improved.

Many maximum power point tracking methods have been proposed, and different methods have advantages and disadvantages, and have energy sources suitable for them. Currently, the most common maximum power point tracking algorithms in academia include an open-circuit voltage algorithm, a short-circuit current algorithm, a hill climbing algorithm, a frequency fitting algorithm, and the like. Among them, the hill climbing algorithm is widely used due to its simplicity and easy operability, and many maximum power point tracking principles based on hill climbing have been developed to maximally convert harvested energy according to load demands. However, the current maximum power point tracking method based on the hill climbing algorithm generally adopts an energy source of a DC-DC converter based on a power level, and generally cannot adjust a charge pump gain in the energy source, so that the existing hill climbing algorithm is generally one-dimensional or two-dimensional, and has the problem of poor maximum power point tracking accuracy and range.

Disclosure of Invention

Aiming at the problems of low precision and narrow application range of the maximum power point tracking method in the existing energy collection field, the invention provides a three-dimensional maximum power point tracking method which can be suitable for an energy collection system using a charge pump in a power stage.

The technical scheme of the invention is as follows:

a three-dimensional maximum power point tracking method is suitable for an energy collection system of which a power stage uses a charge pump, and when the input resistance of the power stage is equal to the internal resistance of the energy collection system, the energy collection system works at a maximum power point;

the three-dimensional maximum power point tracking method comprises the following steps:

step one, the charge pump charges an output capacitor of the energy collection system with maximum gain, so that the output voltage of the energy collection system rises to reach a stabilized voltage value, and the energy collection system is started;

after the starting is finished, the energy collection system charges an output capacitor periodically through the charge pump, and the gain, the interstage capacitance value and the working frequency of the charge pump are adjusted through a hill climbing algorithm in each period;

in the first period, the charge pump charges an output capacitor of the energy collection system with maximum gain, and the interstage capacitance value and the working frequency of the charge pump are sequentially adjusted through a hill climbing algorithm;

in the ith period, comparing the output voltage peak value of the energy collection system in the current period with the output voltage peak value of the energy collection system in the last period, and sequentially adjusting the gain, the interstage capacitance value and the working frequency of the charge pump through a hill climbing algorithm according to the comparison result, wherein i is a positive integer greater than 1;

if the output voltage peak value of the energy collection system in the current period is larger than the output voltage peak value of the energy collection system in the last period, increasing the gain, the interstage capacitance value and the working frequency of the charge pump;

if the output voltage peak value of the energy collection system in the current period is smaller than the output voltage peak value of the energy collection system in the last period, reducing the gain, the interstage capacitance value and the working frequency of the charge pump;

step three, in each period of the step two, when the jth period detects one of the following three conditions, freezing the energy collection system; wherein j is a positive integer, freezing the energy collection system by operating the energy collection system at the gain, inter-stage capacitance, and operating frequency of the charge pump determined the last cycle before freezing, and then proceeding to step four;

the first condition is as follows: at least one of a gain, an inter-stage capacitance value, and an operating frequency of the charge pump are varied back and forth between fixed values over a plurality of successive cycles;

the second condition is that at least one of the gain, the interstage capacitance value and the working frequency of the charge pump exceeds the adjusting range;

in the third case, when at least one of the gain, the interstage capacitance value and the working frequency of the charge pump reaches the maximum value or the minimum value, the maximum power point is still not reached;

step four, setting the freezing standby time of the energy collection system, returning to the step two after the energy collection system is frozen for the standby time, entering the (j + 1) th period, and continuously adjusting the gain, the interstage capacitance value and the working frequency of the charge pump through a hill climbing algorithm;

and fifthly, after each period of the three-dimensional maximum power point tracking method is completed once, setting the gain, the inter-stage capacitance value and the working frequency of the charge pump obtained according to the last period as parameters of the maximum power point determined by the three-dimensional maximum power point tracking method.

Specifically, the number of steps of adjustment of the capacitance is less than the number of steps of adjustment of the frequency in each cycle.

Specifically, the charge pump is a gain-adjustable charge pump, and comprises a first boost module, a second boost module, a third boost module, a fourth boost module and a gain selection module;

the first boosting module comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first capacitor, a second capacitor, a first transmission gate and a second transmission gate,

the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrodes of the fifth NMOS tube and the sixth NMOS tube and an input signal, the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube and one end of the first capacitor and serves as the first output end of the first boosting module after passing through the first transmission gate, and the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and one end of the second capacitor and serves as the second output end of the first boosting module after passing through the second transmission gate;

the drain electrode of the third NMOS tube is connected with the source electrode of the fifth NMOS tube and the other end of the first capacitor, and the source electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and grounded;

the drain electrode of the fourth NMOS tube is connected with the source electrode of the sixth NMOS tube and the other end of the second capacitor;

the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are controlled by a clock signal of the first boosting module;

the first transmission gate and the second transmission gate are controlled by a transmission gate control signal of the first boosting module;

under the control of a clock signal of the first boosting module and a transmission gate control signal of the first boosting module, the first boosting module outputs the input signal after the level of the input signal is increased by two times;

the second boosting module comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a third capacitor, a fourth capacitor, a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, a seventh transmission gate and an eighth transmission gate,

the source electrode of the eighth NMOS tube is connected with the first output end of the first boosting module, the grid electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube and one end of the third capacitor and serves as the first output end of the second boosting module after passing through the third transmission gate, and the drain electrode of the eighth NMOS tube is connected with the grid electrode of the seventh NMOS tube and one end of the fourth capacitor and serves as the second output end of the second boosting module after passing through the fourth transmission gate;

the source electrode of the seventh NMOS tube is connected with the second output end of the first boosting module;

a source electrode of the ninth NMOS tube is connected with a drain electrode of the eleventh NMOS tube and the other end of the third capacitor, and a drain electrode of the ninth NMOS tube is connected with the input signal after passing through a fifth transmission gate on one hand and is connected with a first output end of the first boosting module after passing through a sixth transmission gate on the other hand;

a source electrode of the tenth NMOS transistor is connected to a drain electrode of the twelfth NMOS transistor and the other end of the fourth capacitor, and a drain electrode of the tenth NMOS transistor is connected to the input signal through the seventh transmission gate, and is connected to the second output end of the first boost module through the eighth transmission gate;

the source electrodes of the eleventh NMOS tube and the twelfth NMOS tube are grounded;

a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor are controlled by the clock signal of the second boosting module;

the third transmission gate and the fourth transmission gate are controlled by the transmission gate control signal of the second boosting module;

the fifth transmission gate and the seventh transmission gate are controlled by the first gain control signal, and the sixth transmission gate and the eighth transmission gate are controlled by the second gain control signal;

when the first gain control signal is effective, the second boost module boosts the level of the input signal by three times under the control of the clock signal of the second boost module and the transmission gate control signal of the second boost module and outputs the boosted input signal;

when a second gain control signal is effective, the second boost module boosts the level of the input signal by four times under the control of a clock signal of the second boost module and a transmission gate control signal of the second boost module and outputs the boosted input signal;

the third boosting module comprises a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a fifth capacitor, a sixth capacitor, a first PMOS transistor, a second PMOS transistor, a ninth transmission gate, a tenth transmission gate, an eleventh transmission gate and a twelfth transmission gate,

a source electrode of the fourteenth NMOS tube is connected with the first output end of the second boosting module, a grid electrode of the fourteenth NMOS tube is connected with a drain electrode of the thirteenth NMOS tube, one end of a fifth capacitor and the drain electrode of the first PMOS tube, and a drain electrode of the fourteenth NMOS tube is connected with a grid electrode of the thirteenth NMOS tube, one end of a sixth capacitor and the drain electrode of the second PMOS tube

The source electrode of the thirteenth NMOS tube is connected with the second output end of the second boosting module;

a source electrode of the first PMOS tube is used as a first output end of the third boosting module, and a source electrode of the second PMOS tube is used as a second output end of the third boosting module;

the drain electrode of the fifteenth NMOS tube is connected with the other end of the fifth capacitor, is connected with the first output end of the second boosting module after passing through the ninth transmission gate and the tenth transmission gate in sequence, and the source electrode of the fifteenth NMOS tube is connected with the source electrode of the sixteenth NMOS tube and is grounded;

the drain electrode of the sixteenth NMOS tube is connected with the other end of the sixth capacitor, sequentially passes through the eleventh transmission gate and the twelfth transmission gate and then is connected with the second output end of the second boosting module;

a fifteenth NMOS transistor, a sixteenth NMOS transistor, a ninth transmission gate and an eleventh transmission gate are controlled by the clock signal of the third boosting module;

the first PMOS tube and the second PMOS tube are controlled by a transmission gate control signal of the third boosting module;

the tenth transmission gate and the twelfth transmission gate are controlled by a third gain control signal;

under the control of the third gain control signal, the clock signal of the third boost module and the transmission gate control signal of the third boost module, the third boost module boosts the level of the input signal by six times or eight times and outputs the boosted level;

the fourth boosting module comprises a seventeenth NMOS transistor, an eighteenth NMOS transistor, a seventh capacitor, an eighth capacitor, a thirteenth transmission gate, a fourteenth transmission gate, a fifteenth transmission gate, a sixteenth transmission gate, a seventeenth transmission gate, an eighteenth transmission gate, a nineteenth transmission gate, a twentieth transmission gate, a twenty-first transmission gate and a twenty-second transmission gate,

one end of a thirteenth transmission gate is connected with the input signal, and the other end of the thirteenth transmission gate is connected with one end of a seventh capacitor and is used as a first output end of the fourth boosting module after passing through a fourteenth transmission gate;

one end of a fifteenth transmission gate is connected with the input signal, and the other end of the fifteenth transmission gate is connected with one end of an eighth capacitor and is used as a second output end of the fourth boosting module after passing through a sixteenth transmission gate;

one end of a seventeenth transmission gate is connected with the drain electrode of the seventeenth NMOS tube and the other end of the seventh capacitor, and the other end of the seventeenth transmission gate is connected with the first output end of the second boosting module through an eighteenth transmission gate on one hand and is connected with the first output end of the third boosting module through a nineteenth transmission gate on the other hand;

one end of a twentieth transmission gate is connected with the drain electrode of the eighteenth NMOS tube and the other end of the eighth capacitor, and the other end of the twentieth transmission gate is connected with the second output end of the second boosting module through the twenty-first transmission gate on one hand and connected with the second output end of the third boosting module through the twenty-twelfth transmission gate on the other hand;

the source electrodes of the seventeenth NMOS tube and the eighteenth NMOS tube are grounded;

a thirteenth transmission gate, a fifteenth transmission gate, a seventeenth transmission gate, a twentieth transmission gate, a seventeenth NMOS transistor and an eighteenth NMOS transistor are controlled by a clock signal of the fourth boosting module;

a fourteenth transmission gate and a sixteenth transmission gate are controlled by a transmission gate control signal of the fourth boosting module;

the eighteenth transmission gate and the twenty-first transmission gate are controlled by a tenth gain control signal;

the nineteenth transmission gate and the twenty-second transmission gate are controlled by a fourth gain control signal;

when a fourth gain control signal is effective, the fourth boost module boosts the level of the input signal by seven times or nine times under the control of a clock signal and a transmission gate control signal of the fourth boost module and outputs the boosted level;

when a tenth gain control signal is effective, the fourth boost module boosts the level of the input signal by four times or five times under the control of a clock signal and a transmission gate control signal of the fourth boost module and outputs the boosted level;

the gain selection module comprises a twenty-third transmission gate, a twenty-fourth transmission gate, a twenty-fifth transmission gate, a twenty-sixth transmission gate, a twenty-seventh transmission gate, a twenty-eighth transmission gate, a twenty-ninth transmission gate, a thirty-first transmission gate and a thirty-first transmission gate,

one end of the twenty-third transmission gate is connected with the input signal, and the other end of the twenty-third transmission gate is connected with the output end of the charge pump and is controlled by a fifth gain control signal;

one end of a twenty-fourth transmission gate, one end of a twenty-fifth transmission gate, one end of a twenty-sixth transmission gate and one end of a twenty-seventh transmission gate are respectively connected with the first output end of the first boosting module, the first output end of the second boosting module, the first output end of the third boosting module and the first output end of the fourth boosting module, and the other ends of the twenty-fourth transmission gate, the twenty-fifth transmission gate, the twenty-sixth transmission gate and the twenty-seventh transmission gate are respectively connected with the output end of;

one end of each of the twenty-eighth transmission gate, the twenty-ninth transmission gate, the thirty-eighth transmission gate and the thirty-first transmission gate is connected with the second output end of the first boosting module, the second output end of the second boosting module, the second output end of the third boosting module and the second output end of the fourth boosting module respectively, and the other end of each of the twenty-eighth transmission gate, the twenty-ninth transmission gate, the thirty-eighth transmission gate and the thirty-first transmission gate is connected with the output end of the charge pump;

the twenty-fourth transmission gate and the twenty-eighth transmission gate are controlled by a sixth gain control signal;

the twenty-fifth transmission gate and the twenty-ninth transmission gate are controlled by a seventh gain control signal;

the twenty-sixth transmission gate and the thirtieth transmission gate are controlled by an eighth gain control signal;

the twenty-seventh transmission gate and the thirty-first transmission gate are controlled by a ninth gain control signal;

and the gain selection module selects a signal obtained by raising the level of the input signal by any multiple of one time to nine times as the output signal of the charge pump under the control of a fifth gain control signal to a ninth gain control signal.

Specifically, the charge pump further includes a clock generation module, and the clock generation module is configured to generate non-overlapping clock signals as clock signals and transmission gate control signals of the first boost module, the second boost module, the third boost module, and the fourth boost module.

Specifically, the charge pump comprises a plurality of first boosting modules, a plurality of second boosting modules, a plurality of third boosting modules and a plurality of fourth boosting modules, and output signals of each of the first boosting modules, the second boosting modules, the third boosting modules and the fourth boosting modules are superposed through the gain selection module.

The invention has the beneficial effects that: the invention adjusts the input impedance of the power level from three dimensions, thereby enabling the input impedance to be highly matched with the internal resistance of the energy source, and the tracking precision to be as high as 99.3%; the three parameters which are adjusted successively are the gain multiple of the charge pump, the capacitance of the charge pump and the frequency of the charge pump respectively, and meanwhile, the system is frozen under three conditions, so that the problem that the system oscillates near a stable point in a hill climbing algorithm is solved.

Drawings

Fig. 1 is a frame diagram of a tracking system of a three-dimensional maximum power point tracking method according to the present invention.

Fig. 2 is a flowchart of a three-dimensional maximum power point tracking method according to the present invention.

Fig. 3 shows an implementation form of a gain-adjustable charge pump used in an embodiment of the three-dimensional maximum power point tracking method according to the present invention.

Fig. 4 is an implementation form of a gain selection module in the charge pump with adjustable gain in the embodiment.

Fig. 5 is a charge pump control bit to gain correspondence table in the gain-adjustable charge pump according to the embodiment.

Fig. 6 is a waveform diagram of main nodes of the clock generation module in the embodiment.

Detailed Description

The invention is further illustrated with reference to the figures and the specific examples.

Fig. 1 is a frame diagram of a tracking system adopted by a three-dimensional maximum power point tracking method according to the present invention, in which a voltage detector is used to collect a peak value of an output voltage of an energy collection system in each period and compare the peak value with a peak value of an output voltage of an energy collection system in a previous period, and a digital controller adjusts a gain, a capacitance value, and an operating frequency of a charge pump according to a comparison result, so as to adjust an input impedance of a power stage, thereby highly matching the input impedance of an energy source. The three-dimensional maximum power point tracking method provided by the invention adjusts the input resistance of the power stage to be equal to the internal resistance of the energy source by adjusting the three parameters of the gain, the capacitance and the working frequency of the charge pump, so that the power of the energy collection system reaches the maximum.

The essence of the maximum power point tracking algorithm is to find the maximum power point, and the following description is given by taking an energy collection system with constant on-time COT as an example, that is, charges are transported to the output capacitor through the charge pump in a fixed time in each period, so the present embodiment uses the magnitude of voltage increase on the output capacitor in each constant on-time as the basis for determining. In other types of energy collection systems, three-dimensional maximum power point tracking is performed based on the magnitude of voltage increase on the output capacitor within the turn-on time of each period.

Before the output voltage of the energy collection system is raised to a stable value, such as 3.3V, the three-dimensional maximum power point tracking system stops working. When the system is started, the reconfigurable charge pump of the energy collection system keeps the maximum multiple gain to charge the output capacitor until the output reaches 3.3V.

And after the starting process is finished, the maximum power point tracking system starts to work. And in each starting period, the voltage detection circuit collects the output voltage peak value of the energy collection system for comparison with the output voltage peak value of the energy collection system in the previous period. During the non-start time of each period, the charge pump can transmit energy to the standby energy storage capacitor, the standby energy storage capacitor is a capacitor which is connected with the load in parallel, when the output is not idle, the charge pump charges the energy storage capacitor to store the energy, and when the output cannot meet the load requirement, the standby energy storage capacitor can supply power. After comparing the sampling voltages of two adjacent cycles each time, if the sampling voltage of the current cycle is greater than the sampling voltage of the previous cycle, the gain, the inter-stage capacitance or the frequency of the charge pump needs to be increased, otherwise, the three parameters are decreased to adjust the equivalent input impedance.

In the first period, the maximum power point tracking system keeps the gain unchanged and is always the maximum time, on the basis, the inter-stage capacitance value is adjusted by using a hill climbing algorithm, finally, the working frequency is adjusted, and in the first period, the inter-stage capacitance value and the working frequency of the charge pump can be adjusted to be increased or decreased arbitrarily. And starting from the second period, entering a normal maximum power point tracking process, and adjusting the gain, the inter-stage capacitance or the frequency of the charge pump according to a comparison structure of the output voltage peak values of the system in the second period and the upper period.

The maximum power point tracking algorithm flow chart based on the hill climbing algorithm is shown in fig. 2, and in a complete maximum power point tracking large period, the gain of a charge pump is firstly adjusted each time, then the inter-stage capacitance value is changed, and finally the working frequency is changed. Fig. 2 shows the adjustment flow of the charge pump gain N in detail, and the process of adjusting the inter-stage capacitance C and the operating frequency f is similar to the gain N.

In an embodiment, the number of adjustment steps of the capacitor is set to be less than the number of adjustment steps of the frequency, because the finer the division of the capacitor is, the more the number of driving switches is required, and the more redundant the control of the whole system is.

The hill climbing algorithm has the problem that the system oscillates around a stable point, and the solution of the invention is to freeze the energy collection system in each cycle as soon as one of the following three conditions is detected, in such a way that the energy collection system is operated at the gain, the inter-stage capacitance value and the operating frequency of the charge pump determined in the last cycle before freezing.

The following situations are: the entire system is frozen as long as the system detects that the change in at least one of the three parameters of the charge pump gain, inter-stage capacitance and operating frequency is varied back and forth between fixed values over a period of time. In addition to the parameter oscillating back and forth causing freezing, there are two cases: if the maximum power point exceeds the regulation range, the system is also required to be frozen, and the three-dimensional maximum power point tracking method provided by the invention regulates the maximum power point by regulating three parameters of the gain, the capacitance and the working frequency of the charge pump, so that only whether at least one of the gain, the inter-stage capacitance and the working frequency of the charge pump exceeds the regulation range is required to be judged. There are also cases three: the system also needs to be frozen when at least one of the gain, the inter-stage capacitance value and the operating frequency of the charge pump reaches a maximum or minimum value, and is still determined by the maximum power point tracking system to be not the maximum power point.

After the system is frozen, the next maximum power point tracking algorithm is executed after a relatively long time, the relatively long time is the standby time of the frozen maximum power point tracking system in the system, and the standby time is set according to the change of an energy source, the load and the like. After the system is frozen for the standby time, the adjustment of the next period is continuously carried out in the last period before the system is frozen, for example, the jth period is frozen, after the standby time, the jth +1 period is continuously carried out, and the gain, the interstage capacitance value and the working frequency of the charge pump are sequentially adjusted according to the comparison result of the output voltage peak values of the system in the jth +1 period and the jth period.

And setting a maximum power point tracking large period according to the change of the energy source or self, wherein after the maximum power point tracking large period is finished, a period of time for only working the charge pump exists, and the parameters are set according to the maximum power point parameters obtained by the maximum power point tracking system. The method for tracking the maximum power point once is carried out in each maximum power point tracking large period.

The charge pump used in the invention is a gain-adjustable charge pump, and as shown in fig. 3, an implementation form of the gain-adjustable charge pump is provided, and the gain-adjustable charge pump comprises a gain selection module and four boosting modules, wherein in each boosting module, a group of NMOS body diodes of a cross-coupled structure is used for pre-charging a capacitor, and then the voltage on the capacitor is raised through the control of a non-overlapped clock signal, so that the improvement of different multiples of output voltage is realized.

As shown in fig. 3(a), the first voltage boost module includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first capacitor C11, a second capacitor C12, a first transmission gate and a second transmission gate, wherein the source of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2, the drains of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6, and the input signal VIN, the drain of the first voltage boost module is connected to the gate of the second NMOS transistor NM2, one end of the first capacitor C11 and is used as a first output terminal of the first voltage boost module after passing through the first transmission gate, and the gate of the first voltage boost module is connected to the drain of the second NMOS transistor NM2, one end of the second capacitor C12 and is used as a second output terminal of the first voltage boost module after passing through the second transmission gate; the drain of the third NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5 and the other end of the first capacitor C11, and the source thereof is connected to the source of the fourth NMOS transistor NM4 and grounded; the drain of the fourth NMOS transistor NM4 is connected to the source of the sixth NMOS transistor NM6 and the other end of the second capacitor C12.

The third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6 are controlled by clock signals clk01, clk02, clk11, and clk12 of the first voltage boosting module, as shown in fig. 3(a), the clock signal clk01 is connected to a gate of the fourth NMOS transistor NM4, the clock signal clk02 is connected to a gate of the third NMOS transistor NM3, the clock signal clk11 is connected to a gate of the fifth NMOS transistor NM5, and the clock signal clk12 is connected to a gate of the sixth NMOS transistor NM 6.

The first transmission gate and the second transmission gate are controlled by transmission gate control signals gate11, -gate11, gate12 and-gate 12 of the first boosting module; the transmission gate is composed of an NMOS (N-channel metal oxide semiconductor) tube and a PMOS (P-channel metal oxide semiconductor) tube, a transmission gate control signal gate11 is connected with the grid electrode of the NMOS tube in the first transmission gate, a transmission gate control signal gate11 is connected with the grid electrode of the PMOS tube in the first transmission gate, a transmission gate control signal gate12 is connected with the grid electrode of the NMOS tube in the second transmission gate, and a transmission gate control signal gate12 is connected with the grid electrode of the PMOS tube in the second transmission gate.

Under the control of a clock signal of the first boost module and a transmission gate control signal of the first boost module, the first boost module increases the level of the input signal VIN by two times and outputs the increased level.

As shown in fig. 3(b), the second boost module includes a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a third capacitor C21, a fourth capacitor C22, a third transfer gate, a fourth transfer gate, a fifth transfer gate, a sixth transfer gate, a seventh transfer gate, and an eighth transfer gate, a source of the eighth NMOS transistor NM8 is connected to the first output terminal of the first boost module, a gate thereof is connected to the drain of the seventh NMOS transistor NM7 and one end of the third capacitor C21 and is used as the first output terminal of the second boost module after passing through the third transfer gate, and a drain thereof is connected to the gate of the seventh NMOS transistor NM7 and one end of the fourth capacitor C22 and is used as the second output terminal of the second boost module after passing through the fourth transfer gate; the source electrode of the seventh NMOS tube NM7 is connected with the second output end of the first boosting module; the source of the ninth NMOS transistor NM9 is connected to the drain of the eleventh NMOS transistor NM11 and the other end of the third capacitor C21, and the drain thereof is connected to the input signal VIN through the fifth transfer gate, and is connected to the first output terminal of the first boost module through the sixth transfer gate; a source electrode of the tenth NMOS transistor NM10 is connected to a drain electrode of the twelfth NMOS transistor NM12 and the other end of the fourth capacitor C22, and a drain electrode thereof is connected to the input signal VIN through a seventh transfer gate, and is connected to the second output terminal of the first boost module through an eighth transfer gate; sources of the eleventh and twelfth NMOS transistors NM11 and NM12 are grounded.

The ninth NMOS transistor NM9, the tenth NMOS transistor NM10, the eleventh NMOS transistor NM11, and the twelfth NMOS transistor NM12 are controlled by the clock signals clk11, clk12, clk21, clk22 of the second boost module, as shown in fig. 3(b), the clock signal clk21 is connected to the gate of the ninth NMOS transistor NM9, the clock signal clk22 is connected to the gate of the tenth NMOS transistor NM10, the clock signal clk11 is connected to the gate of the twelfth NMOS transistor NM12, and the clock signal 12 is connected to the gate of the eleventh NMOS transistor NM 11.

The third transmission gate and the fourth transmission gate are controlled by transmission gate control signals gate21, -gate21, gate22 and-gate 22 of the second boosting module; the transmission gate control signal gate21 is connected with the gate of the NMOS transistor in the third transmission gate, the transmission gate control signal gate21 is connected with the gate of the PMOS transistor in the third transmission gate, the transmission gate control signal gate22 is connected with the gate of the NMOS transistor in the fourth transmission gate, and the transmission gate control signal gate22 is connected with the gate of the PMOS transistor in the fourth transmission gate.

The fifth and seventh transmission gates are controlled by the first gain control signals ctl1, -ctl1, and the sixth and eighth transmission gates are controlled by the second gain control signals ctl2, -ctl 2; the first gain control signal ctl1 is connected with the gates of the NMOS transistors in the fifth and seventh transmission gates, the first gain control signal-ctl 1 is connected with the gates of the PMOS transistors in the fifth and seventh transmission gates, the second gain control signal ctl2 is connected with the gates of the NMOS transistors in the sixth and eighth transmission gates, and the second gain control signal-ctl 2 is connected with the gates of the PMOS transistors in the sixth and eighth transmission gates.

When the first gain control signal is valid, the fifth transmission gate and the seventh transmission gate are opened to access the input signal VIN, and the second boost module boosts the output signal of the first boost module by one level of the input signal VIN under the control of the clock signal of the second boost module and the transmission gate control signal of the second boost module and outputs the boosted output signal, that is, the input signal VIN is boosted by three times.

When the second gain control signal is effective, the sixth transmission gate and the eighth transmission gate are opened to access the output signal of the first boosting module, and the second boosting module boosts the output signal of the first boosting module to the level of the output signal of the first boosting module under the control of the clock signal of the second boosting module and the transmission gate control signal of the second boosting module and outputs the output signal, namely, the level of the input signal VIN is raised four times and then output.

As shown in fig. 3(C), the third boost module includes a thirteenth MOS transistor NM13, a fourteenth MOS transistor NM14, a fifteenth NMOS transistor NM15, a sixteenth NMOS transistor NM16, a fifth capacitor C31, a sixth capacitor C32, a first PMOS transistor PM1, a second PMOS transistor PM2, a ninth transmission gate, a tenth transmission gate, an eleventh transmission gate, and a twelfth transmission gate, a source of the fourteenth MOS transistor NM14 is connected to the first output terminal of the second boost module, a gate of the fourteenth MOS transistor NM13 is connected to a drain of the thirteenth MOS transistor NM13, one end of the fifth capacitor C31, and a drain of the first PMOS transistor PM1, a drain of the fourteenth MOS transistor NM13 is connected to a gate of the sixth capacitor C32, and a drain of the second PMOS transistor PM2, and a source of the thirteenth MOS transistor NM13 is connected to the second output terminal of the second boost module; the source electrode of the first PMOS transistor PM1 is used as the first output end of the third boost module, and the source electrode of the second PMOS transistor PM2 is used as the second output end of the third boost module; the drain of the fifteenth NMOS transistor NM15 is connected to the other end of the fifth capacitor C31, and is connected to the first output terminal of the second boost module after passing through the ninth transmission gate and the tenth transmission gate in sequence, and the source thereof is connected to the source of the sixteenth NMOS transistor NM16 and grounded; the drain of the sixteenth NMOS transistor NM16 is connected to the other end of the sixth capacitor C32, and is connected to the second output terminal of the second boost module after passing through the eleventh transmission gate and the twelfth transmission gate in sequence.

The fifteenth NMOS transistor NM15 and the sixteenth NMOS transistor NM16 are controlled by the clock signals clk11 and clk12 of the third boost module, the ninth transmission gate and the eleventh transmission gate are controlled by the clock signals clk31, clk32, -clk31 and-clk 32 of the third boost module, the first PMOS transistor PM1 and the second PMOS transistor PM2 are controlled by the transmission gate control signals-gate 31 and-gate 32 of the third boost module, and the tenth transmission gate and the twelfth transmission gate are controlled by the third gain control signals ctl3 and-ctl 3.

Under the control of a third gain control signal, a clock signal of the third boosting module and a transmission gate control signal of the third boosting module, the third boosting module boosts an output signal of the second boosting module to a level of an output voltage of the second boosting module and outputs the boosted output signal.

As shown in fig. 3(d), the fourth voltage boost module includes a seventeenth NMOS transistor NM17, an eighteenth NMOS transistor NM18, a seventh capacitor C41, an eighth capacitor C42, a thirteenth transmission gate, a fourteenth transmission gate, a fifteenth transmission gate, a sixteenth transmission gate, a seventeenth transmission gate, an eighteenth transmission gate, a nineteenth transmission gate, a twentieth transmission gate, a twenty-first transmission gate, and a twenty-second transmission gate, one end of the thirteenth transmission gate is connected to the input signal VIN, and the other end of the thirteenth transmission gate is connected to one end of the seventh capacitor C41 and passes through the fourteenth transmission gate to serve as a first output end of the fourth voltage boost module; one end of the fifteenth transmission gate is connected with the input signal VIN, and the other end of the fifteenth transmission gate is connected with one end of the eighth capacitor C42 and serves as a second output end of the fourth boosting module after passing through the sixteenth transmission gate; one end of a seventeenth transmission gate is connected with the drain of a seventeenth NMOS transistor NM17 and the other end of a seventh capacitor C41, and the other end of the seventeenth transmission gate is connected with the first output end of the second boost module through an eighteenth transmission gate on one hand and is connected with the first output end of the third boost module through a nineteenth transmission gate on the other hand; one end of the twentieth transmission gate is connected with the drain of the eighteenth NMOS transistor NM18 and the other end of the eighth capacitor C42, and the other end of the twentieth transmission gate is connected with the second output end of the second boosting module through the twenty-first transmission gate on one hand and is connected with the second output end of the third boosting module through the twenty-twelfth transmission gate on the other hand; the sources of the seventeenth NMOS transistor NM17 and the eighteenth NMOS transistor NM18 are grounded.

The thirteenth, fifteenth, seventeenth, and twentieth transmission gates are controlled by the clock signals clk41, -clk41, clk42, and-clk 42 of the fourth voltage boosting module, and the seventeenth and eighteenth NMOS transistors NM17 and NM18 are controlled by the clock signals clk11 and clk12 of the fourth voltage boosting module; the fourteenth transmission gate and the sixteenth transmission gate are controlled by transmission gate control signals gate41, -gate41, gate42 and-gate 42 of the fourth boosting module; the eighteenth and twenty-first transmission gates are controlled by tenth gain control signals ctl10, -ctl 10; the nineteenth and twenty-second transmission gates are controlled by fourth gain control signals ctl4, -ctl 4.

When the fourth gain control signal is valid, the nineteenth transmission gate and the twenty-second transmission gate are opened to access the output signal of the third boost module, and the fourth boost module boosts the input signal VIN by the level of the output signal of the third boost module and outputs the boosted input signal VIN, namely, outputs the boosted input signal VIN by seven times or nine times under the control of the clock signal of the fourth boost module and the control signal of the transmission gate.

When the tenth gain control signal is valid, the eighteenth transmission gate and the twenty-first transmission gate are opened to access the output signal of the second boost module, and the fourth boost module boosts the input signal VIN by the level of the output signal of the second boost module under the control of the clock signal of the fourth boost module and the control signal of the transmission gate and outputs the boosted input signal VIN, that is, the level of the input signal VIN is boosted four times or five times and then output.

As shown in fig. 3(e), the gain selection module includes a twenty-third transmission gate, a twenty-fourth transmission gate, a twenty-fifth transmission gate, a twenty-sixth transmission gate, a twenty-seventh transmission gate, a twenty-eighth transmission gate, a twenty-ninth transmission gate, a thirty-fifth transmission gate, and a thirty-first transmission gate, wherein one end of the twenty-third transmission gate is connected to the input signal VIN, and the other end thereof is connected to the output end of the charge pump, and is controlled by the fifth gain control signals ctl5 and ctl 5; one end of a twenty-fourth transmission gate, one end of a twenty-fifth transmission gate, one end of a twenty-sixth transmission gate and one end of a twenty-seventh transmission gate are respectively connected with the first output end of the first boosting module, the first output end of the second boosting module, the first output end of the third boosting module and the first output end of the fourth boosting module, and the other ends of the twenty-fourth transmission gate, the twenty-fifth transmission gate, the twenty-sixth transmission gate and the twenty-seventh transmission gate are respectively connected with the output end; one end of each of the twenty-eighth transmission gate, the twenty-ninth transmission gate, the thirty-fifth transmission gate and the thirty-first transmission gate is connected with the second output end of the first boosting module, the second output end of the second boosting module, the second output end of the third boosting module and the second output end of the fourth boosting module respectively, and the other end of each of the twenty-eighth transmission gate, the twenty-ninth transmission gate, the thirty-fifth transmission gate and the thirty-fifth transmission gate is connected with the output end of the charge pump; the twenty-fourth and twenty-eighth transmission gates are controlled by sixth gain control signals ctl6, -ctl 6; the twenty-fifth and twenty-ninth transmission gates are controlled by seventh gain control signals ctl7, -ctl 7; the twenty-sixth and thirty-sixth transfer gates are controlled by eighth gain control signals ctl8, -ctl 8; the twenty-seventh transmission gate and the thirty-first transmission gate are controlled by a ninth gain control signal ctl9, -ctl 9; by selecting the fifth gain control signal to the ninth gain control signal, the gain selection module takes the signal obtained by raising the level of the input signal VIN by any multiple of one time to nine times as the output signal of the charge pump.

As can be seen from the above analysis, the first boost module proposed in fig. 3(a) can achieve a voltage boost with a double gain, the second boost module proposed in fig. 3(b) can achieve a voltage boost with a triple or quadruple gain on the basis of the first boost module proposed in fig. 3(a), the third boost module proposed in fig. 3(c) can achieve a voltage boost with a six or eight-fold gain on the basis of the first boost module (fig. 3(a)), the second boost module (fig. 3(b)), and the fourth boost module proposed in fig. 3(d) can achieve a voltage boost with a quadruple, five, seven and nine-fold gain on the basis of the first boost module (fig. 3(a)), the second boost module (fig. 3(b)), and the third boost module (fig. 3 (c)). The specific operating principle of each boost module is analyzed below.

First phase the first boost module proposed in fig. 3(a) operates, initially with a clock signal clk₀₁And clk₀₂Is high, input voltage V_INThe first capacitor C is connected to the body diode of the first NMOS transistor NM1 and the second NMOS transistor NM2₁₁And a second capacitor C₂₂Charging to an input voltage V_INClock signal clk when the voltage on the capacitor cannot ramp₁₁And clk₁₂When the voltage of the upper plate of the capacitor is raised to be twice of the input voltage from low to high, the gate control signal gate is transmitted₁₁And gate₁₂The first transfer gate and the second transfer gate controlled will be opened, thereby 2V will be formed_INOutput voltage V transmitted to first boosting module_O11(V_O12)。

Second stage the second boost module proposed in FIG. 3(b) operates, the output V of the first boost module_O11And V_O12As an input of the second boost module, the operation principle is similar to that of the first boost module in the first stage, and the first gain control signal ctl₁When active, the first gain control signal ctl₁The fifth transmission gate and the seventh transmission gate controlled transmit the input signal V_INVoltage to output V of the second boost module_O21(V_O22) V raised to three times_IN. Second gain control signal ctl₂When active, the second gain control signal ctl₂The controlled sixth transmission gate and the eighth transmission gate transmit the output V of the first boosting module_O11(V_O12) Voltage to output V of the second boost module_O21(V_O22) V boosted by four times_INThe output voltage V of the second boosting module_O21(V_O22) Can be selected as 3V_INOr 4V_IN。

The third boost module proposed in fig. 3(c) works in the third stage, and the working principle is the same as that of the third gain control signal ctl₃The tenth transmission gate and the twelfth transmission gate which are controlled transmit the output V of the second boosting module_O21(V_O22) So that the third boost module V_O31(V_O32) Is lifted to 6V_INOr 8V_IN。

Fourth stage the fourth boost module proposed in fig. 3(d) operates, with the fourth gain control signal ctl₄When active, the fourth gain control signal ctl₄The nineteenth transmission gate and the twenty-second transmission gate which are controlled transmit the output V of the third boosting module_O31(V_O32) Voltage to boost the output V of the fourth boost module_O41(V_O42) Is lifted to 7V_INOr 9V_IN. Tenth gain control signal ctl₁₀When active, the tenth gain control signal ctl₁₀The eighteenth transmission gate and the twenty-first transmission gate which are controlled transmit the output V of the second boosting module_O21(V_O22) Voltage to boost the output V of the fourth boost module_O41(V_O42) Is lifted to 4V_INOr 5V_INThe output voltage V of the fourth boost module_O41(V_O42) Can be selected as 5V_INOr 7V_IN。

In summary, the boost module provided in this embodiment mainly includes a switch tube and a charging capacitor, two cross-coupled NMOS tubes are connected to the upper plate of the capacitor and the capacitor is precharged by using a body diode, so that 1-9 times of input voltage can be boosted. In combination with the gain selection module that controls the transmission gate by the gain control signal, the user can select an appropriate gain to boost the voltage according to the requirement, and how to select according to the gain control signal is described in detail below.

First gain control signal ctl₁To the tenth gain control signal ctl₁₀For controlling the gain of the charge pump, the corresponding relationship between each signal and the output gain is shown in fig. 5.

When a double gain is selected, the fifth gain control signal ctl5 is high to couple the input signal V_INTo the OUTPUT of the charge pump as shown in fig. 3 (e).

When the double gain is selected, the sixth gain control signal ctl6 is high to boost the output V of the first boost module_O11(V_O12) OUTPUT transmitted to the charge pump, at which time the OUTPUT V of the first boost module_O11(V_O12) Is selected to be 2V_IN。

When the triple gain is selected, the first gain control signal ctl1 and the seventh gain control signal ctl7 are high, and the seventh gain control signal ctl7 is high to boost the output V of the second boost module_O21(V_O22) OUTPUT transmitted to the charge pump, wherein the OUTPUT V of the second boost module_O21(V_O22) Is selected to be 3V by the first gain control signal ctl1_IN。

When the quadruple gain is selected, the second gain control signal ctl2 and the seventh gain control signal ctl7 are high, and the seventh gain control signal ctl7 is high to boost the output V of the second boost module_O21(V_O22) OUTPUT transmitted to the charge pump, wherein the OUTPUT V of the second boost module_O21(V_O22) Is selected to be 4V by the second gain control signal ctl2_IN。

When the quintuple gain is selected, the second, ninth, and tenth gain control signals ctl2, ctl9, and ctl10 are high, and the ninth gain control signal ctl9 is high to boost the output of the fourth boost module, V_O41(V_O42) OUTPUT transmitted to the charge pump, wherein the OUTPUT V of the fourth boost module_O41(V_O42) Selected as V by the tenth gain control signal ctl10_O21+V_IN(V_O22+V_IN) And V is_O21(V_O22) Is selected to be 4V by the second gain control signal ctl2_INThen the voltage of the OUTPUT of the charge pump is 5V_IN。

When the six-fold gain is selected, the first, third, and eighth gain control signals ctl1, ctl3, and ctl8 are high, and the eighth gain control signal ctl8 is high to boost the output of the third boost module, V_O31(V_O32) OUTPUT transmitted to the charge pump, wherein the OUTPUT V of the third boost module_O31(V_O32) Is selected to be 2V by the third gain control signal ctl3_O21(2V_O22) And V is_O21(V_O22) Is selected to be 3V by the first gain control signal ctl1_INThen the voltage of the OUTPUT of the charge pump is 6V_IN。

When the seven-fold gain is selected, the first, third, fourth, and ninth gain control signals ctl1, ctl3, ctl4, and ctl9 are high, and the ninth gain control signal ctl9 is high to boost the output V of the fourth boost module_O41(V_O42) OUTPUT transmitted to the charge pump, wherein the OUTPUT V of the fourth boost module_O41(V_O42) Selected as V by the fourth gain control signal ctl4_O31+V_IN(V_O32+V_IN) And V is_O31(V_O32) Is selected to be 2V by the third gain control signal ctl3_O21(2V_O22)，V_O21(V_O22) Is selected to be 3V by the first gain control signal ctl1_INThen the voltage of the OUTPUT of the charge pump is 7V_IN。

When the octave gain is selected, the second, third, and eighth gain control signals ctl2, ctl3, and ctl8 are high, and the eighth gain control signal ctl8 is high to boost the output of the third boost module, V_O31(V_O32) OUTPUT transmitted to charge pump, OUTPUT V of third boost module_O31(V_O32) Is selected to be 2V by the third gain control signal ctl3_O21(2V_O22) And V is_O21(V_O22) Is selected to be 4V by the second gain control signal ctl2_INThen the voltage of the OUTPUT of the charge pump is 8V_IN。

When nine times the gain is selected, the second gain control signal ctl2, the third gain control signal ctl3, the fourth gain control signal ctl4, and the ninth gain control signal ctl9 are high, and the ninth gain control signal ctl9 is high to boost the output V of the fourth boost module_O41(V_O42) OUTPUT transmitted to the charge pump, wherein the OUTPUT V of the fourth boost module_O41(V_O42) Selected as V by the fourth gain control signal ctl4_O31+V_IN(V_O32+V_IN) And V is_O31(V_O32) Is selected to be 2V by the third gain control signal ctl3_O21(2V_O22) Namely 8V_IN，V_O21(V_O22) Is selected to be 2V by the second gain control signal ctl2_O11(2V_O12) I.e. 4V_INThen the voltage of the OUTPUT of the charge pump is 9V_IN。

In addition, a plurality of first boosting modules, second boosting modules, third boosting modules and fourth boosting modules can be stacked to obtain voltage boosting of more than 9 times, for example, a group of boosting structures composed of the first boosting modules, the second boosting modules, the third boosting modules and the fourth boosting modules are arranged at present, another group of boosting structures composed of the first boosting modules, the second boosting modules, the third boosting modules and the fourth boosting modules (only the first boosting modules may be included, only the first boosting modules and only the second boosting modules may be included, only the first boosting modules, only the second boosting modules and only the third boosting modules are included) are arranged, each boosting structure is stacked by using a gain selection module, and voltage boosting of higher multiples can be achieved.

The clock signal and the transmission gate control signal in the charge pump can be generated by a clock generation module, as shown in fig. 4, which shows an implementation form of the clock generation module, and the circuit is composed of a delay block and a logic gate, so as to generate different non-overlapping clock signals to control a switch tube in the charge pump circuit. In the implementation mode of the whole clock generator in the embodiment, a series of clock signals with time difference are obtained through a delay chain, and then the signals are processed by using a nand gate, a nor gate and an inverter to obtain another group of clock signals capable of correctly driving the reconfigurable charge pump.

Fig. 6 shows the last generated waveform of the clock generation module in this embodiment, and it can be seen that the last waveform is nested. The last stage clocks gate _41, gate _42 and clk _41, clk _42 are the clocks with the shortest on time. That is, the last stage does not start to operate until the signals controlled by the penultimate stages, i.e., gate _31, gate _32, clk _31, and clk _32, start to operate; similarly, the shutdown process is such that the last stage is shutdown before the second to last stage. The remaining two stages are similar to the last two stages in relation to the previous stage, although not shown in the figure, but are also nested open. Because the two clocks with the second subscripts of 1 and 2 are not in a high state at the same time, the reverse charging of the interstage capacitor to the input end does not exist; the gate signal is turned on after the clk signal and turned off before the clk signal, so that reverse charging from the output end to the input end does not exist; and because the signals of the front stage and the rear stage are nested, the reverse charging loss from the output end to the inter-stage capacitor does not exist. The clock generator avoids reverse charging losses.

In summary, the present invention provides a new maximum power tracking method based on the hill climbing algorithm, which adjusts the input impedance of the power stage in the energy collection system from three dimensions (the gain of the charge pump, the inter-stage capacitance, and the operating frequency) to match the internal resistance of the energy source, so that the system operates at the maximum power point.

Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims

1. A three-dimensional maximum power point tracking method is characterized by being applicable to an energy collection system using a charge pump for a power stage, wherein when the input resistance of the power stage is equal to the internal resistance of the energy collection system, the energy collection system works at a maximum power point;

2. The three dimensional maximum power point tracking method of claim 1, wherein the number of steps of adjusting the capacitance is less than the number of steps of adjusting the frequency in each cycle.

3. The three-dimensional maximum power point tracking method according to claim 1 or 2, wherein the charge pump is a gain-adjustable charge pump comprising a first boost module, a second boost module, a third boost module, a fourth boost module and a gain selection module;

4. The three-dimensional maximum power point tracking method according to claim 3, wherein the charge pump further comprises a clock generation module for generating non-overlapping clock signals as the clock signals and transmission gate control signals of the first, second, third and fourth boost modules.

5. The three-dimensional maximum power point tracking method according to claim 3 or 4, wherein the charge pump comprises a plurality of first, second, third and fourth boosting modules, and output signals of each of the first, second, third and fourth boosting modules are superimposed through the gain selection module.