CN111199934A - Circuit device and circuit design and assembly method - Google Patents
Circuit device and circuit design and assembly method Download PDFInfo
- Publication number
- CN111199934A CN111199934A CN201811366820.7A CN201811366820A CN111199934A CN 111199934 A CN111199934 A CN 111199934A CN 201811366820 A CN201811366820 A CN 201811366820A CN 111199934 A CN111199934 A CN 111199934A
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- ball
- solder balls
- circuit
- component
- target
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
Abstract
The invention discloses a circuit device and a circuit design and assembly method, which can reduce parasitic inductance to improve circuit efficiency. An embodiment of the circuit device comprises: an integrated circuit of a ball grid array package, comprising a plurality of solder balls, wherein the plurality of solder balls comprise at least one target ball; a printed circuit board electrically connected to the BGA package IC via the solder balls; and a component disposed between the ball grid array packaged integrated circuit and the printed circuit board and electrically connected to the at least one target ball.
Description
Technical Field
The present invention relates to a circuit device and a circuit design and assembly method, and more particularly, to a circuit device and a circuit design and assembly method capable of reducing parasitic inductance.
Background
Many electronic products (e.g., set-top boxes, mobile phones, tablet computers) adopt a system-on-a-chip (SoC) design, which usually includes a central processing unit/microprocessor (CPU/μ P), a peripheral circuit, and so on, and requires multiple sets of power supplies (e.g., multi-layer ceramic capacitors (MLCCs)), where the power supplies of the CPU particularly require capacitors with low inductance values.
The voltage stabilizing capacitor is usually soldered to the back of a printed circuit board or contained in the IC package of the SoC. If a voltage-stabilizing capacitor is disposed on the back side of the printed circuit board, the voltage-stabilizing capacitor needs to pass through a via (via) of the printed circuit board to be electrically connected to a circuit (e.g., a CPU) of the SoC, wherein the via causes a parasitic inductance problem, and the parasitic inductance affects the high-frequency response of the voltage-stabilizing capacitor and causes unstable transient voltage of the CPU. If a voltage-stabilizing capacitor is included in the SoC IC package, the IC package has a higher cost and requires additional space for disposing the voltage-stabilizing capacitor; in addition, such IC packages may also result in the SoC being taxed at a higher rate in certain countries.
Disclosure of Invention
It is an object of the present invention to provide a circuit device and a circuit design and assembly method to avoid the problems of the prior art.
An object of the present invention is to provide a circuit device and a circuit design and assembly method to reduce parasitic inductance.
The invention discloses a circuit device, one embodiment of which comprises a ball grid array packaged integrated circuit, a printed circuit board and a component. The integrated circuit of the ball grid array package comprises a plurality of solder balls, and the plurality of solder balls comprise at least one target ball. The printed circuit board is electrically connected with the integrated circuit of the ball grid array package through the plurality of solder balls. The element is arranged between the integrated circuit of the ball grid array package and the printed circuit board, namely in the range of an orthographic projection of the integrated circuit of the ball grid array package on the printed circuit board, and the element is electrically connected with the at least one target ball.
The invention also discloses a circuit design and assembly method, one embodiment of which comprises the following steps: making a standing height of each of a plurality of solder balls of an integrated circuit of a ball grid array package greater than a preset height, and making a layout of the plurality of solder balls comprise a reserved space, wherein the reserved space does not contain any solder ball; selecting an element with a height not greater than the predetermined height; arranging the element on a printed circuit board; and connecting the printed circuit board to the integrated circuit of the BGA package via the plurality of solder balls, wherein the component is located between the printed circuit board and the integrated circuit of the BGA package and in the reserved space.
The features, implementations, and technical advantages of the present invention are described in detail below with reference to the accompanying drawings.
Drawings
FIG. 1 shows a side view of one embodiment of a circuit device of the present disclosure;
FIG. 2 illustrates a bottom view of one embodiment of the ball grid array packaged integrated circuit of FIG. 1;
FIG. 3 shows a side view of another embodiment of a circuit device of the present disclosure;
FIG. 4 shows a side view of another embodiment of a circuit device of the present disclosure;
FIG. 5 illustrates one embodiment of a circuit design and assembly method of the present disclosure;
FIG. 6 shows another embodiment of the circuit design and assembly method of the present disclosure;
FIG. 7 shows yet another embodiment of a circuit design and assembly method of the present disclosure; and
FIG. 8 shows a further embodiment of the circuit design and assembly method of the present disclosure.
Description of the symbols
100 circuit arrangement
110 ball grid array packaged integrated circuit
120 printed circuit board
130 element
112 substrate
114 chip
116 packaging material
118 multiple solder balls
1182 at least one target ball
122 first side of the printed circuit board
124 second side of the printed circuit board
1222. 1242 welding point
1224 routing
126 guide hole
210 reserve space
300 circuit device
132 first end of element
134 second end of the element
310 power supply ball
320 ground ball
400 circuit arrangement
405. 415 routing
410 target ball
420 target weld spot
S510 to S540
S610 to S620
S710 step
S810 step
Detailed Description
The present disclosure includes circuit devices and circuit design and assembly methods that can reduce parasitic inductance of the circuit, thereby improving circuit performance.
Fig. 1 shows an embodiment of the circuit device of the present invention. The circuit device 100 of fig. 1 includes an integrated circuit of Ball Grid Array (BGA) package 110, a Printed Circuit Board (PCB) 120 and a component 130.
Please refer to fig. 1. One embodiment of BGA IC110 includes a substrate 112, a chip 114, a packaging material 116 (e.g., resin), and a plurality of solder balls 118. The chip 114 may be electrically connected to the substrate 112 by wire bonding, flip chip, or other methods, which are well known in the art and the details of which are omitted herein. The solder balls 118 include at least one target ball 1182, the target ball 1182 is at least one of a power ball (power ball), a signal ball (signal ball), and a ground ball (ground ball), wherein the power ball is used for providing a power potential, the signal ball is used for transmitting a signal, and the ground ball is used for providing a ground potential; in this embodiment, the at least one target ball 1182 includes a power ball (shown by the diagonal circles in fig. 1 and 2) and a ground ball (shown by the dot circles in fig. 1 and 2). In addition, the layout (layout) of the solder balls 118 (or distribution pattern) includes a reserved space for accommodating the component 130, and the reserved space is free of any solder balls 118. The bottom view of BGA IC110 of fig. 2 shows the remaining space 210 of solder balls 118, which is merely exemplary and not intended to limit the practice of the present invention.
Please refer to fig. 1. The PCB120 includes a first side 122 and a second side 124, the first side 122 includes a plurality of solder joints 1222 (shown as black square bars in fig. 1) and traces 1224; the component 130 is disposed on the first surface 122 and electrically connected to at least one target ball 1182 via at least one of the pads 1222, and the PCB120 is connected to the plurality of solder balls 118 via at least a portion of the pad 1222, thereby electrically connecting the BGA IC 110. The second side 124 may optionally include solder joints 1242 and traces (not shown), the solder joints 1242 of the second side 124 can be electrically connected to the solder joints 1222, the traces 1224, other solder joints or other traces of the first side 122 through vias (vias)126 of the PCB 120. It is noted that the solder 1242, traces (not shown) and vias 126 of the second side 124 are implementation options of the PCB120, and are not implementation requirements; in addition, the PCB120 should reserve a space on the first surface 122 for disposing the aforementioned components 130.
Please refer to fig. 1. The component 130 is disposed between the BGA IC110 and the PCB 120; in other words, the component 130 is disposed within an orthographic projection of the BGA IC110 on the PCB 120. In the present embodiment, the device 130 includes a first end electrically connected to the power ball of the at least one target ball 1182 through the solder 1222 and the trace 1224, and a second end electrically connected to the earth of the at least one target ball 1182 through the solder 1222 and the trace 1224. In another embodiment, as shown in the circuit device 300 of fig. 3, the position of the device 130 and the position of at least one target ball (i.e., the power ball 310 and the ground ball 320) are in tandem from the perspective of fig. 3, a first end 132 of the device 130 is electrically connected to the power ball 310 of the at least one target ball through a bonding pad and a trace, and a second end 134 of the device 130 is electrically connected to the ground ball 320 of the at least one target ball through a bonding pad and a trace, wherein a shortest distance between the first end 132 and the second end 134 is substantially equal to a shortest distance between the center of the power ball 310 and the center of the ground ball 320, and a distance from the first end 132 to the power ball 310 is substantially equal to a distance from the second end 134 to the ground ball 320. In another embodiment, the device 130 is electrically connected to at least one target ball via at least one conductive path (e.g., trace, wire bond, conductor …) of the PCB 120. In another embodiment, as shown in the circuit device 400 of fig. 4, one end of the component 130 is electrically connected to at least one target ball 410 (e.g., at least one power ball) via a trace 405, and the other end of the component 130 is electrically connected to a target pad 420 (e.g., a pad for providing ground potential) on the first surface 122 of the PCB120 via a trace 415, where the target pad 420 is not located between the BGA IC110 and the PCB120, i.e., not located within the range of the orthographic projection. In addition, one embodiment of the device 130 is a passive device (passive device); for example, the passive component is a capacitor (e.g., a multilayer ceramic capacitor (MLCC)), an inductor, or a resistor (e.g., a precise external resistor for generating a precise reference voltage).
Please refer to fig. 1. In order to position the component 130 between the BGA IC110 and the PCB120, the height of the component 130 is not greater than a stand-off height (standing height) of each of the solder balls 118, which may be a minimum value within a range of standing heights specified by a packaging process of the BGA IC110, depending on the packaging process; alternatively, the height of the component 130 is not greater than the distance from the substrate 112(substrate) of the BGA IC110 to the first side 122 of the PCB120, and since the solder balls 118 and the pads of the component 130 are solder paste, the maximum height of the component 130 is less than the minimum standing height of the solder balls 118. For example, since the standing height of each of the solder balls 118 is usually not larger than a predetermined diameter of each of the solder balls 118, which is determined by the packaging process, the height of the component 130 can be limited to be not larger than the predetermined diameter. The aforementioned packaging process for BGA IC110 and surface attachment process may be known or self-developed techniques.
FIG. 5 shows an embodiment of the circuit design and assembly method of the present disclosure. The method of fig. 5 comprises the following steps:
step S510: a standing height of each of a plurality of solder balls of an integrated circuit of a ball grid array package is made to be larger than a preset height, and a layout of the solder balls comprises a reserved space, wherein the reserved space is free of any solder ball. One embodiment of the predetermined height is a predetermined diameter of each of the plurality of solder balls, the predetermined diameter being associated with a packaging process of the BGA packaged integrated circuit.
Step S520: selecting a component having a height not greater than the predetermined height. An embodiment of the device is a passive device, such as a capacitor (e.g., MLCC), an inductor, or a resistor. The device may also be an active device (active device) as long as the height of the active device is not greater than the predetermined height and can be accommodated in the reserved space.
Step S530: the component is disposed on a printed circuit board.
Step S540: the printed circuit board is connected to the integrated circuit of the ball grid array package through the plurality of solder balls, wherein the component is located between the printed circuit board and the integrated circuit of the ball grid array package (i.e. within an orthographic projection of the integrated circuit of the ball grid array package on the printed circuit board) and located in the reserved space.
Fig. 6 shows another embodiment of the circuit design and assembly method of the present disclosure. Compared to fig. 5, the method of fig. 6 further includes the following steps:
step S610: electrically connecting the first end of the element to a power supply ball of the plurality of solder balls; and
step S620: the second end of the element is electrically connected with a grounding ball of the plurality of solder balls, wherein the shortest distance between the first end and the second end is substantially equal to the shortest distance between the center of the power supply ball and the center of the grounding ball, and the distance from the first end to the power supply ball is substantially equal to the distance from the second end to the grounding ball.
Fig. 7 shows a further embodiment of the circuit design and assembly method of the present disclosure. Compared to fig. 5, the method of fig. 7 further includes the following steps:
step S710: the component is electrically connected with a power ball or a signal ball of the plurality of solder balls.
Fig. 8 shows a further embodiment of the circuit design and assembly method of the present disclosure. Compared to fig. 5, the method of fig. 8 further includes the following steps:
step S810: one end of the element is electrically connected with at least one target ball of the plurality of solder balls; and electrically connecting the other end of the component to a target solder joint of the printed circuit board, wherein the target solder joint is not positioned between the integrated circuit packaged by the ball grid array and the printed circuit board.
Since the details and variations of the embodiments of the method described above can be understood by those skilled in the art with reference to the disclosure of the embodiments of the apparatus, that is, the technical features of the embodiments of the apparatus can be reasonably applied to the embodiments of the method, the repeated and redundant description is omitted here without affecting the disclosure requirements and the feasibility of the embodiments of the method. It is noted that the order of the steps of the method embodiments is not limiting, provided that implementation is possible.
It should be noted that, when the implementation is possible, a person skilled in the art may selectively implement some or all of the technical features of any one of the foregoing embodiments, or selectively implement a combination of some or all of the technical features of the foregoing embodiments, thereby increasing the flexibility in implementing the invention.
In summary, the invention uses the reserved space of the BGA solder ball layout to place the device, so as to reduce the distance from the device to the BGA solder ball, thereby reducing the parasitic inductance and improving the circuit performance.
Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
Claims (10)
1. A circuit device, comprising:
an integrated circuit of a ball grid array package, comprising a plurality of solder balls, wherein the plurality of solder balls comprise at least one target ball;
a printed circuit board electrically connected to the integrated circuit of the BGA package via the solder balls; and
and a component arranged between the ball grid array packaged integrated circuit and the printed circuit board and electrically connected with the at least one target ball.
2. The circuit device of claim 1, wherein the at least one target ball comprises a power ball or a signal ball.
3. The circuit device of claim 1, wherein the at least one target ball comprises a power ball and a ground ball.
4. The circuit device of claim 1, wherein the component is a passive component.
5. The circuit device of claim 1, wherein the height of the component is not greater than a standing height of each of the plurality of solder balls.
6. The circuit device of claim 1, wherein the component comprises a first terminal electrically connected to a power ball of the at least one target ball and a second terminal electrically connected to a ground of the at least one target ball, wherein a shortest distance between the first terminal and the second terminal is equal to a shortest distance between a center of the power ball and a center of the ground ball.
7. The circuit device of claim 1, wherein one end of the component is electrically connected to the at least one target ball, and the other end of the component is electrically connected to a target pad of the printed circuit board, the target pad not being located between the ball grid array packaged integrated circuit and the printed circuit board.
8. A circuit design and assembly method includes the following steps:
making a standing height of each of a plurality of solder balls of an integrated circuit of a ball grid array package greater than a preset height, and making a layout of the solder balls comprise a reserved space, wherein the reserved space does not contain any solder ball;
selecting an element with a height not greater than the predetermined height;
arranging the element on a printed circuit board; and
connecting the printed circuit board to the integrated circuit of the BGA package via the solder balls, wherein the component is located between the printed circuit board and the integrated circuit of the BGA package and in the reserved space.
9. The circuit design and assembly method of claim 8, wherein the predetermined height is a predetermined diameter of each of the plurality of solder balls.
10. The circuit design and assembly method of claim 8, wherein the device includes a first terminal and a second terminal, the circuit design and assembly method further comprising: electrically connecting the first end to a power ball of the solder balls; and a grounding ball electrically connecting the second end with the plurality of solder balls, wherein a shortest distance between the first end and the second end is equal to a shortest distance between the center of the power ball and the center of the grounding ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811366820.7A CN111199934B (en) | 2018-11-16 | 2018-11-16 | Circuit device and circuit design and assembly method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811366820.7A CN111199934B (en) | 2018-11-16 | 2018-11-16 | Circuit device and circuit design and assembly method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111199934A true CN111199934A (en) | 2020-05-26 |
| CN111199934B CN111199934B (en) | 2022-07-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811366820.7A Active CN111199934B (en) | 2018-11-16 | 2018-11-16 | Circuit device and circuit design and assembly method |
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| Country | Link |
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| CN (1) | CN111199934B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420661A (en) * | 2022-03-28 | 2022-04-29 | 飞腾信息技术有限公司 | Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8698317B2 (en) * | 2010-09-27 | 2014-04-15 | Samsung Electronics Co., Ltd | Methods of fabricating package stack structure and method of mounting package stack structure on system board |
| CN103811472A (en) * | 2012-11-05 | 2014-05-21 | 三星电子株式会社 | Semiconductor package and manufacturing method thereof |
| CN103915421A (en) * | 2012-12-28 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Methods and apparatus for forming package-on-packages |
| CN105679749A (en) * | 2014-12-05 | 2016-06-15 | 三星电子株式会社 | Package on packages and mobile computing devices having the same |
-
2018
- 2018-11-16 CN CN201811366820.7A patent/CN111199934B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8698317B2 (en) * | 2010-09-27 | 2014-04-15 | Samsung Electronics Co., Ltd | Methods of fabricating package stack structure and method of mounting package stack structure on system board |
| CN103811472A (en) * | 2012-11-05 | 2014-05-21 | 三星电子株式会社 | Semiconductor package and manufacturing method thereof |
| CN103915421A (en) * | 2012-12-28 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Methods and apparatus for forming package-on-packages |
| CN105679749A (en) * | 2014-12-05 | 2016-06-15 | 三星电子株式会社 | Package on packages and mobile computing devices having the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420661A (en) * | 2022-03-28 | 2022-04-29 | 飞腾信息技术有限公司 | Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment |
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| Publication number | Publication date |
|---|---|
| CN111199934B (en) | 2022-07-19 |
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