CN114420661A - Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment - Google Patents

Abstract

The integrated circuit packaging structure comprises a first substrate, a ball grid array, an integrated circuit component and a first capacitor, wherein the first capacitor is connected with the first substrate through a bonding pad and is connected with at least two contact solder balls through interconnection wiring on the first substrate to realize electric connection with the integrated circuit component, so that the first capacitor can provide energy for a core power supply of the integrated circuit component when the core power supply fluctuates, the fluctuation of the core power supply is reduced or eliminated, and the performance of the integrated circuit packaging structure is optimized. In addition, the arrangement density of a plurality of contact solder balls included in the ball grid array in the first area of the first substrate is smaller than that in the second area, so that more space is provided for arranging the first capacitor in the first area, the arrangement quantity of the first capacitor is increased, and the first capacitor can better exert the voltage stabilizing function on the core power supply.

Description

Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to an integrated circuit package structure, an integrated circuit package method, an integrated circuit system, and an electronic device.

Background

With the continuous development of semiconductor technology, the number of elements accommodated on a single integrated circuit is increasing, which puts higher demands on the package structure of the integrated circuit.

Among various integrated Circuit package structures, Ball Grid Array (BGA) package structures have better suitability for Large Scale Integration (LSI) or Very Large Scale Integration (VLSI) due to their smaller size, better heat dissipation performance, and electrical performance.

However, as the integration level of the integrated circuit is further improved, it is necessary to optimize the performance of the integrated circuit package structure.

Disclosure of Invention

In view of the above, embodiments of the present disclosure are directed to an integrated circuit package structure, a packaging method, an integrated circuit system and an electronic device, so as to achieve the purpose of optimizing the performance of the integrated circuit package structure.

In a first aspect, an integrated circuit package structure is provided, including:

a first substrate including a first side and a second side opposite the first side, the first side including a first area and a second area surrounding the first area;

a ball grid array including a plurality of contact balls distributed on the first side, the density of the contact balls distributed in the first area being less than the density of the contact balls distributed in the second area;

an integrated circuit component located on the second side;

a first capacitor disposed in the first region, the first capacitor being connected to at least two of the contact solder balls for electrical connection to the integrated circuit component.

The first capacitor is electrically connected with the integrated circuit component through connection with at least two contact solder balls (specifically, the first capacitor is connected with the first substrate through a pad and is connected with at least two contact solder balls through routing wires on the first substrate), so that the first capacitor can provide energy for a core power supply of the integrated circuit component when the core power supply fluctuates, the fluctuation of the core power supply is reduced or eliminated, and the performance of the integrated circuit packaging structure is optimized. In addition, the arrangement density of the plurality of contact solder balls in the first area of the first substrate is smaller than that in the second area, so that more space is available in the first area for arranging the first capacitor, the arrangement quantity of the first capacitor is increased, and the first capacitor can better play a voltage stabilizing function on the core power supply.

In a feasible implementation manner, the ratio of the area of the first region to the sum of the areas of the first region and the second region ranges from 10% to 20%.

The inventor finds that the ratio of the area of the first region to the sum of the areas of the first region and the second region is limited to 10% -20%, and the first capacitor can be arranged in a certain region, so that substrate warping caused by welding stress of contact solder balls after the first substrate is packaged with other package substrates can be avoided on the basis of improving the stability of a core power supply.

In one possible implementation, the density of the contact solder balls distributed in the first area is zero.

Because the first area is not used for arranging the contact solder balls, a larger space is provided for the first capacitor, and the arrangement convenience of the first capacitor is improved. Secondly, because the first area is not provided with the contact solder balls, the possibility that the first capacitor is in error contact with the adjacent contact solder balls in the setting process is reduced to a certain extent, and the preparation yield of the integrated circuit packaging structure is improved. Thirdly, because all be used for setting up first electric capacity in the first region for can set up more first electric capacity in the same size's first region, increase the electric capacity as core power supply energy storage capacitor, the energy storage capacitor of great electric capacity can provide better steady voltage function for the core power supply of integrated circuit part, improves system stability.

In one possible implementation, the integrated circuit component includes a core power supply;

an orthographic projection of the first region on the first side at least partially overlaps an orthographic projection of the core power supply on the first side.

Therefore, the decoupling path between the first capacitor (especially the first capacitor in the overlapping area with the core power supply) arranged in the overlapping area and the core power supply is relatively short, which is beneficial to improving the capacitance filtering effect of the first capacitor in the overlapping area and ensuring that the first capacitor has a good voltage stabilizing effect.

In a possible implementation, an orthographic projection of the first area on the first side coincides with an orthographic projection of the core power supply on the first side.

The distance between the first capacitor and the core power supply in the first area is smaller, namely the decoupling path of the first capacitor in the first area is relatively shorter, so that the filtering effect of the first capacitor is promoted, and the first capacitor is ensured to play a good voltage stabilizing effect.

In a possible implementation manner, the number of the first capacitors is multiple, multiple first capacitors are arranged in the first area in an array manner, and the first capacitors in the same row are oriented in the same direction.

Usually first electric capacity includes electric capacity body, the first utmost point and second utmost point, because the interconnection of connecting the first utmost point is walked the line and can not be crossed with the interconnection of connecting the second utmost point to avoid short-circuiting first electric capacity, therefore the first electric capacity that so sets up makes the interconnection of connecting the first utmost point walk the line and all arrange in one side of first electric capacity, the interconnection of connecting the second utmost point walks to walk the line and all arrange at the opposite side of first electric capacity, be favorable to simplifying the design degree of difficulty that the interconnection was walked, reduce the risk with the short circuit of first electric capacity.

In a possible implementation, the first capacitors in the same row are oriented perpendicular to the row direction, and the first poles of the first capacitors in the same row are connected to at least one contact ball in a row of contact balls in the ball grid array.

The second pole of the first capacitance in the same row is connected to at least one contact ball in another row of contact balls in the ball grid array.

And the contact solder balls connected with the first pole and the second pole are arranged in different rows, so that the risk of short circuit between the interconnection line connected with the first pole and the interconnection line connected with the second pole is reduced, the design difficulty of the interconnection line is simplified, and the risk of short circuit of the first capacitor is reduced.

In one possible implementation, the first substrate further includes: a recessed region located in the first region.

The plurality of capacitors are disposed in the recessed region.

The first capacitor is arranged in the recessed area, so that the space of the first capacitor in the longitudinal direction (the direction perpendicular to the first side and the second side of the first substrate) is increased, the operation space is larger when the first capacitor is placed on the first substrate, the success rate of placing the first capacitor is increased, and the preparation yield of the whole integrated circuit packaging structure is increased.

In one possible implementation, the height of the first capacitor is smaller than the height of the contact solder ball.

Since the ball grid array further needs to be connected to a Printed Circuit Board (PCB), the first capacitor further needs to have a low height, and the height of the first capacitor is smaller than that of the contact solder ball, so as to ensure good electrical contact between the contact solder ball and other package substrates, and avoid the problem of abnormal electrical contact between the contact solder ball and other package substrates due to the excessively high first capacitor.

In a second aspect, an integrated circuit package structure is provided, comprising:

the first substrate comprises a packaging side and a circuit side opposite to the packaging side, wherein the circuit side is used for arranging an integrated circuit component, the packaging side comprises a decoupling area and a welding area surrounding the decoupling area, the decoupling area is used for providing an arrangement space of a first capacitor, and the first capacitor is used for reducing or eliminating core power supply fluctuation of the integrated circuit component.

The special decoupling area is arranged on the packaging side of the first substrate to provide a corresponding arrangement space for the first capacitor electrically connected with the integrated circuit component, the arrangement difficulty of the first capacitor is reduced on the premise that the first capacitor eliminates or reduces the core power supply fluctuation of the integrated circuit component, and meanwhile, the special decoupling area is also favorable for placing a relatively large number of first capacitors, and the suppression capability of the first capacitors in the decoupling area on the core power supply fluctuation is favorable for optimizing.

In a third aspect, an integrated circuit system is provided, comprising: an integrated circuit package structure as claimed in any preceding claim, comprising a ball grid array;

a printed circuit board including a third side and a fourth side, the third side including at least one coupling region that couples with a ball grid array of the integrated circuit package structure.

And the second capacitor is arranged on the fourth side, and the orthographic projection of the second capacitor on the fourth side and the orthographic projection of the contact solder balls of the ball grid array on the fourth side do not overlap.

When the core power supply fluctuates, the second capacitor can provide energy for the core power supply, similar to the first capacitor, so that the fluctuation of the voltage of the core power supply is reduced, and the stability of the voltage of the core power supply is improved.

In a possible implementation manner, a package size of the first capacitor is smaller than a package size of the second capacitor, or a capacity of the first capacitor of the integrated circuit package structure is smaller than a capacity of the second capacitor.

When the packaging size of the first capacitor is smaller than that of the second capacitor, and the capacity of the first capacitor is smaller than that of the second capacitor, the first capacitor can provide a better energy supplement effect for the core power supply at a medium frequency (for example, 100 MHz) or a high frequency, the second capacitor can provide a better energy supplement effect for the core power supply at a low frequency, and the first capacitor and the second capacitor supplement each other, so that the core power supply can stably run at a full frequency band (particularly at a low frequency and a medium frequency band), and the stability of the system is improved.

In one possible implementation, the fourth side includes: an orthographic projection of the third region on the first side at least partially overlaps with an orthographic projection of a region where the first capacitor is disposed in the integrated circuit package structure on the first side of the first substrate of the integrated circuit package structure.

The second capacitor is disposed in the third region.

Since the density of the contact solder balls in the arrangement region (e.g., the first region) of the first capacitor is small or is not used for arranging the contact solder balls, the degree of freedom in arranging the second capacitor in the overlapping region can be increased without considering the positional relationship between the second capacitor and the contact solder balls.

In a possible implementation manner, the number of the second capacitors is multiple, and the multiple second capacitors are arranged in an array manner.

In one column of the second capacitors, the orientation of the second capacitors is parallel to the row direction, the first poles of the second capacitors face preset edges, and the preset edges include a vertical edge which is closest to the second capacitors in the third region outer edge.

The first poles of the second capacitors arranged in this way all face towards the outside (namely towards the preset edge), so that the first poles connected with the core power supply face towards the same direction, the crossing of the wiring connected with the first poles and the second poles is avoided, the wiring design on the fourth side is simplified, the first poles face towards the outside, the arrangement space of the wiring connected with the first poles is increased, the design difficulty is reduced, and the preparation yield is improved.

In one possible implementation, the integrated circuit package structure further includes: a first power supply terminal, a second power supply terminal, and a third capacitor.

The third side includes at least two of the coupling regions, the third capacitor, the first power terminal, and the second power terminal are disposed between adjacent coupling regions, a first pole of the third capacitor is connected to the first power terminal, and a second pole of the third capacitor is connected to the second power terminal.

The third capacitor is arranged on the third side of the printed circuit board, so that the third capacitor can provide energy for the system power supply when the system power supply signal fluctuates, and particularly for low-frequency power supply signals (for example, power supply signals smaller than or equal to 30 MHz), the third capacitor can play a good decoupling role, and the stability of the system power supply is improved.

In a fourth aspect, there is provided an integrated circuit packaging method comprising:

providing a first substrate comprising a first side and a second side opposite the first side, the first side comprising a first area and a second area surrounding the first area;

forming an integrated circuit component on the second side;

forming a ball grid array on the first side, the ball grid array including a plurality of contact solder balls, the density of the contact solder balls distributed in the first area being less than the density of the contact solder balls distributed in the second area;

and forming a first capacitor in the first area, wherein the first capacitor is connected with at least two contact solder balls so as to be electrically connected with the integrated circuit component.

In a fifth aspect, there is provided an electronic device comprising an integrated circuit system as claimed in any one of the above.

In a sixth aspect, there is provided a server chip comprising an integrated circuit system as claimed in any one of the preceding claims.

The integrated circuit packaging structure provided by the embodiment of the specification comprises a first substrate, a ball grid array, an integrated circuit component and a first capacitor, wherein the first capacitor is connected with the first substrate through a bonding pad and is connected with at least two contact solder balls through a routing wire on the first substrate, so that the first capacitor is electrically connected with the integrated circuit component, and the first capacitor can provide energy for a core power supply of the integrated circuit component when the core power supply fluctuates, so that the fluctuation of the core power supply is reduced or eliminated, and the performance of the integrated circuit packaging structure is optimized.

In addition, the arrangement density of the plurality of contact solder balls in the first area of the first substrate is smaller than that in the second area, so that more space is available in the first area for arranging the first capacitor, the arrangement quantity of the first capacitor is increased, and the first capacitor can better play a voltage stabilizing function on the core power supply.

Drawings

Fig. 1 is a schematic diagram of an integrated circuit package structure according to an embodiment of the present disclosure.

Fig. 2 is a top view of fig. 1.

Fig. 3 is a schematic cross-sectional view along line AA' in fig. 2.

Fig. 4 is a schematic view of a first side of a first substrate according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram illustrating connection between a first capacitor and a contact ball according to an embodiment of the present disclosure.

Fig. 6 is a schematic view of a first side of another first substrate provided in an embodiment of the present disclosure.

Fig. 7 is a schematic cross-sectional view taken along line BB' in fig. 6.

Fig. 8 is a schematic view of a first side of another first substrate provided in an embodiment of the present disclosure.

Fig. 9 is a schematic cross-sectional view taken along line CC' of fig. 8.

Fig. 10 is a schematic cross-sectional view of an integrated circuit package structure according to an embodiment of the present disclosure.

Fig. 11 is an enlarged schematic view of a partial region of a first side of a first substrate according to an embodiment of the present disclosure.

Fig. 12 is a schematic cross-sectional view of an integrated circuit system according to an embodiment of the present disclosure.

Fig. 13 is a schematic cross-sectional view of another integrated circuit system provided in an embodiment of the present disclosure.

Fig. 14 is an enlarged schematic view of a partial area of a fourth side of a printed circuit board according to an embodiment of the present disclosure.

Fig. 15 is a schematic cross-sectional view of an integrated circuit package structure according to an embodiment of the present disclosure.

Fig. 16 is a flowchart illustrating an integrated circuit packaging method according to an embodiment of the present disclosure.

Description of reference numerals:

10-integrated circuit package structure;

20-an integrated circuit system;

100-a first substrate;

101-a first side;

102-a second side;

1001-first area;

1002-a second region;

1001 a-recessed area;

110-contact solder balls;

110 a-first contact solder balls;

110 b-second contact solder balls;

120-a first capacitance;

121-a capacitor body of a first capacitance;

122 — a first pole of a first capacitance;

123-a second pole of the first capacitor;

130-integrated circuit components;

131-core power supply;

161-an insulating layer;

162-interconnect routing;

163-pad;

140-a printed circuit board;

141-third side;

142-fourth side;

143-a coupling region;

144-an interconnect layer;

145-third zone;

1451-a vertical edge of the third region 145;

1452-another vertical edge of the third region 145;

150-a second capacitance;

151-first pole of second capacitance;

152-a capacitor body of a second capacitance;

153-a second pole of a second capacitor;

171-a first power supply terminal;

172-a second power supply terminal;

173-third capacitance;

202-package side;

201-circuit side;

2021-a decoupling region;

2022-welding area.

Detailed Description

The specification describes example embodiments with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions illustrated in the present specification but include deviations in shapes that result, for example, from manufacturing. For example, a contact solder ball shown as a spherical surface will typically have an elliptical character. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Unless otherwise defined, technical or scientific terms used in the embodiments of the present specification should have the ordinary meaning as understood by those having ordinary skill in the art to which the embodiments of the present specification belong. The terms "first," "second," and the like as used in the embodiments of the present specification do not denote any order, quantity, or importance, but rather are provided to avoid mixing of constituent elements.

Unless the context requires otherwise, throughout the description, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to". In the description of the specification, the terms "one embodiment," "some embodiments," "an example embodiment," "an example," "a specific example" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the specification. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples. In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited to the description.

Summary of the application

With the rapid development of the integrated circuit technology, the demand of the integrated circuit chip on the information transmission capability of the integrated circuit packaging structure is higher and higher, the number of the welding points is denser and denser, and the ball grid array packaging structure has the characteristics of small volume, excellent heat dissipation performance and electric performance, so that the ball grid array packaging structure with the same size can accommodate more contact welding balls, and the characteristics make the ball grid array packaging structure become a common packaging form at present.

Modern large Integrated Circuit or very large Integrated Circuit devices, such as Application Specific Integrated Circuits (ASICs) and general purpose processors, can operate at high frequency, high power specifications. The inventor researches and discovers that for the application field of integrated circuits such as servers, the chip size is large, the load fluctuation is large when the chip works, when the current flowing to the integrated circuit components is increased sharply, such as when a calculation intensive process or a high concurrent process is started, the Core power Supply Voltage (CVDD) is disturbed by the inductance effect generated in the circuit, and the generated power ripple can cause the integrated circuit to be incapable of working normally. There is therefore a need to improve the power supply stability of integrated circuit chips.

Embodiments of the present disclosure provide an integrated circuit package structure, so as to achieve the purposes of reducing or eliminating core power supply fluctuation, optimizing performance of the integrated circuit package structure, and improving system stability of an integrated circuit through improvement of the integrated circuit package structure. The technical solutions in the embodiments of the present specification will be described below with reference to the drawings in the embodiments of the present specification. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without any creative effort belong to the protection scope of the present specification.

Exemplary Package Structure

An exemplary embodiment of the present description provides an integrated circuit package structure, and referring to fig. 1, fig. 2 and fig. 3, fig. 1 shows a schematic diagram of an integrated circuit package structure 10, fig. 2 is a top view of fig. 1 (i.e., a schematic diagram of a first side 101 of a first substrate 100), fig. 3 is a schematic diagram of a cross-sectional structure along line AA' in fig. 2, and the integrated circuit package structure 10 includes:

a first substrate 100, said first substrate 100 comprising a first side 101 and a second side 102 opposite to said first side 101, said first side 101 comprising a first area 1001 and a second area 1002 surrounding said first area 1001. The first substrate 100 may be a semiconductor material substrate such as silicon or gallium arsenide, and the integrated circuit component 130 may be formed based on the first substrate 100 by using semiconductor processes such as doping, etching, film forming, and the like. The second region 1002 may surround the first region 1001 completely as shown in fig. 2, or may surround the first region 1001 partially (for example, the second region 1002 surrounds three or two sides of the first region 1001), which is not limited in this specification.

A ball grid array, wherein the ball grid array comprises a plurality of contact solder balls 110 distributed on the first side, and the density of the contact solder balls 110 distributed in the first area 1001 is less than that of the contact solder balls 110 distributed in the second area 1002. The contact solder balls 110 located in the same area generally follow the same standard spacing rule, such as a pitch of 1.27mm or 1.0 mm. Some of the contact balls 110 in the ball grid array are electrically connected to a core power supply of the integrated circuit component 130, and some of the contact balls 110 in the ball grid array are electrically connected to a negative power supply input (e.g., ground) of the integrated circuit component 130. Integrated circuit components 130 are disposed on a second side 102 opposite the first side 101 of the first substrate 100, and some of the contact balls 110 in the ball grid array connect input/output signals to the integrated circuit package structure 10. Without limiting the present disclosure, the pattern formed by the contact balls 110 in the ball grid array may be square, rectangular, circular (referring to fig. 4, fig. 4 is a schematic view of the first side 101 of the first substrate 100 provided by an embodiment of the present disclosure), diamond, or any other grid Configuration (Lattice Configuration). In some exemplary embodiment modes, the pattern formed by the contact balls 110 in the ball grid array may also be asymmetric or have limited symmetry. The contact solder balls 110 may be spherical in shape, in which case the contact solder balls 110 may also be referred to as contact balls. Of course, in some exemplary embodiments of the present description, the shape of the contact solder ball 110 may also be an ellipsoid shape (refer to fig. 10) or other shapes, which is not limited in the present description. The material of the contact balls 110 may include metallic tin, and the forming process may include Reflow Soldering (Reflow Soldering).

In this embodiment, the integrated circuit package structure 10 includes a first capacitor 120, the first capacitor 120 is disposed in the first region 1001, the first capacitor 120 is connected to the interconnection trace 162 on the first substrate 100 through the pad 163, and is connected to the contact solder ball 110 through the interconnection trace 162 so as to be electrically connected to the integrated circuit component 130, more specifically, referring to fig. 5, fig. 5 is a schematic connection diagram of the first capacitor 120 and the contact solder ball 110, the first capacitor 120 includes a capacitor body 121, a first pole 122 and a second pole 123, the first pole 122 is connected to a first contact solder ball 110a electrically connected to the core power supply, and the second pole 123 is connected to a second contact solder ball 110b electrically connected to the ground terminal. When the number of the first capacitors 120 is plural, the connection relationship between the plural first capacitors 120 connected in parallel is parallel, and according to the physical knowledge, the sum of the total capacitance of the plural first capacitors 120 connected in parallel is the sum of the capacitance values of the respective first capacitors 120 connected in parallel. Further shown in fig. 5 is an insulating layer 161 on the first side 101, the insulating layer 161 is used to protect the interconnection trace 162 and other elements on the first side 101 from water and oxygen, and the first pole 122 and the second pole 123 of the first capacitor 120 are respectively connected to different interconnection traces 162 through pads 163, so as to electrically connect to the first contact solder ball 110a and the second contact solder ball 110 b.

The integrated circuit component 130 may be disposed on the first substrate 100 in a flip-chip manner, and the signal contacts on the integrated circuit component 130 are electrically connected to the metal traces on the first substrate 100 through metal bumps (bumps). The integrated circuit component 130 is a main load of the integrated circuit system, and when the load current is unchanged or changes little, the core power supply can meet the requirement that the system provides a stable voltage for the load, and the voltage across the first capacitor 120 is consistent with the core power supply voltage. When the load current of the system is greatly changed due to the drastic changes of the operation amount, the concurrency amount and the like, the core power supply voltage of the integrated circuit component is obviously fluctuated due to the large and quick jump of the load current, and the first capacitor 120 serving as an energy storage element can provide energy for the core power supply, so that the fluctuation of the core power supply voltage is reduced, and the voltage stabilizing effect is achieved. In addition, because the density of the contact solder balls 110 in the first region 1001 on the first side 101 of the first substrate 100 is low, a large space is provided for the first capacitor 120, on one hand, the convenience of the first capacitor 120 in the first region 1001 is improved, the difficulty in manufacturing the integrated circuit package structure 10 is reduced, and the yield of the integrated circuit package structure is improved, on the other hand, the number of the first capacitors 120 in the first region 1001 is increased, it is easy to understand that the large number of the first capacitors 120 can provide large energy storage capacitors for the system, only a small voltage change is needed, the large energy storage capacitors can provide a large enough current, the requirement of load transient current is met, the change of the core power supply voltage is within an allowable range, and the stability of the system is improved.

The first Capacitor 120 may be a Ceramic Capacitor (Ceramic Capacitor) or a silicon Capacitor, and the like having characteristics of compact structure, low Equivalent Inductance (ESL), and the like. In addition, since the ball grid array is required to be connected to other package substrates such as Printed Circuit Boards (PCBs), the first capacitor 120 is also required to have a low height, and in conjunction with fig. 3 and 5, the height H of the first capacitor 120 is smaller than the height H of the contact solder ball 110, so as to ensure good electrical contact between the contact solder ball 110 and other package substrates, and avoid the problem of abnormal electrical contact between the contact solder ball 110 and other package substrates due to the over-high first capacitor 120. In some embodiments of the present disclosure, the first capacitor 120 may be a capacitor with a package size of 0402 or 0201, the first capacitor height is typically less than 0.35mm, and the capacitance is less than 2.2 μ F. When the first capacitor 120 is a ceramic capacitor, the characteristic of the ceramic capacitor that the impedance curve is low near the middle frequency band (100 MHz) makes the core voltage drop caused by the load fluctuation smaller, so as to achieve a good decoupling effect on the middle frequency noise of the core power supply of the integrated circuit component 130. In the embodiment shown in fig. 5, the height H of the contact ball 110 refers to the distance between the point of the contact ball 110 farthest from the first side 101 and the surface of the first side 101, and correspondingly, the height H of the first capacitor 120 refers to the distance between the point of the first capacitor 120 farthest from the first side 101 and the surface of the first side 101. Of course, in other exemplary embodiments of the present disclosure, the height H of the contact solder ball 110 may also refer to a distance between a farthest point of the contact solder ball 110 from the interconnect trace 162 and the interconnect trace 162, and the height H of the first capacitor 120 may also refer to a distance between a farthest point of the first capacitor 120 from the interconnect trace 162 and the interconnect trace 162. In summary, the height of the contact solder ball 110 is the same as the comparison reference point (surface) of the height of the first capacitor, and this description is not exhaustive.

In an exemplary embodiment of the present description, referring to fig. 6 in combination with fig. 2 and 4, fig. 6 is a schematic diagram of the first side 101 of the first substrate 100, and in fig. 2 and 4, the density of the contact solder balls 110 distributed in the first area 1001 is zero, that is, the distribution area of the ball grid array, which is not used for disposing the contact solder balls 110 in the first area 1001, is the second area 1002. In the present exemplary embodiment, since the first region 1001 is not used for disposing the contact solder balls 110, a large space is provided for the first capacitor 120, and in the first aspect, the convenience of disposing the first capacitor 120 is improved. In the second aspect, because the first region 1001 has no contact solder ball 110, the possibility of the first capacitor 120 being in erroneous contact with the adjacent contact solder ball 110 during the setting process is reduced to a certain extent, and the manufacturing yield of the integrated circuit package structure 10 is improved. In the third aspect, since all the first regions 1001 are used for disposing the first capacitors 120, a larger number of first capacitors 120 can be disposed in the first regions 1001 with the same size, and the capacitance of the core power storage capacitor is increased, similar to the foregoing description, the storage capacitor with a larger capacitance can provide a better voltage stabilizing function for the core power of the integrated circuit component 130, thereby improving the system stability. In fig. 6, the density of the contact solder balls 110 in the first region 1001 is greater than zero, so that the stress difference between the first region 1001 and the second region 1002 when the first substrate 100 is soldered to another package substrate can be reduced, the possibility of warpage of the first substrate 100 can be reduced, and the yield of the integrated circuit package structure can be increased.

In an exemplary embodiment of the present description, the ratio of the area of the first region 1001 to the sum of the areas of the first region 1001 and the second region 1002 ranges from 10% to 20%, i.e., 10% ≦ MA/(MA + MB) ≦ 20%, where MA represents the area of the first region 1001 and MB represents the area of the second region 1002. The inventor finds that limiting the ratio of the area of the first region 1001 to the sum of the areas of the first region 1001 and the second region 1002 to 10% -20% can prevent the first substrate 100 from warping due to the soldering stress of the contact solder balls 110 after being packaged with other package substrates on the basis of satisfying the requirement of improving the stability of the core power supply 131.

In an exemplary embodiment of the present disclosure, referring to fig. 7, fig. 8, and fig. 9 in combination with fig. 3, fig. 8 is a schematic diagram of a first side 101 of a first substrate 100 of an integrated circuit package structure 10, fig. 7 is a schematic diagram of a cross-sectional structure along a line BB 'in fig. 6, and fig. 9 is a schematic diagram of a cross-sectional structure along a line CC' in fig. 8, where an orthographic projection of the first region 1001 on the first side 101 at least partially overlaps an orthographic projection of the core power supply 131 on the first side 101. In the embodiment shown in fig. 9, the orthographic projection of the first region 1001 on the first side 101 overlaps with one part of the orthographic projection of the core power supply 131 on the first side, and the other part does not overlap, so that the decoupling path between the first capacitor 120 and the core power supply 131 arranged in the overlapping region is relatively short, which is beneficial to improving the capacitive filtering effect of the first capacitor 120 in the overlapping region, and ensuring that the first capacitor 120 has a good voltage stabilizing effect.

In the exemplary embodiment shown in fig. 3 and 7, an orthographic projection of the first area 1001 on the first side 101 coincides with an orthographic projection of the core power supply 131 on the first side, so that distances between the first capacitors 120 and the core power supply 131 arranged in the first area 1001 are both small, that is, decoupling paths of the first capacitors 120 arranged in the first area 1001 are both relatively short, which is beneficial to improving a filtering effect of the first capacitors 120 and ensuring that the first capacitors 120 have a good voltage stabilizing effect.

Of course, in some exemplary embodiments of the present disclosure, the orthogonal projection of the first region 1001 on the first side 101 and the orthogonal projection of the core power supply 131 on the first side may also have no overlapping region, and the first region 1001 designed in this way may meet some special packaging requirements, which is beneficial to improving the applicability of the integrated circuit package structure 10.

In an exemplary embodiment of the present description, referring to fig. 10, fig. 10 is a schematic cross-sectional structure diagram of an integrated circuit package structure 10, where the first substrate further includes: a recess 1001a in the first region 1001, and the first capacitor 120 is disposed in the recess 1001 a.

Disposing the first capacitor 120 in the recessed area 1001a is helpful to increase the space of the first capacitor 120 in the longitudinal direction (the direction perpendicular to the first side 101 and the second side 102 of the first substrate 100), so that when the first capacitor 120 is disposed on the first substrate 100, the operation space is larger, which is beneficial to increasing the success rate of disposing the first capacitor 120, thereby increasing the preparation yield of the whole integrated circuit package structure 10. In addition, due to the existence of the recessed region 1001a, the space in the longitudinal direction where the first capacitor 120 can be placed becomes larger, and on the premise that the height of the first capacitor 120 is ensured to be smaller than the height of the contact solder ball 110, the first capacitor 120 with a higher height can be selected, so that a greater degree of freedom can be provided for the size selection of the first capacitor 120.

In an exemplary embodiment of the present description, the area of the recessed region 1001a may be equal to the area of the first region 1001, i.e. an orthographic projection of the recessed region 1001a on the first side 101 may coincide with an orthographic projection of the first region 1001 on the first side 101 (as shown in fig. 10) to provide as much accommodation space as possible for the first capacitor 120. Of course, in other exemplary embodiments of the present disclosure, the area of the recessed region 1001a may also be smaller than the area of the first region 1001, that is, in the orthographic projection of the recessed region 1001a on the first side 101, in the orthographic projection of the first region 1001 on the first side 101, the recessed region 1001a thus configured may provide a larger fault tolerance for the formation of the recessed region 1001a, and avoid a formation process (e.g., an etching process or a thinning process) of the recessed region 1001a from causing an adverse effect on a region other than the first region 1001. The specification does not limit the specific size of the recessed region 1001a, which is determined according to the actual situation.

In an exemplary embodiment of the present disclosure, referring to fig. 11, fig. 11 is an enlarged schematic view of a partial region of the first side 101 of the first substrate 100, the number of the first capacitors 120 is plural, the plural first capacitors 120 are arranged in the first region 1001 in an array manner, and the first capacitors 120 in the same row are oriented in the same direction.

In the present embodiment, the orientation of the first capacitor 120 refers to the orientation of the first pole 122 (e.g., positive pole) or the second pole 123 (e.g., negative pole) of the first capacitor 120 relative to the capacitor body 121, in fig. 11, the first pole 122 of the first capacitor 120 in the first row from top to bottom is oriented upward of the paper (i.e., in the direction indicated by arrow DR 1) relative to the capacitor body 121, and the second pole 123 is oriented downward of the paper relative to the capacitor body 121. The orientation of the first capacitors 120 in different rows may be the same or different (e.g., the orientation of the first capacitors 120 in the second row may be different from the orientation of the first capacitors 120 in the first row). Since the interconnection trace 162 connected to the first pole 122 cannot intersect with the interconnection trace 162 connected to the second pole 123, so as to avoid short-circuiting the first capacitor 120, the interconnection traces 162 connected to the first pole 122 can be all arranged on one side of the first capacitor, and the interconnection traces 162 connected to the second pole 123 can be all arranged on the other side of the first capacitor, which is beneficial to simplifying the design difficulty of the interconnection traces 162 and reducing the risk of short-circuiting the first capacitor 120.

In an exemplary embodiment of the present description, still referring to fig. 11, the first capacitors 120 in the same row are oriented perpendicular to the row direction, and the first poles 122 of the first capacitors 120 in the same row are connected to at least one contact ball 110 in a row of contact balls 110 in the ball grid array.

The second pole 123 of the first capacitance 120 in the same row is connected to at least one contact ball 110 in another row of contact balls 110 in the ball grid array.

It will be readily appreciated that the row direction, i.e. the direction in which "rows" of the array extend, and the column direction, i.e. the direction in which "columns" of the array extend, is parallel to the column direction and perpendicular to the row direction as indicated by the pointing direction of arrow DR1 in fig. 11 with reference to fig. 11. The first capacitors 120 in the same row are oriented perpendicular to the row direction, and the contact solder balls 110 connected with the first poles 122 and the second poles 123 of the first capacitors 120 in the same row are distributed in different rows, so that the possibility of cross contact between the first poles 122 and the second poles 123 when the first poles 122 and the second poles 123 are connected with the contact solder balls 110 is reduced, and the preparation yield of products is improved.

In fig. 11, the first pole 122 of each first capacitor 120 is connected to a solder contact ball 110, and the second poles 123 of a plurality of first capacitors 120 are connected to the same solder contact ball 110. In other exemplary embodiments, the first poles 122 of a plurality of first capacitors 120 may be connected to the same contact solder ball 110, or the second poles 123 of the first capacitors 120 may be connected to different contact solder balls 110, which is not limited in this specification.

Exemplary Integrated Circuit System

Embodiments of the present specification also provide an integrated circuit system, which, with reference to fig. 12 and 13, includes: the integrated circuit package structure 10 according to any of the above embodiments, and a printed circuit board 140, the printed circuit board 140 includes a third side 141 and a fourth side 142, the third side 141 includes at least one coupling region 143, the coupling region 143 is coupled to the ball grid array of the first substrate 100, a second capacitor 150 is disposed on the fourth side 142, an orthogonal projection of the second capacitor 150 on the fourth side 142 and an orthogonal projection of the contact solder ball 110 on the fourth side 142 do not overlap each other.

The coupling area 143 on the printed circuit board 140 is used for arranging the first substrate 100 integrated with the integrated circuit components 130, the printed circuit board 140 is electrically connected with the integrated circuit components through the ball grid array on the first substrate 100, different integrated circuit components 130 may have different functions, for example, in fig. 13, two integrated circuit components 130 may respectively have a data and/or instruction storage function and an operation function, in actual operation, one of the integrated circuit components 130 may perform corresponding operation by calling the data and/or instructions stored in the other integrated circuit component 130, and the like. The number of the coupling regions 143 on the printed circuit board 140 is not limited, and the functions of the integrated circuit components 130 on the first substrate 100 coupled and connected to the coupling regions 143 are not limited, which depends on the actual situation.

In this embodiment, the second capacitor 150 disposed on the fourth side 142 of the printed circuit board 140 is electrically connected to the integrated circuit device 130 through the interconnection layer 144 inside the printed circuit board 140 and at least some of the contact balls 110 in the ball grid array. Since the second capacitor 150 is disposed on the fourth side 142 of the printed circuit board 140, which is not blocked by other components, the second capacitor 150 with a larger package and a larger capacity can be disposed to stabilize the voltage fluctuation of the core power of the integrated circuit component 130, thereby improving the system stability.

In an exemplary embodiment of the present specification, a package size of the first capacitor 120 is smaller than a package size of the second capacitor 150, or a capacity of the first capacitor 120 is smaller than a capacity of the second capacitor 150.

As mentioned above, the first capacitor 120 may be a capacitor with a package size of 0402 or 0201, the first capacitor height is typically less than 0.35mm, and the capacitance is less than 2.2 μ F. The second capacitor 150 can be a capacitor with a package size of 0805 or more, and the capacitance of the second capacitor 150 can be 22 muF-100 muF. According to the capacitive decoupling principle, when the core power supply of the integrated circuit component 130 operates in a low frequency band, such as several tens of kHz, since the inductive reactance generated by the low frequency signal on the inductor can be ignored, the equivalent inductance (ESL) of the first capacitor 120 and the second capacitor 150 can be approximately zero in the low frequency band, and when the load needs a large current instantly, the first capacitor 120 and the second capacitor 150 can supply power to the load in time, so that the fluctuation of the core power supply is reduced or eliminated. Since the frequency is low, the discharge time is also long (reciprocal of the frequency), and thus the second capacitor 150 with large capacity can discharge for a long time, and a good voltage stabilizing effect can be achieved for the core power supply.

When the core power supply works at medium and high frequency and the load changes, the equivalent inductance formed on the first capacitor 120 and the second capacitor 150 cannot be ignored, and at this time, the first capacitor 120 with small package, small capacity and low ESL can better play a role of quickly providing current for the load, so that the first capacitor 120 can more quickly provide energy for the core power supply, the normal work of integrated circuit components is ensured, and the system stability is improved.

That is, in general, when the package size of the first capacitor 120 is smaller than the package size of the second capacitor 150, and the capacity of the first capacitor 120 is smaller than the capacity of the second capacitor 150, the first capacitor 120 may provide a better energy supplement effect for the core power supply at a middle frequency (e.g., 100 MHz) or a high frequency, while the second capacitor 150 may provide a better energy supplement effect for the core power supply at a low frequency, and the first capacitor 120 and the second capacitor 150 complement each other, so that the core power supply can stably operate in a full frequency band (especially in a low frequency band and a middle frequency band), and the system stability is improved.

In an exemplary embodiment of the present description, still referring to fig. 12, the fourth side includes: a third region 145, an orthographic projection of the third region 145 on the first side 101 at least partially overlapping an orthographic projection of the region where the first capacitance is disposed, the second capacitance 150 being disposed in the third region 145.

In this embodiment, the area where the first capacitor is disposed is taken as the first area 1001 for explanation, and in other embodiments of this specification, when the integrated circuit package structure is the package structure shown in fig. 15, the area where the first capacitor is disposed may also be a decoupling area, which is not limited in this specification.

The third region 145 is used for disposing the second capacitor 150, and when the orthographic projection of the third region 145 on the first side 101 and the orthographic projection of the first region 1001 on the first side 101 at least partially overlap, because the density of the contact solder balls 110 in the first region 1001 is smaller or the contact solder balls 110 are not used for disposing, the degree of freedom of disposing the second capacitor 150 in the overlapping region can be increased without considering the position relationship between the second capacitor 150 and the contact solder balls 110.

When the orthographic projection of the third region 145 on the first side 101 and the orthographic projection of the first region 1001 on the first side 101 completely coincide, the degree of freedom in the arrangement of the second capacitor 150 is increased, and when the first region 1001 is arranged in coincidence with the core power supply of the integrated circuit component, the decoupling path between the second capacitor 150 and the core power supply is relatively short, which is beneficial to improving the decoupling effect of the second capacitor 150, reducing the core power supply fluctuation, and improving the system stability.

In an exemplary embodiment of the present disclosure, referring to fig. 14, fig. 14 is an enlarged schematic view of a partial region of a fourth side 142 of a printed circuit board 140, where the number of the second capacitors 150 is multiple, the multiple second capacitors 150 are arranged in an array manner, in a column of the second capacitors 150, the second capacitors 150 face in parallel with a row direction, and a first pole 151 of the second capacitors 150 is disposed toward a preset side, and the preset side includes a vertical side closest to the second capacitors 150 among sides enclosing the third region 145.

In fig. 14, similarly to the first capacitor 120, in the second capacitor 150, a capacitor body 152 and a second pole 153 of the second capacitor 150 are included in addition to the first pole 151 of the second capacitor 150. As mentioned above, the row direction refers to the extending direction of "rows" in the ball grid array, for example, the direction indicated by arrow DR2 in fig. 14, and in addition to the orientation of the second capacitor 150 being arranged parallel to the row direction, the first pole 151 of the second capacitor 150 is arranged towards the predetermined side. Taking fig. 14 as an example, for the second capacitors 150 in the left column, the vertical side 1451 of the third region 145 is a preset side of the second capacitors 150 in the column, and for the second capacitors 150 in the right column, the vertical side 1452 of the third region 145 is a preset side of the second capacitors 150 in the column. The first poles 151 of the second capacitors 150 are all oriented to the outside (i.e., to the preset side), so that the first poles 151 connected to the core power supply are oriented to the same direction, which is beneficial to simplifying the wiring design on the fourth side 142, and the first poles 151 are all oriented to the outside, which is beneficial to increasing the layout space of the wirings connected to the first poles 151, reducing the design difficulty and improving the preparation yield.

It should be noted that, because the package size of the second capacitor 150 is larger, in fig. 12, 13 and 14, the second capacitors 150 in one third area 145 are all disposed in two columns, which is beneficial to simplify the arrangement of the second capacitors 150 and the design of the traces connected to the second capacitors 150. However, in other exemplary embodiments of the present specification, the second capacitors 150 in the third region 145 may also be arranged in three or more columns according to actual situations, and the present specification does not limit this.

In an exemplary embodiment of the present description, still referring to fig. 13, the integrated circuit system 20 further includes: a first power supply terminal 171, a second power supply terminal 172, and a third capacitor 173.

The third side 141 includes at least two coupling regions, the third capacitor 173, the first power terminal 171 and the second power terminal 172 are disposed between adjacent coupling regions, a first pole of the third capacitor 173 is connected to the first power terminal 171, and a second pole of the third capacitor 173 is connected to the second power terminal 172.

In this embodiment, the first power terminal 171 and the second power terminal 172 may be a positive terminal and a negative terminal of a system power supply, respectively, the system power supply is a power supply for providing an operating voltage for integrated circuit components carried on the printed circuit board 140. The third capacitor 173 disposed on the third side 141 of the printed circuit board 140 may provide better decoupling for low frequency power signals (e.g., power signals less than or equal to 30 MHz), thereby improving the stability of the system power.

Exemplary Package Structure

One or more embodiments of the present specification further provide an integrated circuit package structure 10, as shown in fig. 15, where the integrated circuit package structure 10 includes a first substrate 100, the first substrate 100 includes a package side 202 and a circuit side 201 opposite to the package side 202, the circuit side 201 is used for disposing an integrated circuit component 130, the package side 202 includes a decoupling region 2021 and a soldering region 2022 surrounding the decoupling region 2021, the decoupling region 2021 is used for providing a disposing space for a first capacitor 120, and the first capacitor 120 is used for reducing or eliminating power supply fluctuation of a core power supply 131 of the integrated circuit component 130.

The package side 202 of the first substrate 100 refers to the side that is packaged with other package substrates, and the circuit side 201 of the first substrate 100 refers to the side on which the integrated circuit component 130 is disposed. It is understood that, in order to realize the soldering of the package side 202 with other package substrates, the package side 202 is usually used to arrange a ball grid array including a plurality of contact solder balls 110, the contact solder balls 110 are mainly arranged in the soldering region 2022, and the decoupling region 2021 is mainly used to provide a placement space for the first capacitor 120.

In order to provide as much space as possible for the first capacitor 120, in one embodiment of the present description, the decoupling region 2021 is not used for disposing the contact solder ball 110.

In order to reduce the risk of warpage of the first substrate 100 and the like due to the provision of the decoupling area 2021, in one embodiment of the present description, said decoupling area 2021 is used for providing a small number of contact solder balls 110, i.e. the density of contact solder balls 110 in the decoupling area 2021 is smaller than the density of contact solder balls 110 in the soldering area 2022.

That is, in general, the decoupling region 2021 is mainly used for placing the first capacitor 120, in other words, the area of the decoupling region 2021 where the first capacitor 120 is placed is larger than the area where the contact solder ball 110 is placed.

In this embodiment, a special decoupling area 2021 is disposed in the package side 202 for the first capacitor 120 to provide a larger placing space for the first capacitor 120, so that the difficulty in disposing the first capacitor 120 is reduced on the premise that the first capacitor 120 eliminates or reduces the fluctuation of the core power supply 131 of the integrated circuit component 130, and meanwhile, the special decoupling area 2021 is also beneficial to placing a relatively larger number of first capacitors 120, and is beneficial to optimizing the capability of the first capacitor 120 in the decoupling area 2021 to suppress the fluctuation of the core power supply 131.

Exemplary packaging method

Fig. 16 is a flowchart illustrating a method for packaging an integrated circuit according to an exemplary embodiment of the present disclosure, the method including:

s101: providing a first substrate comprising a first side and a second side opposite the first side, the first side comprising a first area and a second area surrounding the first area.

S102: forming an integrated circuit component on the second side, the integrated circuit component including a core power supply.

S103: forming a ball grid array on the first side, wherein the ball grid array comprises a plurality of contact solder balls, and the density of the contact solder balls distributed in the first area is less than that of the contact solder balls distributed in the second area.

In step S103, during forming the ball grid array, the contact solder balls may be prepared in a first area and a second area according to a conventional ball grid array forming process, and then a part or all of the contact solder balls in the second area are removed, so that the density of the contact solder balls distributed in the first area is less than the density of the contact solder balls distributed in the second area. It is of course also possible to use different ball grid array formation processes in the first and second regions, even if initially the density of the contact balls distributed in the first region is lower than the density of the contact balls distributed in the second region. The specification does not limit the specific forming process of the ball grid array, which is determined according to the actual situation.

S104: and forming a first capacitor in the first area, wherein the first capacitor is connected with at least two contact solder balls so as to be electrically connected with the integrated circuit component.

It should be understood that, although the steps in the flowchart of fig. 16 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in a strict order unless explicitly stated in the specification, and may be performed in other orders. Moreover, at least a portion of the steps in fig. 16 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

For each specific structure and beneficial effect of the package structure formed by using the above-mentioned packaging method, reference may be made to the above description of "exemplary package structure", and this description is not repeated herein.

Exemplary electronic device

One or more exemplary embodiments of the present specification also provide an electronic device including the integrated circuit system according to any one of the above embodiments.

Exemplary chip

One or more exemplary embodiments of the present specification also provide a server chip including the integrated circuit system according to any one of the above embodiments.

The server chip generally has the characteristics of large size, high computation and high concurrency, and by adopting the integrated circuit system of any one of the embodiments, the first capacitor arranged in the first side of the first substrate in the integrated circuit system can provide energy for the core power supply of the server chip when the server chip performs high concurrency or high computation operation, so that the fluctuation of the core power supply is reduced or reduced, and the normal operation of the server chip is ensured. The server chip may include one of a memory and a processor, or may be an integrated chip integrated with a plurality of structures such as a memory and a processor, and the specific type and form of the server chip are not limited in this specification, which is determined by the actual situation.

The basic principles of the present specification have been described above with reference to specific embodiments, but it should be noted that advantages, effects, and the like, mentioned in the specification are only examples and are not limiting, and the advantages, effects, and the like, should not be considered as necessarily possessed by various embodiments of the specification. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the description is not intended to be exhaustive or to be limited to the precise details set forth.

Claims (16)

1. An integrated circuit package structure, comprising:

a first substrate including a first side and a second side opposite the first side, the first side including a first area and a second area surrounding the first area;

a ball grid array including a plurality of contact balls distributed on the first side, the density of the contact balls distributed in the first area being less than the density of the contact balls distributed in the second area;

an integrated circuit component located on the second side;

a first capacitor disposed in the first region, the first capacitor being connected to at least two of the contact solder balls for electrical connection to the integrated circuit component.

2. The integrated circuit package structure of claim 1, wherein a density of the contact solder balls distributed in the first area is zero.

3. The integrated circuit package structure of claim 1, wherein a height of the first capacitor is less than a height of the contact solder ball.

4. The integrated circuit package structure of any of claims 1-3, wherein the integrated circuit component includes a core power supply, and wherein an orthographic projection of the first region on the first side at least partially overlaps an orthographic projection of the core power supply on the first side.

5. The integrated circuit package structure of claim 4, wherein an orthographic projection of the first area on the first side coincides with an orthographic projection of the core power supply on the first side.

6. The integrated circuit package structure of any one of claims 1-3, wherein the number of the first capacitors is plural, the plural first capacitors are arranged in the first region in an array manner, and the first capacitors in the same row are oriented in the same direction.

7. The integrated circuit package structure of claim 6, wherein the first capacitors in the same row are oriented perpendicular to the row direction, and the first poles of the first capacitors in the same row are connected to at least one contact ball in a row of contact balls in the ball grid array;

the second pole of the first capacitance in the same row is connected to at least one contact ball in another row of contact balls in the ball grid array.

8. The integrated circuit package structure of any of claims 1-3, wherein the first substrate further comprises: a recessed region in the first region;

the first capacitor is disposed in the recess.

9. An integrated circuit package structure, comprising:

the first substrate comprises a packaging side and a circuit side opposite to the packaging side, wherein the circuit side is used for arranging an integrated circuit component, the packaging side comprises a decoupling area and a welding area surrounding the decoupling area, the decoupling area is used for providing an arrangement space of a first capacitor, and the first capacitor is used for reducing or eliminating core power supply fluctuation of the integrated circuit component.

10. An integrated circuit system, comprising:

the integrated circuit package structure of any of claims 1-9, comprising a ball grid array;

a printed circuit board comprising a third side and a fourth side, the third side comprising at least one coupling region that couples with a ball grid array of the integrated circuit package structure;

and the second capacitor is arranged on the fourth side, and the orthographic projection of the second capacitor on the fourth side and the orthographic projection of the contact solder balls of the ball grid array on the fourth side do not overlap.

11. The integrated circuit system of claim 10, wherein a package size of the first capacitor of the integrated circuit package structure is smaller than a package size of the second capacitor; or the like, or, alternatively,

the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

12. The integrated circuit system of any of claims 10-11, wherein the fourth side comprises: a third region, wherein an orthographic projection of the third region on the first side at least partially overlaps with an orthographic projection of a setting region of the first capacitor in the integrated circuit package structure on the first side of the first substrate of the integrated circuit package structure;

the second capacitor is disposed in the third region.

13. The integrated circuit system according to claim 12, wherein the second capacitors are plural in number, and the plural second capacitors are arranged in an array;

in one column of the second capacitors, the orientation of the second capacitors is parallel to the row direction, the first poles of the second capacitors face preset edges, and the preset edges include a vertical edge which is closest to the second capacitors in the third region outer edge.

14. The integrated circuit system of any of claims 10-11, further comprising: a first power supply terminal, a second power supply terminal, and a third capacitor;

the third side includes at least two of the coupling regions, the third capacitor, the first power terminal, and the second power terminal are disposed between adjacent coupling regions, a first pole of the third capacitor is connected to the first power terminal, and a second pole of the third capacitor is connected to the second power terminal.

15. A method of packaging an integrated circuit, comprising:

providing a first substrate comprising a first side and a second side opposite the first side, the first side comprising a first area and a second area surrounding the first area;

forming an integrated circuit component on the second side;

forming a ball grid array on the first side, the ball grid array including a plurality of contact solder balls, the density of the contact solder balls distributed in the first area being less than the density of the contact solder balls distributed in the second area;

and forming a first capacitor in the first area, wherein the first capacitor is connected with at least two contact solder balls so as to be electrically connected with the integrated circuit component.

16. An electronic device, comprising: the integrated circuit system of any of claims 10-14.

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