CN111183516A - 用于集成电路的线中屏蔽栅 - Google Patents

用于集成电路的线中屏蔽栅 Download PDF

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CN111183516A
CN111183516A CN201880064420.2A CN201880064420A CN111183516A CN 111183516 A CN111183516 A CN 111183516A CN 201880064420 A CN201880064420 A CN 201880064420A CN 111183516 A CN111183516 A CN 111183516A
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mol
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metal resistor
interconnect
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CN111183516B (zh
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戈立新
杨斌
陆叶
鲍军静
P·奇达姆巴拉姆
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Qualcomm Inc
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Abstract

公开了一种集成电路(IC)中的线中(MOL)屏蔽栅。在IC中的MOL层中制造一个或多个金属电阻器来减少半导体区域中的栅极到漏极寄生电容。通过在MOL层中制造金属电阻器，金属电阻器可以被定位为靠近半导体器件，以在不增加当前制造工艺的成本或缺陷的情况下，更有效地减小半导体器件的寄生电容。当前的制造工艺可以用于在MOL中创建触点来制造金属电阻器。

Description

用于集成电路的线中屏蔽栅
相关申请的交叉引用
本专利申请要求于2017年10月3日提交的题为“MIDDLE-OF-LINE SHIELDED GATEFOR INTEGRATED CIRCUITS”的申请号15/723,224的优先权，本专利申请已转让给其受让人，并且明确地通过引用并入本文。
技术领域
本发明总体上涉及场效应晶体管(FET)，并且更具体地涉及减小用于集成电路(IC)的金属氧化物半导体场效应晶体管(MOSFET)中的栅极到漏极电容。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)在许多高输入阻抗或高增益电路、高速切换电路或射频(RF)集成电路(IC)(例如，在机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、智能电话、平板电脑、平板手机、计算机、便携式计算机、台式计算机、个人数字助理(PDA)、监视器、计算机监视器、电视、调谐器、收音机、卫星收音机、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器、便携式数字视频播放器和汽车中使用的)中是有价值的组件。功率MOSFET的优势通常包括高切换速度和相对低的导通电阻。
屏蔽栅极MOSFET是优选的，原因在于它们提供减小的栅极到漏极电容、减小的导通电阻以及增加的晶体管击穿电压。通过屏蔽栅极不受漂移区域中的电场的影响，屏蔽栅极MOSFET结构实质上减小了栅极到漏极电容。屏蔽栅极MOSFET结构还为器件的击穿电压提供了漂移区域中的少数载流子浓度更高以及因此的导通电阻更低的附加益处。
将栅极MOSFET屏蔽的常规方法是在栅极和下层的漏极之间制造硅化钨(WSi)法拉第屏蔽。但是，制造WSi法拉第屏蔽需要附加的多晶硅沉积、掩膜和蚀刻。这些附加步骤增加成本、要求附加的规范并且可能增加IC的缺陷。因此，需要能够降低成本和工艺流程中的步骤，并且仍然能够有效地减小栅极到漏极寄生电容的在IC中制造屏蔽栅极MOSFET的设备和过程。
发明内容
本文所公开的各方面包括集成电路(IC)中的线中(MOL)屏蔽栅。为此，在本文所公开的某些方面中，在IC的MOL层中制造一个或多个金属电阻器来屏蔽IC。MOL层被形成在包括例如MOSFET之类的器件的IC的线前端(FEOL)部分中的有源半导体区域之上并与其相邻。(多个)金属电阻器可以通过MOL层中形成的触点耦合到(多个)互连层中的互连线，从而例如耦合到电压源、片上RF和/或IC中的功率电路。
因此，通过在IC的MOL层中制造金属电阻器，可以将金属电阻器有利地定位为非常靠近半导体器件(例如，晶体管)，以更准确地屏蔽半导体器件。此外，通过在MOL层中提供金属电阻器，也可以使用与在MOL层中创建触点所使用的相同制造工艺来在MOL层中制造金属电阻器。此外，由于已在IC中提供了MOL层来提供有源半导体层中的半导体器件与互连层之间的触点，所以可能不需要附加的面积来在IC中提供金属电阻器。
附图说明
图1是图示集成电路(IC)的截面侧视图的图，集成电路(IC)包括具有金属电阻器的线中(MOL)屏蔽栅极；
图2是图示制造MOL屏蔽栅极(例如，图1中的IC中的MOL屏蔽栅)的示例性过程的流程图；
图3A-图3F是在IC中制造MOL屏蔽栅极(例如，图1中的IC中的MOL屏蔽栅极)的示例性工艺阶段；
图4是包括MOL屏蔽栅极的示例性系统的概括表示；以及
图5是包括射频(RF)组件和MOL屏蔽栅极的示例性无线通信设备的框图。
具体实施方式
参考附图，描述了本公开的若干示例性方面。词语“示例性”在本文中用于表示“用作示例、实例或图示”。本文中被描述为“示例性”的任何方面不必被解释为比其他方面优选或有利。
图1是图示用于IC 102的半导体管芯100的截面侧视图的图，IC 102包括MOL屏蔽栅极104。在该示例中，MOL屏蔽栅极104被提供在IC 102的芯片上。MOL屏蔽栅极104包括金属电阻器106，金属电阻器106由半导体管芯100的MOL区域110的MOL层108中提供的金属材料制造。应注意，金属电阻器106存在于当前的制造工艺中，并且因此，不存在与制造金属电阻器106相关联的附加蚀刻、掩模分层或成本。如下所述，金属电阻器106在MOL区域110处制造，从而提供屏蔽栅并有效减小栅极到漏极寄生电容。金属电阻器106具有基于金属电阻器106的材料和尺寸的电阻。MOL层108被形成在衬底116上设置的半导体管芯100的线前端(FEOL)区域114中的一个或多个有源半导体层112之上，并与之相邻。有源半导体层112包括半导体器件(例如诸如MOSFET)。在该示例中，MOSFET是包括Fin 122的FinFET 120，FinFET120提供导电沟道，其中栅极材料124被布置在Fin 122之上和/或与其邻近。
因为在该示例中，金属电阻器106被设置在MOL层108中在有源半导体层112正上方和/或与有源半导体层112紧邻，所以MOL层108中的金属电阻器106可以有利地定位为非常靠近有源半导体层112中的半导体器件(例如，FinFET 120)，以更有效地减小栅极到漏极寄生电容。
为了提供到MOL屏蔽栅极104的连接并将电压Vss引导到金属电阻器106，在MOL层108中提供了第一触点126(1)。第一触点126(1)电耦合到金属电阻器106的触点区域128。例如，第一触点126(1)可以是由钨(W)材料制成的导电接触焊盘。在该示例中，第一触点126(1)物理接触触点区域128。第一和第二垂直互连通路ViasO(VO)130(1)、130(2)在半导体管芯100的互连区域134中的互连层132中制造，与第一和第二触点126(1)、126(2)对准接触。例如，互连层132被示出为直接在MOL层108之上的金属1(M1)层。第一互连件136(1)和第二互连件136(2)在互连层132中形成在第一和第二VO 130(1)、130(2)之上并与之接触。例如，第一和第二互连件136(1)、136(2)可以是金属线138(1)、138(2)，金属线138(1)、138(2)由设置在电介质材料141中形成的沟槽中的导电材料制成。通过该方式，在该示例中通过金属线138(1)、138(2)提供了与MOL屏蔽栅极104的连接性。
因此，通过在IC 102的MOL层108中制造金属电阻器106，可以将金属电阻器106有利地定位在有源半导体层112中，并且非常靠近有源半导体层112中的半导体器件，以有效地减小栅极到漏极寄生电容。例如，MOL层108可以具有大约十八(18)纳米(nm)或更小的厚度T，厚度T与半导体层112的厚度可以为大约0.26或更小的厚度比。此外，因为MOL层108已在IC 102中提供以在半导体层112中的半导体器件和互连层132之间提供触点(包括例如第一和第二半导体层触点150(1)、150(2))，因此可以不需要附加的面积来在IC 102中提供金属电阻器106。例如，金属电阻器106的宽度/长度(W/L)大约为0.21μm/0.21μm。
金属电阻器106可以由任何导电材料形成。作为示例，金属电阻器106可以由硅化钨(WSi)、氮化钛(TiN)和钨(W)形成。金属电阻器106应具有足够的电阻以对环境温度的变化敏感。例如，金属电阻器106的电阻可以是半导体器件的每W/Lμm至少400欧姆。此外，通过在MOL层108中设置金属电阻器106，从与FinFET 120的栅极(G)124邻近设置的功函数材料140相同的材料形成金属电阻器106的制造工艺观点来看可能是有效的。
图2是图示了制造在IC中的MOL屏蔽栅极(例如，图1中的IC 102中的MOL屏蔽栅极104)的示例性工艺200的流程图。图3A-图3F是在IC中制造MOL金属电阻器屏蔽栅极(例如，图1中的IC 102中包括金属电阻器106的MOL屏蔽栅极104)的示例性工艺阶段300(1)-300(6)。现在将描述图2中的示例性工艺200和用于制造图3A-图3F中的MOL 304的示例性工艺阶段300(1)-300(6)。
如图3A中的处理阶段300(1)所示，制造在IC 302中的MOL屏蔽栅极304的第一步骤是形成衬底316(图2中的框202)。如图3A所示，有源半导体层312被形成在衬底316之上(图2中的框204)。此外，如图3A所示，在有源半导体层312中形成至少一个半导体器件318(图2中的框206)。在该示例中，在有源半导体层312中形成PFET 319(1)和NFET 319(2)。如图所示，针对PFET 319(1)和NFET 319(2)形成了源极(S)、漏极(D)和栅极(G)。
接下来，在有源半导体层312之上形成MOL层308(图2中的框208)。在该示例中，中间MOL层308包括第一绝缘层342，其后是金属材料层344，其中另一第二绝缘层346设置在金属材料层344上。在该示例中，第一绝缘层342和第二绝缘层346是氧化物层。金属材料层344可以由将提供期望电阻的任何导电材料(例如，钨)形成。如前所述，金属材料层344可以由与用于在有源半导体层312中创建一个或多个栅极(G)的功函数材料相同的材料形成。第一绝缘层342被配置为将MOL层308与有源半导体层312和有源半导体层312中制造的半导体器件绝缘。金属材料层344将被处理来形成如将在下面更详细地讨论的金属电阻器。
接下来，如图3B中的第二工艺阶段300(2)所示，为了准备在MOL层308中形成的金属电阻器，将抗蚀剂层348设置在MOL层308(更具体地，第二绝缘层346)的顶部上。接下来，如图3C中的第三工艺阶段300(3)所示，将硬掩模350设置在抗蚀剂层348之上，以准备从金属材料层344形成金属电阻器。基于期望的金属电阻器的尺寸来调整硬掩模350的尺寸。可以放置硬掩模350，使得金属电阻器由有源半导体层312中的半导体器件之上和/或附近的金属材料层344形成，以有效地减小栅极到漏极寄生电容。然后通过暴露于光来处理IC302。如图3E的工艺阶段300(5)所示，除了在图3C的工艺阶段300(3)中设置硬掩模350的区域下方，去除抗蚀剂层348、第二绝缘层346和金属材料层344。在曝光抗蚀剂层348之后，去除不在硬掩模350下方的第二绝缘层346和金属材料层344。形成金属电阻器306的剩余金属材料层344具有触点区域328(1)和328(2)，以提供与作为MOL屏蔽栅极304的一部分的连至金属电阻器的电接触。例如，可以通过化学蚀刻工艺或其他去除工艺来去除第二绝缘层346。可以通过不同的化学蚀刻工艺或其他去除工艺来去除金属材料层344。
接下来，如图3F中的工艺阶段300(6)所示，可以是氧化物层的另一绝缘层352被设置在剩余的第一绝缘层342、金属电阻器306和第二绝缘层342之上，以制备在MOL层308中待形成的触点。在后续的处理步骤中，为了继续制造MOL屏蔽栅极304，形成连至在MOL层308中的金属电阻器306的第一触点，并且第一触点与第一触点区域328接触(图2中的框210)。在MOL层308之上形成至少一个互连层(图2中的框212)。在电耦合到第一触点的至少一个互连层中形成第一互连件，以将第一互连件电耦合到金属电阻器的第一触点区域328(图2中的框214)。可以在MOL层308之上的互连层中形成过孔，以与MOL层308和有源半导体层312中的触点电耦合。
根据本文所公开的任一示例的集成电路(IC)中的MOL屏蔽栅极可以被提供在任何基于处理器的设备中或集成到任何基于处理器的设备中。示例包括但不限于机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、智能电话、平板电脑、平板手机、计算机、便携式计算机、台式计算机、个人数字助理(PDA)、监视器、计算机监视器、电视、调谐器、收音机、卫星收音机、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器、便携式数字视频播放器和汽车。
在这方面，图4图示了包括CPU 402的基于处理器的系统400的一个示例，基于处理器的系统400包括一个或多个处理器404。基于处理器的系统400可以被提供为片上系统(SoC)406。CPU 402可以具有耦合到(多个)处理器404的高速缓存存储器408，用于快速访问临时存储的数据。CPU 402可以包括MOL屏蔽栅极104。CPU 402耦合到系统总线410并且可以耦合到基于处理器的系统400中包括的其他设备。CPU 402中的(多个)处理器404可以通过系统总线410交换地址、控制和数据信息来与这些其他设备通信。尽管未在图4中进行图示，但可以提供多个系统总线410，其中每个系统总线410构成不同的结构。例如，CPU 402可以将总线事务请求通信到存储器系统414中的存储器(作为从属设备的示例)。
其他设备可以连接到系统总线410。如图4所示，这些设备可以包括例如存储器系统414、一个或多个输入设备418、一个或多个输出设备420、一个或多个网络接口设备422以及一个或多个显示控制器424。(多个)输入设备418可以包括任何类型的输入设备，包括但不限于输入键、开关、语音处理器等。(多个)输出设备420可以包括任何类型的输出设备，包括但不限于音频、视频、其他视觉指示器等。(多个)网络接口设备422可以是配置为允许与网络426进行数据交换或从网络426交换数据的任何设备。网络426可以是任何类型的网络，包括但不限于有线或无线网络、专用或公共网络、局域网(LAN)、无线局域网(WLAN)、广域网(WAN)、BLUETOOTHTM网络和互联网。(多个)网络接口设备422可以被配置为支持期望的任何类型的通信协议。
CPU 402还可被配置为通过系统总线410来访问(多个)显示控制器424，以控制发送到一个或多个显示器428的信息。(多个)显示器428可以包括任何类型的显示器，包括但不限于：阴极射线管(CRT)、液晶显示器(LCD)、等离子显示器等。(多个)显示控制器424将信息发送到(多个)显示器428，以经由一个或多个视频处理器430进行显示，一个或多个视频处理器430将信息处理为适合(多个)显示器428进行显示的格式。
图5图示了无线通信设备500的示例，无线通信设备500可以包括RF组件，在RF组件中，MOL屏蔽栅极104可以在集成电路(IC)506中使用，以减小栅极到漏极寄生电容。为此，无线通信设备500被提供在IC 506中。无线通信设备500可以包括或被提供在任何上述参考的设备(例如，智能电话)中。如图5所示，无线通信设备500包括收发器504和数据处理器508。IC 506和/或数据处理器508可以包括MOL屏蔽栅极104来减小栅极到漏极寄生电容。数据处理器508可以包括存储器(未示出)来存储数据和程序代码。收发器504包括支持双向通信的发射器510和接收器512。通常，无线通信设备500可以包括用于任意数量的通信系统和频带的任意数量的发射器和/或接收器。收发器504的全部或一部分可以在一个或多个模拟IC、RF IC(RFIC)、混合信号IC等上实现。
可以利用超外差架构或直接转换架构来实现发射器或接收器。在超外差架构中，信号在多级中在RF和基带之间进行频率转换(例如，对于接收器，在一级中从RF到中频(IF)，然后在另一级中从IF到基带)。在直接转换架构中，信号在一级中在RF和基带之间进行频率转换。超外差和直接转换架构可以使用不同的电路块和/或具有不同的要求。在图5的无线通信设备500中，发射器510和接收器512利用直接转换架构实现。
在发射路径中，数据处理器508对待发射的数据进行处理，并将I模拟输出信号和Q模拟输出信号提供给发射器510。在示例性无线通信设备500中，数据处理器508包括数模转换器(DAC)514(1)和514(2)，用于将由数据处理器508生成的数字信号转换为I模拟输出信号和Q模拟输出信号(例如，I和Q输出电流)，以进行进一步处理。
在发射器510内，低通滤波器516(1)、516(2)分别对I拟输出信号和Q模拟输出信号进行滤波，以去除由先前的数模转换引起的不期望图像。放大器(AMP)518(1)、518(2)将来自低通滤波器516(1)、516(2)的信号分别放大，并提供I基带信号和Q基带信号。上变频器520借助来自TX LO信号发生器522的混频器524(1)、524(2)，利用I和Q发射(TX)本机振荡器(LO)信号对I基带信号和Q基带信号进行上变频来提供上变频信号526。滤波器528对上变频信号进行滤波，来去除由频率上变频引起的不期望图像以及接收频带中的噪声。功率放大器(PA)530将来自滤波器528的上变频信号放大来获得期望的输出功率电平并提供发射RF信号。发射RF信号借助双工器或开关532进行路由，并经由天线534发射。
在接收路径中，天线534接收由基站发射的信号并提供所接收的RF信号，RF信号借助双工器或开关532路由并提供给低噪声放大器(LNA)536。双工器或开关532被设计用于利用特定的RX至TX双工器频率间隔操作，使得RX信号与TX信号隔离。所接收的RF信号被LNA536放大并且被滤波器538滤波来获得期望的RF输入信号。下变频混频器540(1)、下变频混频器540(2)将滤波器538的输出与来自RX LO信号发生器542的I接收(RX)LO信号和Q接收(RX)LO信号(即，LO_I和LO_Q)混合来生成I和Q基带信号。I基带信号和Q基带信号由放大器(AMP)544(1)、544(2)放大并由低通滤波器546(1)、546(2)进一步滤波，以获得I模拟输入信号和Q模拟输入信号，I模拟输入信号和Q模拟输入信号被提供给数据处理器508。在该示例中，数据处理器508包括模数转换器(ADC)548(1)、548(2)，以将模拟输入信号转换为数字信号而由数据处理器508进一步处理。
在图5的无线通信设备500中，TX LO信号发生器522生成用于频率上变频的I TXLO信号和Q TX LO信号，而RX LO信号发生器542生成用于频率下变频的I RX LO信号和Q RXLO信号。每个LO信号都是具有特定基频的周期性信号。发射(TX)锁相环(PLL)电路550从数据处理器508接收定时信息，并生成用于调整来自TX LO信号发生器522的TX LO信号的频率和/或相位的控制信号。类似地，接收(RX)锁相环(PLL)电路552从数据处理器508接收定时信息，并生成用于调整来自RX LO信号发生器542的RX LO信号的频率和/或相位的控制信号。
本领域技术人员将进一步理解，结合本文所公开的各方面描述的各种例示性的逻辑块、模块、电路和算法可以被实现为电子硬件、存储器中或另一计算机可读介质中存储并由处理器或其他处理设备执行的指令或两者的组合。作为示例，本文描述的设备可以在任何电路、硬件组件、集成电路(IC)或IC芯片中采用。本文所公开的存储器可以是任何类型和容量的存储器，并且可以被配置为存储期望的任何类型的信息。为了清楚地图示该可互换性，上文已整体上根据其功能描述了各种例示性的组件、块、模块、电路和步骤。
还应注意，描述了本文的任何示例性方面中描述的操作步骤来提供示例和讨论。所描述的操作可以以除了图示的顺序之外的许多不同的顺序执行。此外，在单个操作步骤中描述的操作实际上可以在许多不同的步骤中执行。附加地，可以将示例性方面中讨论的一个或多个操作步骤进行组合。应当理解，对于本领域技术人员显而易见的是，流程图中所示的操作步骤可以进行许多不同的修改。
提供本公开的先前描述以使本领域的任何技术人员能够制造或使用本公开。对本公开的各种修改对于本领域技术人员将是显而易见的，并且在不脱离本公开的精神或范围的情况下，本文中定义的一般原理可以应用于其他变型。因此，本公开内容不旨在限于本文描述的示例和设计，而是与符合本文公开的原理和新颖性特征的最宽范围相一致。

Claims (22)

1.一种用于集成电路(IC)的线中(MOL)被屏蔽的栅极，包括：
有源半导体层，包括第一半导体器件；
金属电阻器，被设置在MOL层中，所述MOL层被设置在所述有源半导体层上方；
其中所述第一半导体器件包括晶体管，所述晶体管包括源极、漏极和被设置在所述源极和所述漏极之间的栅极；并且
其中所述金属电阻器被设置在所述晶体管的所述栅极之上。
2.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，还包括：
触点，被设置在所述MOL层中的所述金属电阻器上方，所述触点电耦合至所述金属电阻器的触点区域；以及
互连件，被设置在所述MOL层上方的互连层中，所述互连层电耦合至所述触点，以将所述互连件电耦合至所述金属电阻器的所述触点区域。
3.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，其中所述MOL层具有大约十八(18)纳米(nm)或更小的厚度。
4.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，其中所述金属电阻器被定位在所述MOL层中位于所述第一半导体器件的大约七(7)纳米(nm)内。
5.根据权利要求2所述的用于所述IC的所述MOL被屏蔽的栅极，其中所述互连件包括金属线。
6.根据权利要求2所述的用于所述IC的所述MOL被屏蔽的栅极，还包括：
垂直互连通路(过孔)，被设置在所述互连层中，所述过孔与所述金属电阻器的所述触点区域和所述互连件接触，以将所述触点区域电耦合到所述互连件。
7.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，其中所述第一金属材料包括钨。
8.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，其中所述金属电阻器的尺寸为大约0.21μm/0.21μm的W/L。
9.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，其中所述金属电阻器的电阻为每1.0μm/1.0μm的W/L比至少400欧姆。
10.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，被集成到片上系统(SoC)中。
11.根据权利要求1所述的用于所述IC的所述MOL被屏蔽的栅极，被集成到选自由以下项组成的组的设备中：机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、智能电话、平板电脑、平板手机、计算机、便携式计算机、台式计算机、个人数字助理(PDA)、监视器、计算机监视器、电视、调谐器、收音机、卫星收音机、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器、便携式数字视频播放器和汽车。
12.一种用于集成电路(IC)的线中(MOL)被屏蔽的栅极，包括：
用于形成包括第一半导体器件的有源半导体层的部件；以及
用于在用于提供所述有源半导体的部件上方形成包括金属电阻器的MOL层的部件，其中所述第一半导体器件包括晶体管，所述晶体管包括源极、漏极和被设置在所述源极和所述漏极之间的栅极，并且其中所述金属电阻器被设置在所述晶体管的所述栅极之上。
13.一种在用于集成电路(IC)的半导体管芯中制造被屏蔽的栅极的方法，包括：
形成衬底；
在所述衬底上方形成有源半导体层；
在所述有源半导体层中形成至少一个半导体器件；以及
在所述有源半导体层上方形成线中(MOL)层，包括：
在所述MOL层中形成具有电阻并包括第一金属材料的金属电阻器，所述金属电阻器包括触点区域；
其中在所述有源半导体层中形成所述至少一个半导体器件包括形成晶体管，所述晶体管包括源极、漏极和被设置在所述源极和所述漏极之间的栅极；并且
其中形成所述金属电阻器包括：在所述MOL层中邻近所述晶体管的所述栅极地形成包括所述第一金属材料的所述金属电阻器，来减小栅极到漏极寄生电容。
14.根据权利要求13所述的方法，其中形成所述MOL层包括：在所述有源半导体层上方形成厚度大约为十八(18)纳米(nm)或更小的所述MOL层。
15.根据权利要求13所述的方法，还包括：
形成触点，所述触点在所述MOL层中的所述金属电阻器上方并且与所述金属电阻器的所述触点区域接触；
在所述MOL层上方形成至少一个互连层；以及
在电耦合到所述触点的所述至少一个互连层中形成互连件，以将所述互连件电耦合到所述金属电阻器的所述触点区域。
16.根据权利要求14所述的方法，还包括：
在所述互连件中形成垂直互连通路(过孔)，所述过孔与所述金属电阻器的所述触点区域和所述互连件接触，以将所述触点区域电耦合到所述互连件。
17.根据权利要求13所述的方法，其中在所述有源半导体层上方形成所述MOL层还包括：
在所述有源半导体层上方形成包括第一电介质材料的第一电介质层；
在所述第一电介质层上方形成包括所述第一金属材料的金属层；
在所述金属层上方形成包括第二电介质材料的第二电介质层；
在所述第二电介质层的第一部分上方设置硬掩模；以及
去除所述第一部分之外的所述第二电介质层和所述金属层的第二部分，直到所述第一电介质层，以在所述硬掩模下方留下所述金属层的其余部分和所述第二电介质层的其余部分，所述其余部分形成具有所述电阻的所述金属电阻器。
18.根据权利要求13所述的方法，其中在所述MOL层中形成所述金属电阻器大约在所述第一半导体器件的七(7)纳米(nm)内。
19.根据权利要求15所述的方法，其中所述互连件包括金属线。
20.根据权利要求13所述的方法，其中所述第一金属材料包括钨。
21.根据权利要求13所述的方法，其中所述金属电阻器的尺寸为大约0.21μm/0.21μm的W/L。
22.根据权利要求13所述的方法，其中所述金属电阻器的所述电阻为：每1.0μm/1.0μm的W/L比为至少400欧姆。
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