CN111180597A - Top-emission vertical light-emitting transistor and preparation method and application thereof - Google Patents
Top-emission vertical light-emitting transistor and preparation method and application thereof Download PDFInfo
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Abstract
The invention relates to a top-emission vertical light-emitting transistor and a preparation method and application thereof, wherein the top-emission vertical light-emitting transistor comprises a substrate, a gate electrode, an anti-reflection insulating layer, a source electrode, an organic functional layer and a drain electrode which are sequentially stacked; the anti-reflection insulating layer comprises a plurality of layers of reflecting films, and the refractive indexes of any two adjacent layers of the reflecting films are different. The light emitting efficiency of the top-reflection vertical light emitting transistor can be enhanced without using a high-reflection electrode.
Description
Technical Field
The invention relates to the technical field of light-emitting electronic devices, in particular to a top-emitting vertical light-emitting transistor and a preparation method and application thereof.
Background
In order to obtain a highly integrated device structure, it has been studied to integrate Thin Film Transistor (TFT) and Organic Light-Emitting Diode (OLED) devices into a single optoelectronic device to form Organic Light-Emitting transistors (OLEDs), which use the gate field of Field Effect Transistors (FETs) to control the injection degree of carriers to improve the Light-Emitting efficiency and intensity of Light emission of the Light-Emitting device. The top emission vertical light-emitting transistor emits light from the top of the device without being affected by whether the substrate is transparent or not, so that the aperture opening ratio of the display panel can be improved, the spectrum can be narrowed, the color purity can be improved, and the top emission vertical light-emitting transistor is more and more favored. At present, in order to enhance the light extraction efficiency of a top-emission vertical light-emitting transistor, a traditional method is to design a metal with high reflectivity as a gate electrode, that is, a metal with high reflectivity such as Al, Ag, and the like is used as the gate electrode, but the work function of the metal is low and is limited by the problem of matching with the highest molecular occupied track energy level of a light-emitting layer, which seriously affects the light-emitting efficiency of a display device.
Disclosure of Invention
Accordingly, there is a need for a top-emission vertical light emitting transistor with improved light emitting efficiency without affecting light emitting efficiency, and a method for manufacturing the same and an application thereof.
A top emission vertical light-emitting transistor comprises a substrate, a gate electrode, an anti-reflection insulating layer, a source electrode, an organic functional layer and a drain electrode which are sequentially stacked; the reflection-increasing insulating layer comprises a plurality of layers of reflection films, and the refractive indexes of any two adjacent layers of the reflection films are different.
In one embodiment, the multilayer reflective film includes first reflective films and second reflective films alternately arranged, and the refractive index of the first reflective films is smaller than that of the second reflective films.
In one embodiment, when the refractive index of the reflective film in contact with the gate electrode is less than 1.8, the reflective film in contact with the gate electrode is a first reflective film;
when the refractive index of the reflective film in contact with the gate electrode is greater than 1.8, the reflective film in contact with the gate electrode is a second reflective film.
In one embodiment, the refractive index of the first reflecting film is 1.3-1.8, and the thickness of the first reflecting film is 60nm-150 nm; and/or
The refractive index of the second reflecting film is 2-2.6, and the thickness of the second reflecting film is 40nm-100 nm.
In one embodiment, the first material forming the first reflective film is Al2O3And SiO2One or more of; and/or
The second material forming the second reflective film is ZrO2And TiO2One or more of (a).
In one embodiment, the number of the multilayer reflective film layers is 2-14.
In one embodiment, the top-emission vertical light emitting transistor is a forward structure light emitting transistor or an inverted structure light emitting transistor.
A preparation method of a top-emitting vertical light-emitting transistor comprises the following steps:
forming a gate electrode on a substrate;
forming an anti-reflection increasing insulating layer on the gate electrode;
forming a source electrode on the anti-reflection insulating layer;
forming an organic functional layer on the source electrode;
forming a drain electrode on the organic functional layer;
the reflection increasing insulating layer comprises a plurality of reflection films, and the refractive indexes of any two adjacent reflection films are different.
In one embodiment, the step of forming an enhanced insulating layer on the gate electrode includes the steps of:
depositing a first material on the gate electrode to form a first reflective film;
depositing a second material on the first reflective film to form a second reflective film;
repeating the steps of forming the first reflective film and forming the second reflective film until n layers of the first reflective film are formed, wherein the refractive index of the first reflective film is less than that of the second reflective film, and n is an integer greater than or equal to 1; alternatively, the first and second electrodes may be,
depositing a second material on the gate electrode to form a second reflective film;
depositing a first material on the second reflective film to form a first reflective film;
repeating the steps of forming the second reflective film and forming the first reflective film until m layers of second reflective films are formed, wherein the refractive index of the first reflective film is less than that of the second reflective film, and m is an integer greater than or equal to 1.
An electronic device comprising the above top-emitting vertical light-emitting transistor or the top-emitting vertical light-emitting transistor prepared by the above preparation method.
The top reflection vertical light-emitting transistor improves the insulating layer between the traditional gate electrode and the source electrode into the reflection increasing insulating layer, the reflection increasing insulating layer comprises the adjacent two layers of multilayer reflecting films with different refractive indexes, the light loss caused by the transmission of light rays through the insulating layer and the gate electrode can be reduced by utilizing the difference of the adjacent two layers of refractive indexes, the reflection increasing insulating layer with high reflectivity is formed, and the reflection increasing insulating layer interacts with other layers, so that the top reflection vertical light-emitting transistor does not need to use a high reflection electrode, the problem that the highest molecular occupation track energy level of the high reflection electrode and the light-emitting layer is limited to cause the influence on the light-emitting efficiency can be avoided, and the light-emitting efficiency can be improved on the basis of not. And the increased anti-reflection insulating layer has the functions of a gate insulating layer and a reflection layer of a transistor, so that the working voltage of a light-emitting device using the top-reflection vertical light-emitting transistor can be reduced, and the power consumption can be reduced.
Drawings
FIG. 1 is a schematic diagram of a top-emitting vertical light emitting transistor according to an embodiment;
FIG. 2 is a schematic structural diagram of an enhanced insulating layer according to an embodiment;
FIG. 3 is a diagram of a reflection path of a dual anti-reflection insulating layer according to an embodiment.
Detailed Description
In order that the invention may be more fully understood, a more particular description of the invention will now be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, a top emission vertical light emitting transistor 10 according to an embodiment of the present invention includes: the organic light emitting diode comprises a substrate 101, a gate electrode 201, an anti-reflection insulating layer 301, a source electrode 401, an organic functional layer 501 and a drain electrode 601. The substrate 101, the gate electrode 201, the anti-reflection layer 301, and the source electrode 401 constitute a capacitor unit, and the source electrode 401, the organic functional layer 501, and the drain electrode 601 constitute a light-emitting unit. That is, the capacitor unit and the light emitting unit are connected in the vertical direction with the source electrode 401 as a common electrode, constituting a single integrated top emission vertical light emitting transistor 10.
The antireflection insulating layer 301 includes a plurality of reflective films, and the refractive indices of any two adjacent reflective films are different. As shown in fig. 2, the multilayer reflective film includes first and second reflective films 3011 and 3012 that are repeatedly and alternately arranged, and the refractive index of the first reflective film 3011 is smaller than the refractive index of the second reflective film 3012. Therefore, by using the plurality of insulating layer films with high refractive index and low refractive index alternately, the optical loss caused by the transmission of light through the insulating layer and the grid electrode can be reduced, and the anti-reflection insulating layer with high reflectivity is formed to enhance the light emitting efficiency of the top emission vertical light emitting transistor.
The reflective film of the anti-reflection increasing insulating layer in contact with the gate electrode may be a first reflective film having a low refractive index or a second reflective film having a high refractive index, and is not particularly limited herein. In one embodiment, when the refractive index of the reflective film in contact with the gate electrode is less than 1.8, the reflective film in contact with the gate electrode is the first reflective film, that is, the reflective film in contact with the gate electrode of the anti-reflection insulating layer is the first reflective film having a refractive index of less than 1.8; when the refractive index of the reflective film in contact with the gate electrode is greater than 1.8, the reflective film in contact with the gate electrode is the second reflective film, that is, the reflective film in contact with the gate electrode of the anti-reflection insulating layer is the second reflective film having a refractive index greater than 1.8.
The number of the reflection films of the anti-reflection increasing insulating layer 301 is increased, and the reflectivity is increased, and the number of the reflection films is preferably 2 to 14, more preferably 4 to 12, so as to ensure that the anti-reflection increasing insulating layer has stronger reflectivity.
The first material of the first reflective films may be the same or different. Also, the second material of the plurality of second reflective films may be the same or different, and is not particularly limited herein.
In one embodiment, the second reflective film is made of an inorganic insulating material, preferably ZrO2、TiO2And the like. In another embodiment, the first reflective film is made of an inorganic insulating material, preferably Al2O3、SiO2And the like. The corresponding reflective film may be prepared by a solution method or a vacuum method.
In addition, since light is incident from the optically dense medium to the optically sparse medium, the reflected light does not have a phase jump, but when light is incident from the optically sparse medium to the interface of the optically dense medium and is reflected, the reflected light has a phase jump of pi, that is, a half-wave loss is generated. When two beams of reflected light are present, one beam is reflected from the optically sparse to optically dense interface and the other beam is reflected from the optically dense to optically sparse interface (i.e., n)1<n>n2Or n1>n<n2) And the two reflected light beams have an additional phase difference pi, namely an additional optical path difference lambda/2. At this time, when the thickness of the dielectric film satisfies 1/4 of the optical length of the incident light, the optical path difference δ satisfies the formula:
δ＝2nd+λ/2＝±kλ
that is, the minimum value of the dielectric film thickness is:
d＝λ/4n。
therefore, the thickness of the film needs to be selected according to the refractive index of the selected material, so that two reflected lights reflected by the upper and lower surfaces of the film are superposed to form interference which is long, and the reflected lights are enhanced. That is, the thickness of the reflective film formed of the low refractive index material and the high refractive index material is 1/4 of the optical length of the light emission color of the organic light emitting layer.
In one embodiment, the thickness d of each reflective film in the multilayer reflective film is (λ/4n) ± 30 nm; in another embodiment, each of the plurality of reflective films has a thickness d ═ λ/4n ± 10 nm; in one embodiment, each of the reflective films has a thickness d ═ λ/4n ± 5 nm. Where λ is the wavelength of light emitted from the light-emitting layer in the top-emission vertical light-emitting transistor, and n is the refractive index of the reflective film.
In one embodiment, the first reflective film has a refractive index of 1.3 to 1.8, and the second reflective film has a thickness of 60 to 150 nm. In another embodiment, the second reflective film has a refractive index of 2 to 2.6 and a thickness of 40 to 100 nm.
Further, in the present embodiment, the base plate 101 includes a glass base plate, a silicon wafer substrate, and a flexible substrate.
Further, in the present embodiment, the gate electrode 201 may be an ITO electrode, or may be an electrode made of other metal materials or other metal oxide electrodes.
Further, in the present embodiment, the source electrode 401 is a Carbon Nanotube (CNTs), a nano silver wire, or a metal mesh. The carbon nanotubes and the silver nanowires can be prepared by a solution spin coating method, the metal grid can be prepared by ink-jet printing of metal ink (Au, Ag and the like), and the shape of the metal grid can be in a grid shape, a strip shape and the like.
Further, in the present embodiment, the top emission vertical light emitting transistor is a forward structure light emitting transistor or an inverted structure light emitting transistor, and the stacking order of the layers in the organic functional layer 501 is selected according to the structure of the light emitting transistor. In one embodiment, as shown in fig. 1, the top emission vertical light emitting transistor is a forward structure light emitting transistor, i.e., the organic functional layer 501 includes a hole injection layer 5011, a hole transport layer 5012, a light emitting layer 5013, an electron transport layer 5014, and an electron injection layer 5015, which are sequentially stacked, and the hole injection layer 5011 is adjacent to the source electrode 401. In another embodiment, the top-emission vertical light-emitting transistor is an inverted structure, i.e., the organic functional layer includes an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer, which are sequentially stacked, wherein the electron transport layer is adjacent to the source electrode. In addition, the light emitting layer in the organic functional layer may be an organic light emitting material or a quantum dot light emitting material.
Further, in the present embodiment, the drain electrode 601 is a transparent oxide conductive film, an ultra-thin translucent metal film, or an ultra-thin translucent alloy film, specifically including but not limited to ITO, ZnO, IZO, Al, MgAg alloy, or the like. Wherein the thickness of the transparent oxide conductive film is 40-100 nm. The thickness of the ultra-thin semitransparent metal film or the ultra-thin semitransparent alloy film is 15-30 nm.
A preparation method of a top-emitting vertical light-emitting transistor comprises the following steps:
s101: a gate electrode is formed on a substrate.
The substrate may be cleaned first, and then a metal electrode is prepared on the substrate as a gate electrode by using a vacuum evaporation or magnetron sputtering method. In one embodiment, the step of forming the gate electrode on the substrate includes the steps of:
(1) ultrasonic cleaning the glass substrate with acetone, ethanol and deionized water for 5-10min respectively, blowing with nitrogen, baking in hot plate or oven for 10-20min, and performing UV/O on the surface of the glass substrate3Or oxygen plasma (O)2Plasma) for 5-10 min.
(2) And preparing patterned ITO (indium tin oxide) serving as a gate electrode on the substrate by using a mask plate and adopting a magnetron sputtering method.
S102: an anti-reflection insulating layer is formed on the gate electrode.
The anti-reflection insulating layer can be deposited and prepared on the substrate with the prepared gate electrode by utilizing a vacuum process or a solution spin coating process.
In one embodiment, the step of forming an enhanced insulating layer on the gate electrode includes the steps of:
S1021A: depositing a first material on the gate electrode to form a first reflective film;
wherein the first material is not particularly limited and may be, for example, Al2O3、SiO2And the like.
In one embodiment, the first material is Al2O3Specifically, on the substrate of the prepared ITO electrode, the low-refractive-index Al is prepared by using a solution method spin coating process2O3Oxide insulating layer, deviceThe method comprises the following steps:
(a) weighing a certain amount of aluminum nitrate hydrate, dissolving in dimethoxyethanol organic solvent, and preparing Al with the concentration of 0.2-0.8M2O3And (3) stirring the solution precursor at high speed for 2-4h at room temperature, standing and aging for use.
(b) After spin coating a film on a glass substrate by a spin coating method (3000rpm/30s) in air, the glass substrate is placed on a hot plate at 150 ℃ and heated and baked for 15min with the assistance of water vapor, so that the formation of metal-oxygen bonds between reactants is promoted.
(c) Repeating the step (b) for a plurality of times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form Al2O3And an insulating layer, wherein the annealing environment is air or nitrogen.
S1022A: depositing a second material on the first reflective film to form a second reflective film;
wherein the second material has a refractive index greater than that of the first material, which may be, for example, ZrO2、TiO2And the like, and are not particularly limited herein.
In one embodiment, the first material is Al2O3The second material is ZrO2. Specifically, a solution spin coating process is utilized to coat Al with low refractive index2O3Preparing a high-refractive-index ZrO2 oxide insulating layer on the oxide insulating layer, comprising the following steps of:
(a) weighing a certain amount of zirconium acetylacetonate, dissolving in DMF organic solvent, and preparing ZrO with concentration of 0.1-0.5M2And (3) stirring the solution precursor at high speed for 2-8h at room temperature, standing and aging for use.
(b) In air, Al was coated by spin coating (4000rpm/30s)2O3After spin coating to form a film on the oxide insulating layer, the film is placed on a hot plate at 150 ℃ and the organic solvent is removed.
(c) Repeating the step (b) for a plurality of times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form ZrO2And an insulating layer, wherein the annealing environment is air or nitrogen.
S1023A: repeating the steps of forming the first reflective film and forming the second reflective film until n layers of the first reflective film are formed, wherein the refractive index of the first reflective film is less than that of the second reflective film, and n is an integer greater than or equal to 1. Preferably, the refractive index of the first reflective film is less than 1.8.
In another embodiment, the step of forming an enhanced insulating layer on the gate electrode includes the steps of:
S1021B: depositing a second material on the gate electrode to form a second reflective film;
wherein the second material is not particularly limited and may be, for example, ZrO2、TiO2And the like. In one embodiment, the second material is ZrO2Specifically, ZrO is prepared on the substrate of the prepared ITO electrode by a solution method spin coating process2The oxide insulating layer specifically includes the steps of:
(a) weighing a certain amount of zirconium acetylacetonate, dissolving in DMF organic solvent, and preparing ZrO with concentration of 0.1-0.5M2And (3) stirring the solution precursor at high speed for 2-8h at room temperature, standing and aging for use.
(b) After spin coating was performed on a glass substrate in the air by the spin coating method (4000rpm/30s), the substrate was placed on a hot plate at 150 ℃ to remove the organic solvent.
(c) Repeating the step (b) for a plurality of times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form ZrO2And an oxide insulating layer, wherein the annealing environment is air or nitrogen.
S1022B: depositing a first material on the second reflective film to form a first reflective film;
wherein the first material is not particularly limited, the refractive index of the first material is smaller than that of the second material, and may be, for example, Al2O3、SiO2And the like.
In one embodiment, the second material is ZrO2The first material is Al2O3. Specifically, the solution method is utilized to spin-coat ZrO2Preparation of Al on oxide insulating layer2O3An insulating layer comprising the steps of:
(a) weighing machineDissolving a certain amount of aluminum nitrate hydrate in dimethoxy ethanol organic solvent to prepare Al with the concentration of 0.2-0.8M2O3And (3) stirring the solution precursor at high speed for 2-4h at room temperature, standing and aging for use.
(b) In air, the ZrO was coated by spin coating (3000rpm/30s)2Spin coating on the oxide insulating layer to form a film, placing on a hot plate at 150 deg.C, heating with water vapor for 15min to promote the formation of metal-oxygen bond between reactants.
(c) Repeating the step (b) for a plurality of times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form Al2O3And an insulating layer, wherein the annealing environment is air or nitrogen.
S1023B: repeating the steps of forming the second reflective film and forming the first reflective film until m layers of the second reflective film are formed, wherein the refractive index of the first reflective film is less than that of the second reflective film, and m is an integer greater than or equal to 1. Preferably, the refractive index of the second reflective film is greater than 1.8.
S103: and forming a source electrode on the anti-reflection insulating layer.
The carbon nano tube or the nano silver wire can be prepared on the insulating layer as the source electrode by a solution spin coating method, or any metal grid such as a grid shape or a strip shape is printed on the insulating layer by a method of ink jet printing metal ink, and the conductive metal grid is obtained by high-temperature sintering and is used as the source electrode.
In one embodiment, a metallic silver grid is prepared on the anti-reflection insulating layer by an ink-jet printing method to be used as a source electrode, and a finished capacitor unit is prepared, wherein the method comprises the following steps:
(1) the shape of the inkjet printed metal mesh, i.e. the inkjet printed pattern design, is designed and input.
(2) And adjusting the printing output voltage and frequency of the ink-jet printing equipment, and adjusting the printing speed to be 0.5-20mm/s, thereby realizing the printing of the metal grid lines with different line widths.
(3) After the ink-jet printing pattern is formed, the substrate is placed on a hot plate at 200 ℃ to sinter the silver ink, so that the conductivity of the metal grid is realized.
S104: an organic functional layer is formed on the source electrode.
The organic functional layer can be sequentially prepared on the substrate on which the source electrode is prepared by using an ink jet printing method or a thermal evaporation method. In one embodiment, the organic functional layer is formed by a thermal evaporation method, and specifically, the vacuum degree of evaporation is less than 5e-4pa, the evaporation rate is controlled to be 0.1-0.2 angstroms per second. In one embodiment, the organic functional layer comprises: the light-emitting diode comprises a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer, wherein the hole injection layer is close to the source electrode.
S105: a drain electrode is formed on the organic functional layer.
The oxide conductive film can be prepared by magnetron sputtering, or the metal film or the metal alloy film can be prepared by thermal evaporation method to be used as the drain electrode. In one embodiment, a thermal evaporation method is adopted to prepare an ultrathin Al film as a drain electrode, and the thickness of the ultrathin Al film is 40 nm.
The top-emitting vertical light-emitting transistor can enhance the light-emitting efficiency of the top-emitting vertical light-emitting transistor without a high-reflection metal electrode, and simultaneously realizes a highly integrated optoelectronic device with low power consumption, so that the top-emitting vertical light-emitting transistor is suitable for preparing electronic devices.
An electronic device comprising the above top-emitting vertical light emitting transistor. The electronic device may be any commonly used light emitting device, such as: the display panel, the display device, and the like are not particularly limited. More specifically as follows: cell phones, computers, tablets, etc. The structure and the position relationship of the top emission vertical light emitting transistor are the same as those described above, and are not described herein again.
The present invention will be described below with reference to specific embodiments.
Example 1:
top emission vertical light emitting transistor (multilayer reflective film of 2 layers constituting the anti-reflection increasing insulating layer)
The preparation method comprises the following steps:
(1) ultrasonic cleaning the glass substrate with acetone, ethanol and deionized water for 5-10min respectively, blowing with nitrogen, baking in hot plate or oven for 10-20min, and performing UV/O on the surface of the glass substrate3Or O2The Plasma treatment is carried out for 5-10 min.
(2) And preparing patterned ITO (indium tin oxide) serving as a gate electrode on the substrate by using a mask plate and adopting a magnetron sputtering method.
(3) Preparing low-refractive-index Al on a substrate with an ITO electrode by using a solution spin coating process2O3An oxide insulating layer comprising the steps of:
the method comprises the following steps: weighing a certain amount of aluminum nitrate hydrate, dissolving in dimethoxyethanol organic solvent, and preparing Al with the concentration of 0.2-0.8M2O3And (3) stirring the solution precursor at high speed for 2-4h at room temperature, standing and aging for use.
Step two: after spin coating a film on a glass substrate by a spin coating method (3000rpm/30s) in air, the glass substrate is placed on a hot plate at 150 ℃ and heated and baked for 15min with the assistance of water vapor, so that the formation of metal-oxygen bonds between reactants is promoted.
Step three: repeating the second step for multiple times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form Al2O3 The insulating layer 3011 is annealed in air or nitrogen.
(4) Spin coating process on low refractive index Al by solution method2O3Preparation of high refractive index ZrO on oxide insulating layer2An oxide insulating layer comprising the steps of:
the method comprises the following steps: weighing a certain amount of zirconium acetylacetonate, dissolving in DMF organic solvent, and preparing ZrO with concentration of 0.1-0.5M2And (3) stirring the solution precursor at high speed for 2-8h at room temperature, standing and aging for use.
Step two: al prepared in step (3) by spin coating method (4000rpm/30s) in air2O3After spin coating to form a film on the oxide insulating layer, the film is placed on a hot plate at 150 ℃ and the organic solvent is removed.
Step three: repeating the second step for multiple times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form ZrO2And the insulating layer 3012 is annealed in air or nitrogen.
(5) Preparing a metal silver grid on the insulating layer by using an ink-jet printing method to serve as a source electrode, and preparing a finished capacitor unit, wherein the method comprises the following steps:
the method comprises the following steps: the shape of the inkjet printed metal mesh, i.e. the inkjet printed pattern design, is designed and input.
Step two: and adjusting the printing output voltage and frequency of the ink-jet printing equipment, and adjusting the printing speed to be 0.5-20mm/s, thereby realizing the printing of the metal grid lines with different line widths.
Step three: after the ink-jet printing pattern is formed, the substrate is placed on a hot plate at 200 ℃ to sinter the silver ink, so that the conductivity of the metal grid is realized.
(6) On the prepared capacitor unit, a thermal evaporation method is utilized to sequentially prepare a hole injection layer, a hole transport layer, a luminescent layer, an electron transport layer, an electron injection layer and other functional layers, and the evaporation vacuum degree is less than 5e-4pa, the evaporation rate is controlled to be 0.1-0.2 angstroms per second.
(7) Finally, an ultra-thin Al thin film as a drain electrode with a thickness of 40nm was prepared by thermal evaporation to obtain the top-emission vertical luminescence transistor of example 1, wherein the reflection optical path of the anti-reflection insulating layer is shown in fig. 3.
Example 2
Top emission vertical light emitting transistor (multilayer reflecting film of increased reflection insulating layer 4 layers)
The preparation method comprises the following steps:
(1) ultrasonic cleaning the glass substrate with acetone, ethanol and deionized water for 5-10min respectively, blowing with nitrogen, baking in hot plate or oven for 10-20min, and performing UV/O on the surface of the glass substrate3Or O2The Plasma treatment is carried out for 5-10 min.
(2) And preparing patterned ITO (indium tin oxide) serving as a gate electrode on the substrate by using a mask plate and adopting a magnetron sputtering method.
(3) Preparing low-refractive-index Al on a substrate with an ITO electrode by using a solution spin coating process2O3An oxide insulating layer comprising the steps of:
the method comprises the following steps: weighing a certain amount of aluminum nitrate hydrate, dissolving in dimethoxyethanol organic solvent to obtain a solution with concentration of 0.2-0.8MAl2O3And (3) stirring the solution precursor at high speed for 2-4h at room temperature, standing and aging for use.
Step two: after spin coating a film on a glass substrate by a spin coating method (3000rpm/30s) in air, the glass substrate is placed on a hot plate at 150 ℃ and heated and baked for 15min with the assistance of water vapor, so that the formation of metal-oxygen bonds between reactants is promoted.
Step three: repeating the second step for multiple times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form Al2O3An insulating layer. The annealing environment is air or nitrogen.
(4) Spin coating process on low refractive index Al by solution method2O3Preparation of high refractive index ZrO on oxide insulating layer2An oxide insulating layer comprising the steps of:
the method comprises the following steps: weighing a certain amount of zirconium acetylacetonate, dissolving in DMF organic solvent, and preparing ZrO with concentration of 0.1-0.5M2And (3) stirring the solution precursor at high speed for 2-8h at room temperature, standing and aging for use.
Step two: al prepared in step (3) by spin coating method (4000rpm/30s) in air2O3After spin coating to form a film on the oxide insulating layer, the film is placed on a hot plate at 150 ℃ and the organic solvent is removed.
Step three: repeating the second step for multiple times, spin-coating to a proper thickness, and finally placing the sample on a hot plate at 400 ℃ for high-temperature annealing to form ZrO2An oxide insulating layer. The annealing environment is air or nitrogen.
(5) Solution spin coating process for high refractive index ZrO2Preparation of low-refractive-index Al on oxide insulating layer2O3And (4) oxidizing the insulating layer, and performing the specific steps in the step (3).
(6) Low refractive index Al at step (5) by solution spin coating2O3Preparation of high refractive index ZrO on oxide insulating layer2And (4) oxidizing the insulating layer, and performing the same steps as the step (4).
(7) Preparing a metal silver grid on the insulating layer by using an ink-jet printing method to serve as a source electrode, and preparing a finished capacitor unit, wherein the method comprises the following steps:
the method comprises the following steps: the shape of the inkjet printed metal mesh, i.e. the inkjet printed pattern design, is designed and input.
Step two: and adjusting the printing output voltage and frequency of the ink-jet printing equipment, and adjusting the printing speed to be 0.5-20mm/s, thereby realizing the printing of the metal grid lines with different line widths.
Step three: after the ink-jet printing pattern is formed, the substrate is placed on a hot plate at 200 ℃ to sinter the silver ink, so that the conductivity of the metal grid is realized.
(8) On the prepared capacitor unit, a thermal evaporation method is utilized to sequentially prepare a hole injection layer, a hole transport layer, a luminescent layer, an electron transport layer, an electron injection layer and other functional layers, and the evaporation vacuum degree is less than 5e-4pa, the evaporation rate is controlled to be 0.1-0.2 angstroms per second.
(9) Finally, an ultra-thin Al thin film as a drain electrode was prepared by thermal evaporation to a thickness of 40nm to obtain the top-emission vertical light-emitting transistor of example 2.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A top-emitting vertical light-emitting transistor is characterized by comprising a substrate, a gate electrode, an anti-reflection insulating layer, a source electrode, an organic functional layer and a drain electrode which are arranged in a stacked mode; the reflection-increasing insulating layer comprises a plurality of layers of reflection films, and the refractive indexes of any two adjacent layers of the reflection films are different.
2. The top-emitting vertical light emitting transistor according to claim 1, wherein the multilayer reflective film comprises a first reflective film and a second reflective film alternately arranged, and a refractive index of the first reflective film is smaller than a refractive index of the second reflective film.
3. The top-emitting vertical light emitting transistor according to claim 2, wherein when a refractive index of the reflective film in contact with the gate electrode is less than 1.8, the reflective film in contact with the gate electrode is a first reflective film;
when the refractive index of the reflective film in contact with the gate electrode is greater than 1.8, the reflective film in contact with the gate electrode is a second reflective film.
4. The top-emitting vertical emission transistor according to claim 3, wherein the refractive index of the first reflective film is 1.3 to 1.8, and the thickness of the first reflective film is 60nm to 150 nm; and/or
The refractive index of the second reflecting film is 2-2.6, and the thickness of the second reflecting film is 40nm-100 nm.
5. The top-emitting vertical emission transistor of claim 4, wherein the first material forming the first reflective film is Al2O3And SiO2One or more of; and/or
The second material forming the second reflective film is ZrO2And TiO2One or more of (a).
6. The top-emitting vertical emission transistor according to any one of claims 1 to 5, wherein the number of layers of the multilayer reflective film is 2 to 14.
7. The top-emitting vertical light emitting transistor according to any one of claims 1 to 5, wherein the top-emitting vertical light emitting transistor is a forward structure light emitting transistor or an inverted structure light emitting transistor.
8. A preparation method of a top-emitting vertical light-emitting transistor is characterized by comprising the following steps:
forming a gate electrode on a substrate;
forming an anti-reflection increasing insulating layer on the gate electrode;
forming a source electrode on the anti-reflection insulating layer;
forming an organic functional layer on the source electrode;
forming a drain electrode on the organic functional layer;
the reflection increasing insulating layer comprises a plurality of reflection films, and the refractive indexes of any two adjacent reflection films are different.
9. The method of claim 8, wherein the step of forming an anti-reflection layer on the gate electrode comprises the steps of:
depositing a first material on the gate electrode to form a first reflective film;
depositing a second material on the first reflective film to form a second reflective film;
repeating the steps of forming the first reflective film and forming the second reflective film until n layers of the first reflective film are formed, wherein the refractive index of the first reflective film is less than that of the second reflective film, and n is an integer greater than or equal to 1; alternatively, the first and second electrodes may be,
depositing a second material on the gate electrode to form a second reflective film;
depositing a first material on the second reflective film to form a first reflective film;
repeating the steps of forming the second reflective film and forming the first reflective film until m layers of second reflective films are formed, wherein the refractive index of the first reflective film is less than that of the second reflective film, and m is an integer greater than or equal to 1.
10. An electronic device comprising the top-emission vertical light-emitting transistor according to any one of claims 1 to 7 or the top-emission vertical light-emitting transistor produced by the production method according to claims 8 to 9.
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