CN111180492A - Array substrate, manufacturing method thereof and double-sided display device - Google Patents
Array substrate, manufacturing method thereof and double-sided display device Download PDFInfo
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- CN111180492A CN111180492A CN202010001844.3A CN202010001844A CN111180492A CN 111180492 A CN111180492 A CN 111180492A CN 202010001844 A CN202010001844 A CN 202010001844A CN 111180492 A CN111180492 A CN 111180492A
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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Abstract
The embodiment of the application provides an array substrate, a manufacturing method thereof and a double-sided display device. The array substrate comprises a plurality of first areas and a plurality of second areas, wherein the first areas comprise first driving thin film transistors and first light emitting units electrically connected with the first driving thin film transistors, and the second areas comprise second driving thin film transistors and second light emitting units electrically connected with the second driving thin film transistors; the first light-emitting unit is a top-emitting organic light-emitting diode, and the second light-emitting unit is a double-sided light-emitting organic light-emitting diode; the width-to-length ratio of the channel of the second driving thin film transistor is larger than that of the channel of the first driving thin film transistor. The embodiment can improve the problem of uneven brightness of the main display surface of the double-sided display device, and meanwhile, the display brightness of the auxiliary display surface is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a double-sided display device.
Background
With the development of display technology, there is an increasing demand for display devices, for example, double-sided display devices have become one of the development trends.
The existing double-sided display device is mostly composed of two display screens, the cost is higher, and the thickness of the display device is difficult to be thinned and is thicker and heavier.
Some OLED (organic light-Emitting Diode) display screens can realize double-sided display, so that the cost of the display device is reduced, the thickness of the display device is reduced, but the uniformity of the display brightness of the main light Emitting surface of the OLED double-sided display screen is poor.
Disclosure of Invention
The application aims at the defects of the existing mode and provides an array substrate, a manufacturing method thereof and a double-sided display device, double-sided display can be achieved, and the technical problem that the uniformity of the display brightness of the main display surface of a double-sided OLED display screen is poor in the prior art is solved.
In a first aspect, embodiments of the present application provide an array substrate including a plurality of first regions and a plurality of second regions, the first regions including a first driving thin film transistor and a first light emitting unit electrically connected to the first driving thin film transistor, the second regions including a second driving thin film transistor and a second light emitting unit electrically connected to the second driving thin film transistor;
the first light-emitting unit is a top-emitting organic light-emitting diode, and the second light-emitting unit is a double-sided light-emitting organic light-emitting diode;
the width-length ratio of the channel of the second driving thin film transistor is larger than that of the channel of the first driving thin film transistor.
Optionally, the array substrate includes:
the active layer comprises a plurality of first active islands positioned in the first area and a plurality of second active islands positioned in the second area, the material of the first active islands comprises warm polycrystalline silicon and/or indium gallium zinc oxide, and the material of the second active islands comprises warm polycrystalline silicon and/or indium gallium zinc oxide;
a gate layer on the active layer, including a plurality of first gates in the first region and a plurality of second gates in the second region;
the insulating layer covers the gate layer, and a plurality of first via holes penetrating through the insulating layer are formed in the insulating layer;
the source-drain electrode layer is positioned on the insulating layer and comprises a plurality of first source electrodes and a plurality of first drain electrodes which are positioned in the first area, and a plurality of second source electrodes and a plurality of second drain electrodes which are positioned in the second area, the first source electrodes and the first drain electrodes are respectively connected with the first active island through the corresponding first via holes, and the second source electrodes and the second drain electrodes are respectively connected with the second active island through the corresponding first via holes;
the first driving thin film transistor comprises a first active island, a first grid electrode, a first source electrode and a second drain electrode, and the second driving thin film transistor comprises a second active island, a second grid electrode, a second source electrode and a second drain electrode.
Optionally, the first light emitting unit includes a first anode, the material of the first anode includes a transparent conductive film layer and a reflective metal layer, the second light emitting unit includes a second anode, and the material of the second anode includes a transparent conductive film.
Optionally, the width-to-length ratio of the channel of the second driving thin film transistor is 5-20 times larger than the width-to-length ratio of the channel of the first driving thin film transistor.
Optionally, the channel width of the first driving thin film transistor is 3 micrometers, the length of the first driving thin film transistor is 30 micrometers, and the channel width of the second driving thin film transistor is 3 micrometers, and the length of the second driving thin film transistor is 3 micrometers; or
The channel width of the first driving thin film transistor is 2 micrometers, the length of the first driving thin film transistor is 20 micrometers, the channel width of the second driving thin film transistor is 4 micrometers, and the length of the second driving thin film transistor is 4 micrometers; or
The channel width of the first driving thin film transistor is 3 micrometers, the length of the first driving thin film transistor is 22.5 micrometers, and the channel width of the second driving thin film transistor is 2.5 micrometers, and the length of the second driving thin film transistor is 3 micrometers.
In a second aspect, the present application provides a dual-sided display device, which includes the array substrate.
In a second aspect, an embodiment of the present application provides a method for manufacturing an array substrate, where the method includes:
providing a substrate, wherein the substrate comprises a plurality of first areas and a plurality of second areas;
manufacturing a first driving thin film transistor in a first area of the substrate, manufacturing a second driving thin film transistor in a second area of the substrate, wherein the width-to-length ratio of the second driving thin film transistor is larger than that of the first driving thin film transistor;
manufacturing a first light-emitting unit in a first area of the substrate, and manufacturing a second light-emitting unit in a second area of the substrate, wherein the first light-emitting unit is a top-emission organic light-emitting diode, and the second light-emitting unit is a double-sided light-emitting organic light-emitting diode.
Optionally, the fabricating a first driving thin film transistor in a first region of the substrate, and fabricating a second driving thin film transistor in a second region of the substrate, where a width-to-length ratio of the second driving thin film transistor is greater than a width-to-length ratio of the first driving thin film transistor, includes:
forming an active layer on the substrate, and performing patterning processing on the active layer to form a plurality of first active islands located in the first region and a plurality of second active islands located in the second region;
forming a gate layer, and carrying out patterning processing on the gate layer to form a first gate positioned on the first active island and a second gate positioned on the second active island;
forming an insulating layer covering a gate layer, and performing patterning processing on the insulating layer to form a plurality of first via holes;
and forming a source drain electrode layer on the insulating layer, and performing graphical processing on the insulating layer to form a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes and a plurality of second drain electrodes, wherein the first source electrodes and the first drain electrodes are connected with the corresponding first active islands through the corresponding first via holes to form the first driving thin film transistors, the second source electrodes and the second drain electrodes are connected with the corresponding second active islands through the corresponding first via holes to form the second driving thin film transistors, and the width-to-length ratio of channels of the second driving thin film transistors is 5-20 times that of the first driving thin film transistors.
Optionally, the fabricating a first light emitting unit in a first region of the substrate, and fabricating a second light emitting unit in a second region of the substrate, where the first light emitting unit is a top emission organic light emitting diode, and the second light emitting unit is a double-sided light emitting organic light emitting diode, includes:
forming a planarization layer, wherein the planarization layer covers the source drain electrode layer, and the planarization layer is subjected to patterning treatment to form a second through hole penetrating through the planarization layer;
forming an anode layer on the planarization layer, wherein the anode layer comprises a first anode and a second anode, the first anode is connected with the first drain electrode through the corresponding second via hole, the second anode is connected with the corresponding second drain electrode through the corresponding second via hole, the material of the first anode comprises a transparent conductive film layer and a reflective metal layer, and the material of the second anode comprises a transparent conductive film;
forming a pixel definition layer, and carrying out patterning processing on the pixel definition layer to form a plurality of openings, wherein the orthographic projection of the openings on the substrate is positioned in the orthographic projection of the first anode or the second anode on the substrate;
forming an organic light emitting layer including a first organic light emitting structure and a second organic light emitting structure within the opening, the first organic light emitting structure being on the first anode and the second organic light emitting structure being on the second anode;
forming a cathode layer covering the organic light emitting layer.
Optionally, forming an anode layer on the planarization layer, the anode layer including the first anode and the second anode, comprising:
forming a first anode layer, and carrying out graphical processing on the first anode layer to form a plurality of first anodes positioned in the first area;
and forming a second anode layer, and performing graphical processing on the second anode layer to form a plurality of second anodes positioned in the second area.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
in the array substrate, the manufacturing method thereof and the dual-sided display device provided by this embodiment, the first light emitting unit is a top emission organic light emitting diode, which can realize single-sided light emission, and the second light emitting unit is a dual-sided light emitting organic light emitting diode, and by making the width-to-length ratio of the channel of the thin film transistor driving the second light emitting unit larger than that of the channel of the thin film transistor driving the first light emitting unit, the total light emission amount of the second light emitting unit can be made larger than that of the first light emitting unit, so that the luminance of the first light emitting unit and the second light emitting unit on the main light emitting surface is closer, thereby improving the problem of uneven luminance of the main display surface of the dual-sided display device; meanwhile, the display brightness of the auxiliary display surface is improved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a partial film structure of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a main display surface of an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a secondary display surface of an array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic frame diagram illustrating a structure of a display device according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic top view of a substrate in an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic top view of a substrate with a first driving thin film transistor and a second driving thin film transistor formed thereon according to an embodiment of the present disclosure;
fig. 9 is a schematic top view of a substrate with a first light emitting unit and a second light emitting unit formed thereon according to an embodiment of the present disclosure;
fig. 10 is a schematic flowchart illustrating step S2 in the method for manufacturing the array substrate shown in fig. 6;
fig. 11 is a schematic flowchart illustrating step S3 in the method for manufacturing the array substrate shown in fig. 6;
fig. 12 is a schematic flowchart of step S302 in the method for manufacturing the array substrate shown in fig. 11.
Reference numerals:
1-an array substrate; 2-cover plate; 3-a driving chip; 4-a power supply;
101-a substrate; 102-a buffer layer; 103-an active layer; 1031-first active island; 1032-a second active island; 104-gate layer; 1041-a first gate; 1042 — a second gate; 105-an insulating layer; 106-source drain electrode layer; 1061-a first source; 1062 — first drain; 1063-a second source; 1064-second drain; 107-a planarization layer; 108-an anode layer; 1081-a first anode; 1082 — a second anode; 109-pixel definition layer; 110-an organic light-emitting layer; 1101 — a first organic light emitting structure; 1102 — a second organic light emitting structure; 111-a cathode layer;
t1 — first driving thin film transistor; t2 — a second driving thin film transistor; EL1 — first light emitting unit; EL 2-second light emitting unit.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The inventor of the present application considers that the existing OLED dual-sided display screen is generally implemented by fabricating a top-emitting OLED and a dual-sided light-emitting OLED on an array substrate, where a main display surface refers to a surface from which both the top-emitting OLED and the dual-sided light-emitting OLED emit light, and only a surface from which the dual-sided light-emitting OLED emits light is a sub-display surface.
Because the light loss of the double-sided light-emitting OLED is large, generally the light loss exceeds 50%, and the double-sided light-emitting OLED emits light, the brightness balance between the top-emitting OLED and the double-sided light-emitting OLED on the main display surface is poor, and the display effect is affected.
The application provides an array substrate, a manufacturing method thereof and a display device, and aims to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
The present embodiment provides an array substrate, as shown in fig. 1, the array substrate provided by the present embodiment includes a plurality of first regions 10 and a plurality of second regions 20, the first regions 10 include a first driving thin film transistor T1 and a first light emitting cell EL1 electrically connected to the first driving thin film transistor T1, and the second regions 20 include a second driving thin film transistor T2 and a second light emitting cell EL2 electrically connected to the second driving thin film transistor T2; the first light emitting unit EL1 is a top emission organic light emitting diode, and the second light emitting unit EL2 is a double-sided light emitting organic light emitting diode; the width-to-length ratio of the channel of the second driving thin film transistor T2 is greater than that of the channel of the first driving thin film transistor T1.
The array substrate provided by the embodiment is used for a double-sided display device, the first light-emitting unit EL1 is a top-emission organic light-emitting diode and can realize single-sided light emission, the second light-emitting unit EL2 is a double-sided light-emitting organic light-emitting diode, and the total light-emitting amount of the second light-emitting unit EL2 can be larger than that of the first light-emitting unit EL1 by enabling the width-length ratio of the channel of the thin film transistor for driving the second light-emitting unit EL2 to be larger than that of the channel of the thin film transistor for driving the first light-emitting unit EL1, so that the luminance on the main light-emitting surfaces of the first light-emitting unit EL1 and the second light-emitting unit EL2 is closer, and the problem of uneven luminance of the main display surface of the double; meanwhile, the display brightness of the auxiliary display surface is improved.
Further, as shown in fig. 2, the array substrate provided in this embodiment includes:
and an active layer 103 including a plurality of first active islands 1031 located in the first region 10 and a plurality of second active islands 1042 located in the second region 20, wherein a material of the first active islands 1030 includes warm polysilicon (LTPS) and/or Indium Gallium Zinc Oxide (IGZO), and a material of the second active islands 1032 includes warm polysilicon (LTPS) and/or Indium Gallium Zinc Oxide (IGZO). In general, the active layer 103 is made of the same material and then patterned to form the first active island 1031 and the second active island 1032, but the first active island 1031 and the second active island 1032 may be made of different materials.
The gate layer 104, located on the active layer 103, includes a plurality of first gates 1041 located in the first region 10 and a plurality of second gates 1042 located in the second region 20. The gate layer 104 may include a first gate layer and a second gate layer, and the corresponding array substrate further includes a first gate insulating layer and a second gate insulating layer.
And an insulating layer 105 covering the gate layer 104, wherein a plurality of first via holes are formed in the insulating layer 105, and are used to connect the first drain 1061 to the corresponding first active island 1031, and connect the second drain 1062 to the corresponding second active island 1032.
A source drain electrode layer 106 on the insulating layer 105, and including a plurality of first source electrodes 1061 and a plurality of first drain electrodes 1062 in the first region 10, and a plurality of second source electrodes 1063 and a plurality of second drain electrodes 1064 in the second region 20; the first source 1061 and the first drain 1062 are connected to the first active island 1031 through corresponding first vias, respectively, and the second source 1063 and the second drain 1062 are connected to the second active island 1032 through corresponding first vias, respectively.
The first driving thin film transistor T1 includes a first active island 1032, a first gate 1041, a first source 1061 and a second drain 1062, and the second driving thin film transistor T2 includes a second active island 1032, a second gate 1042, a second source 1063 and a second drain 1064.
It should be noted that, although the first driving thin film transistor T1 and the second driving thin film transistor T2 shown in fig. 2 have a top gate structure, in practical use, the first driving thin film transistor T1 and the second driving thin film transistor T2 may have a bottom gate structure.
Specifically, as shown in fig. 2, the array substrate further includes a buffer layer 102 under the active layer 103 and a substrate 101 under the buffer layer 102. The substrate 101 may be a rigid substrate such as glass, or may be a flexible substrate such as a Polyimide (PI) film. The buffer layer 102 serves to enhance the bonding strength of the substrate 101 and the active layer 103.
Alternatively, as shown in fig. 2, the first light emitting unit EL1 includes a first anode 1081, the material of the first anode 1081 includes a transparent conductive film layer and a reflective metal layer, the second light emitting unit EL2 includes a second anode 1082, and the material of the second anode 1082 includes a transparent conductive film.
Specifically, the transparent conductive film in the first anode 1081 may be Indium Tin Oxide (ITO), and the reflective metal layer may be metal silver or metal aluminum, for example, the first anode 1081 may be a stacked structure of ITO-Ag-ITO, which can ensure both the electrical conductivity of the first anode 1081 and the high light reflection performance of the first anode 1081, thereby improving the light extraction efficiency of the first light emitting unit EL 1. The transparent conductive film layer in the second anode 1082 may be Indium Tin Oxide (ITO), which can ensure both the conductivity of the second anode 1082 and the double-sided light emission of the second light emitting unit EL 2.
Specifically, as shown in fig. 2, the array substrate provided in this embodiment further includes:
the anode layer 108 includes a plurality of first anodes 1081 disposed in the first region 10 and a plurality of second anodes 1082 disposed in the second region 20, the first anodes 1081 are electrically connected to the corresponding first drain electrodes 1062, and the second anodes 1082 are electrically connected to the corresponding second drain electrodes 1064.
An organic light emitting layer 110 including a plurality of first organic light emitting structures 1101 on a first anode 1081 and a plurality of second organic light emitting structures 1102 on a second anode 1082;
a cathode layer 111 covering the organic light emitting layer 110;
among them, the first light emitting unit EL1 includes a first anode 1081, a first organic light emitting structure 1101, and a cathode layer 111 on the first organic light emitting structure 1101, and the second light emitting unit EL2 includes a second anode 1082, a second organic light emitting structure 1102, and a cathode layer 111 on the second organic light emitting structure 1101.
Further, as shown in fig. 2, the array substrate provided in this embodiment further includes:
a planarization layer 107 covering the source/drain electrode layer 106;
the pixel defining layer 109 includes a plurality of openings, and the first organic light emitting structure 1081 and the second organic light emitting structure 1082 are respectively disposed in the corresponding openings.
Alternatively, as shown in fig. 1 or 2, the width-to-length ratio of the channel of the second driving thin film transistor T2 is 5-20 times the width-to-length ratio of the channel of the first driving thin film transistor T1.
Specifically, the current expression of the thin film transistor is:
a linear region:
a saturation area:
wherein Id is the current of the thin film transistor in a linear region; id' is the current of the thin film transistor in a saturation region; μ is the mobility of the carrier; coxA capacitance per unit area of the insulating layer; vgsIs the voltage difference between the gate and the source of the thin film transistor, VthIs the threshold voltage of the thin film transistor; vdsIs the voltage difference between the drain electrode and the source electrode of the thin film transistor;
is the width-to-length ratio of the channel of the thin film transistor.
Normally, the voltage difference V between the source and the drain of the driving thin film transistor of each light emitting unit in the array substratedsThe anode voltage VDD and the cathode voltage VSS of each light emitting cell in the array substrate are the same. Therefore, the drive current I of the first light emitting unit EL1 is in either the linear region or the saturation regionEL1With the drive current I of the second light-emitting unit EL2EL2And a ratio of the width to length of the channel of the first driving thin film transistor T1 to the width to length of the channel of the second driving thin film transistor T2.
The luminance of the light-emitting unit is positively correlated with the driving current of the light-emitting unit (i.e., the current of the thin film transistor), and the luminance of the light-emitting unit is increased as the current of the thin film transistor is increased. When the width-to-length ratio of the channel of the second driving thin film transistor T2 is 5-20 times the width-to-length ratio of the channel of the first driving thin film transistor T1, the driving current I of the second light emitting cell EL2EL2Is the driving current I of the first light emitting unit EL1EL1About 5-20 times. That is, the total amount of light emission of the second light emitting unit EL2 is 5 to 20 times that of the first light emitting unit EL 1.
However, since the second light emitting unit EL2 is a double-sided light emitting organic light emitting diode, the light loss is large, and in some tests, the light loss exceeds 50%. The light that can be effectively displayed on the front display surface by the second light emitting unit EL2 is generally 10% to 15% or even lower of the total light emission amount of the second light emitting unit EL2, and therefore, when the width-to-length ratio of the channel of the second driving thin film transistor T2 is 5 to 20 times the width-to-length ratio of the channel of the first driving thin film transistor T1, the luminance of the first light emitting unit EL1 and the second light emitting unit EL2 on the front display surface approach each other, and the uniformity of the luminance on the front display surface of the dual-sided display device is improved.
In some specific embodiments, the channel width of the first driving thin film transistor T1 is 3 micrometers and the length is 30 micrometers, and the channel width of the second driving thin film transistor T2 is 3 micrometers and the length is 3 micrometers. At this time, the width-to-length ratio of the channel of the first driving thin film transistor T1 is: 0.1/3 micron/30 micron; the width-to-length ratio of the channel of the second driving thin film transistor T2 is: 3 microns/3 microns is 1; the width-to-length ratio of the channel of the second driving thin film transistor T2 is 10 times the width-to-length ratio of the channel of the first driving thin film transistor T1.
In other specific embodiments, the first driving thin film transistor has a channel width of 2 micrometers and a length of 20 micrometers, and the second driving thin film transistor has a channel width of 4 micrometers and a length of 4 micrometers. At this time, the width-to-length ratio of the channel of the first driving thin film transistor T1 is: 2 microns/20 microns is 0.1; the width-to-length ratio of the channel of the second driving thin film transistor T2 is: 4 microns/4 microns ═ 1; the width-to-length ratio of the channel of the second driving thin film transistor T2 is 10 times the width-to-length ratio of the channel of the first driving thin film transistor T1.
In yet more specific embodiments, the first driving thin film transistor has a channel width of 3 micrometers and a length of 22.5 micrometers, and the second driving thin film transistor has a channel width of 2.5 micrometers and a length of 3 micrometers. At this time, the width-to-length ratio of the channel of the first driving thin film transistor T1 is: 3/22.5 microns-0.135; the width-to-length ratio of the channel of the second driving thin film transistor T2 is: 2.5 micron/3 micron ≈ 0.83; the width-to-length ratio of the channel of the second driving thin film transistor T2 is about 6.14 times the width-to-length ratio of the channel of the first driving thin film transistor T1.
In this embodiment, the inventors are at Vgs＝-10V，VdsUnder the condition of-10.1V, the current of the first driving thin film transistor T1 was measured to be 1.01 × 10-5A, the current of the second driving TFT T2 was measured to be 6.19 × 10-5A. Second driving thin film transistorThe ratio of the current of T2 to the current of the first driving TFT T1 is 6.19 × 10-5A/1.01×10-5A ≈ 6.14. It is detected that the difference between the luminance of the first light emitting unit EL1 and the luminance of the second light emitting unit EL2 is significantly reduced and is substantially the same.
Alternatively, as shown in fig. 3 and 4, the first light emitting cells EL1 and the second light emitting cells EL2 are alternately arranged in the pixel row direction or the pixel column direction, so that the display effect of the front display surface can be ensured while the higher resolution of the sub-display surface is ensured.
Alternatively, as shown in fig. 2 and 3, the colors of the light emitted by each of the first light-emitting units EL1 and each of the second light-emitting units EL2 may be the same, for example, both are white light, and color display is realized by configuring a color filter device; the first light-emitting units EL1 and the second light-emitting units EL2 may emit light of different colors, for example, red, green, or blue, or a part of the first light-emitting units EL1 and a part of the second light-emitting units EL2 may emit white light, that is, RGB display or RGBW display.
Based on the same inventive concept, the present embodiment provides a dual-sided display device, as shown in fig. 5, the dual-sided display device includes the array substrate 1 in the above embodiment, and has the beneficial effects of the array substrate 1 in the above embodiment, which is not described herein again.
Specifically, the double-sided display device further includes a cover plate 2, a driving chip 3, and a power supply 4. The double-sided display device is a foldable mobile phone, a double-sided display mobile phone, a notebook computer, a tablet computer, an electronic book, a drawing board, a display glass wall and the like.
Based on the same inventive concept, the present embodiment provides a manufacturing method of an array substrate, as shown in fig. 6, the manufacturing method includes:
s1: as shown in fig. 7, a substrate 101 is provided, the substrate 101 comprising a plurality of first regions 10 and a plurality of second regions 20.
S2: as shown in fig. 8, the first driving thin film transistor T1 is formed in the first region 10 of the substrate 101, the second driving thin film transistor T2 is formed in the second region 20 of the substrate 101, and the width-to-length ratio of the second driving thin film transistor T2 is greater than that of the first driving thin film transistor T1.
S3: as shown in fig. 9, a first light-emitting unit EL1 is fabricated in a first region 10 of a substrate 101, a second light-emitting unit EL2 is fabricated in a second region 20 of the substrate 101, the first light-emitting unit EL1 is a top-emission organic light-emitting diode, and the second light-emitting unit EL2 is a double-sided light-emitting organic light-emitting diode.
The manufacturing method of the array substrate provided by this embodiment is used for a double-sided display device, the first light-emitting unit EL1 is a top-emission organic light-emitting diode, and can realize single-sided light emission, the second light-emitting unit EL2 is a double-sided light-emitting organic light-emitting diode, and the total light-emitting amount of the second light-emitting unit EL2 can be made larger than that of the first light-emitting unit EL1 by making the width and length of the channel of the thin-film transistor driving the second light-emitting unit EL2 larger than that of the thin-film transistor driving the first light-emitting unit EL1, so that the luminance on the main light-emitting surfaces of the first light-emitting unit EL1 and the second light-emitting unit EL2 are closer, and the problem of uneven luminance on the main display surface of the double-sided display; meanwhile, the display brightness of the auxiliary display surface is improved.
Optionally, as shown in fig. 10 and with reference to fig. 2, in the manufacturing method provided in this embodiment, step S2 includes:
s201: an active layer 103 is formed on the substrate 101 and patterned to form a plurality of first active islands 1031 located in the first region 10 and a plurality of second active islands 1032 located in the second region 20. Specifically, as shown in fig. 1, before the active layer 103 is formed, a buffer layer 102 may be further formed on the substrate to improve the bonding strength of the active layer 103 and the substrate 101.
S202: a gate layer 104 is formed and the gate layer 104 is patterned to form a first gate 1041 on the first active island 1030 and a second gate 1042 on the second active island 1032. Specifically, the gate layer 104 may include a first gate layer and a second gate layer, and the array substrate further includes a first gate insulating layer and a second gate insulating layer, respectively.
S203: an insulating layer 105 is formed to cover the gate layer 104, and the insulating layer 105 is patterned to form a plurality of first via holes.
S204: a source drain electrode layer 106 is formed on the insulating layer 105, and patterning is performed on the insulating layer 106 to form a plurality of first source electrodes 1061, a plurality of first drain electrodes 1062, a plurality of second source electrodes 1063, and a plurality of second drain electrodes 1064, the first source electrodes 1061 and the first drain electrodes 1062 are connected to the corresponding first active islands 1031 through the corresponding first via holes to form first driving thin film transistors T1, the second source electrodes 1063 and the second drain electrodes 1064 are connected to the corresponding second active islands 1032 through the corresponding first via holes to form second driving thin film transistors T2, and a width-to-length ratio of a channel of the second driving thin film transistor T2 is 5-20 times that of a channel of the first driving thin film transistor T1.
In addition, the method of step S2 in this embodiment is a method for manufacturing a top-gate thin film transistor, but in actual use, the method of step S2 may also be a method for manufacturing a top-gate thin film transistor.
In the manufacturing method provided by this embodiment, the width-to-length ratio of the channel of the second driving thin film transistor T2 is 5 to 20 times of the width-to-length ratio of the channel of the first driving thin film transistor T1, and since the light that can be effectively displayed on the front display surface by the second light-emitting unit EL2 is usually 10% to 15% of the total light-emitting amount of the second light-emitting unit EL2, or even lower, the luminance of the first light-emitting unit EL1 and the luminance of the second light-emitting unit EL2 on the front display surface can be made close, and the uniformity of the luminance on the front display surface of the dual-panel display device can be improved.
Optionally, as shown in fig. 11, in the manufacturing method provided in this embodiment, step S3 includes:
s301: a planarization layer 107 is formed, the planarization layer 107 covers the source-drain electrode layer 106, and the planarization layer 107 is patterned to form a second via hole penetrating through the planarization layer 107.
S302: forming an anode layer 108 on the planarization layer 107, the anode layer 108 including a first anode 1081 and a second anode 1082, the first anode 1081 being connected with the first drain 1062 through the corresponding second via, the second anode 1082 being connected with the corresponding second drain 1064 through the corresponding second via; the material of the first anode 1081 includes a transparent conductive film layer and a reflective metal layer, and the material of the second anode 1082 includes a transparent conductive film.
S303: a pixel defining layer 109 is formed, and patterning is performed on the pixel defining layer 109 to form a plurality of openings, an orthogonal projection of the openings on the substrate 101 is located within an orthogonal projection of the first anode 1081 or the second anode 1082 on the substrate 101.
S304: an organic light emitting layer 110 is formed, the organic light emitting layer 110 including a first organic light emitting structure 1101 and a second organic light emitting structure 1102 positioned within the opening, the first organic light emitting structure 1101 positioned on the first anode 1081, the second organic light emitting structure 1102 positioned on the second anode 1082. Specifically, the organic light emitting layer 110 may be formed by evaporation or printing.
S305: a cathode layer 111 is formed, and the cathode layer 111 covers the organic light emitting layer 110.
In the manufacturing method provided by this embodiment, the material of the first anode 1081 includes the transparent conductive film layer and the reflective metal layer, which can ensure both the conductive performance of the first anode 1081 and the high light reflection performance of the first anode 1081, so as to improve the light-emitting efficiency of the first light-emitting unit EL 1; the material of the second anode 1082 includes a transparent conductive film, which can ensure both the conductivity of the second anode 1082 and the double-sided light emission of the second light-emitting unit EL 2.
Further, as shown in fig. 12 in combination with fig. 2, in this embodiment, step S302 includes:
s3021: a first anode layer is formed and patterned to form a plurality of first anodes 1081 positioned in the first region 10. Specifically, the first anode layer may be formed on the planarization layer 107 by sputtering, for example, the material of the first anode layer includes a transparent conductive film layer and a reflective metal layer, where the transparent conductive film in the first anode layer may be Indium Tin Oxide (ITO), and the reflective metal layer may be metal silver or metal aluminum, for example, the first anode 1 layer may be a stacked structure of ITO-Ag-ITO, so as to ensure both the conductive performance of the first anode 1081 and the high light reflection performance of the first anode 1081, thereby improving the light extraction efficiency of the first light emitting unit EL 1.
S3022: a second anode layer is formed and patterned to form a plurality of second anodes 1082 disposed in the second region 20. Specifically, the second anode layer may be formed by sputtering, the material of the second anode layer includes a transparent conductive film, and the transparent conductive film layer in the second anode layer may be Indium Tin Oxide (ITO), which not only ensures the conductivity of the second anode 1082, but also ensures that the second light-emitting unit EL2 realizes double-sided light emission. In the manufacturing process, the second anode may be manufactured first, and then the first anode may be manufactured, as long as the first anode has electrical conductivity and good light reflectivity, and the second anode has electrical conductivity and good light transmissivity.
The array substrate provided by the embodiment can realize the improvement of the uniformity of the brightness of the main light emitting surface of the double-sided display screen and improve the brightness of the auxiliary display surface only by adding one mask plate when the first anode 1081 and the second anode 1082 are formed and on the basis of not greatly increasing the processes.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
in the array substrate, the manufacturing method thereof and the dual-sided display device provided by this embodiment, the first light emitting unit is a top emission organic light emitting diode, which can realize single-sided light emission, and the second light emitting unit is a dual-sided light emitting organic light emitting diode, and by making the width-to-length ratio of the channel of the thin film transistor driving the second light emitting unit larger than that of the channel of the thin film transistor driving the first light emitting unit, the total light emission amount of the second light emitting unit can be made larger than that of the first light emitting unit, so that the luminance of the first light emitting unit and the second light emitting unit on the main light emitting surface is closer, thereby improving the problem of uneven luminance of the main display surface of the dual-sided display device; meanwhile, the display brightness of the auxiliary display surface is improved.
Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.
Claims (10)
1. The array substrate is characterized by comprising a plurality of first areas and a plurality of second areas, wherein the first areas comprise first driving thin film transistors and first light emitting units electrically connected with the first driving thin film transistors, and the second areas comprise second driving thin film transistors and second light emitting units electrically connected with the second driving thin film transistors;
the first light-emitting unit is a top-emitting organic light-emitting diode, and the second light-emitting unit is a double-sided light-emitting organic light-emitting diode;
the width-length ratio of the channel of the second driving thin film transistor is larger than that of the channel of the first driving thin film transistor.
2. The array substrate of claim 1, comprising:
the active layer comprises a plurality of first active islands positioned in the first area and a plurality of second active islands positioned in the second area, the material of the first active islands comprises warm polycrystalline silicon and/or indium gallium zinc oxide, and the material of the second active islands comprises warm polycrystalline silicon and/or indium gallium zinc oxide;
a gate layer on the active layer, including a plurality of first gates in the first region and a plurality of second gates in the second region;
the insulating layer covers the gate layer, and a plurality of first via holes penetrating through the insulating layer are formed in the insulating layer;
the source-drain electrode layer is positioned on the insulating layer and comprises a plurality of first source electrodes and a plurality of first drain electrodes which are positioned in the first area, and a plurality of second source electrodes and a plurality of second drain electrodes which are positioned in the second area, the first source electrodes and the first drain electrodes are respectively connected with the first active island through the corresponding first via holes, and the second source electrodes and the second drain electrodes are respectively connected with the second active island through the corresponding first via holes;
the first driving thin film transistor comprises a first active island, a first grid electrode, a first source electrode and a second drain electrode, and the second driving thin film transistor comprises a second active island, a second grid electrode, a second source electrode and a second drain electrode.
3. The array substrate of claim 1,
the first light emitting unit comprises a first anode, the material of the first anode comprises a transparent conductive film layer and a reflective metal layer, the second light emitting unit comprises a second anode, and the material of the second anode comprises a transparent conductive film.
4. The array substrate of any one of claims 1 to 3, wherein the width-to-length ratio of the channel of the second driving thin film transistor is 5 to 20 times the width-to-length ratio of the channel of the first driving thin film transistor.
5. The array substrate of claim 4,
the channel width of the first driving thin film transistor is 3 micrometers, the length of the first driving thin film transistor is 30 micrometers, the channel width of the second driving thin film transistor is 3 micrometers, and the length of the second driving thin film transistor is 3 micrometers; or
The channel width of the first driving thin film transistor is 2 micrometers, the length of the first driving thin film transistor is 20 micrometers, the channel width of the second driving thin film transistor is 4 micrometers, and the length of the second driving thin film transistor is 4 micrometers; or
The channel width of the first driving thin film transistor is 3 micrometers, the length of the first driving thin film transistor is 22.5 micrometers, and the channel width of the second driving thin film transistor is 2.5 micrometers, and the length of the second driving thin film transistor is 3 micrometers.
6. A double-sided display device comprising the array substrate according to any one of claims 1 to 5.
7. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a plurality of first areas and a plurality of second areas;
manufacturing a first driving thin film transistor in a first area of the substrate, manufacturing a second driving thin film transistor in a second area of the substrate, wherein the width-to-length ratio of the second driving thin film transistor is larger than that of the first driving thin film transistor;
manufacturing a first light-emitting unit in a first area of the substrate, and manufacturing a second light-emitting unit in a second area of the substrate, wherein the first light-emitting unit is a top-emission organic light-emitting diode, and the second light-emitting unit is a double-sided light-emitting organic light-emitting diode.
8. The method for manufacturing the array substrate according to claim 7, wherein a first driving thin film transistor is manufactured in a first region of the substrate, a second driving thin film transistor is manufactured in a second region of the substrate, and a width-to-length ratio of the second driving thin film transistor is larger than that of the first driving thin film transistor, and the method comprises the following steps:
forming an active layer on the substrate, and performing patterning processing on the active layer to form a plurality of first active islands located in the first region and a plurality of second active islands located in the second region;
forming a gate layer, and carrying out patterning processing on the gate layer to form a first gate positioned on the first active island and a second gate positioned on the second active island;
forming an insulating layer covering a gate layer, and performing patterning processing on the insulating layer to form a plurality of first via holes;
and forming a source drain electrode layer on the insulating layer, and performing graphical processing on the insulating layer to form a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes and a plurality of second drain electrodes, wherein the first source electrodes and the first drain electrodes are connected with the corresponding first active islands through the corresponding first via holes to form the first driving thin film transistors, the second source electrodes and the second drain electrodes are connected with the corresponding second active islands through the corresponding first via holes to form the second driving thin film transistors, and the width-to-length ratio of channels of the second driving thin film transistors is 5-20 times that of the first driving thin film transistors.
9. The method for manufacturing an array substrate according to claim 8, wherein a first light emitting unit is manufactured in a first region of the substrate, a second light emitting unit is manufactured in a second region of the substrate, the first light emitting unit is a top emission organic light emitting diode, and the second light emitting unit is a double-sided light emitting organic light emitting diode, comprising:
forming a planarization layer, wherein the planarization layer covers the source drain electrode layer, and the planarization layer is subjected to patterning treatment to form a second through hole penetrating through the planarization layer;
forming an anode layer on the planarization layer, wherein the anode layer comprises a first anode and a second anode, the first anode is connected with the first drain electrode through the corresponding second via hole, the second anode is connected with the corresponding second drain electrode through the corresponding second via hole, the material of the first anode comprises a transparent conductive film layer and a reflective metal layer, and the material of the second anode comprises a transparent conductive film;
forming a pixel definition layer, and carrying out patterning processing on the pixel definition layer to form a plurality of openings, wherein the orthographic projection of the openings on the substrate is positioned in the orthographic projection of the first anode or the second anode on the substrate;
forming an organic light emitting layer including a first organic light emitting structure and a second organic light emitting structure within the opening, the first organic light emitting structure being on the first anode and the second organic light emitting structure being on the second anode;
forming a cathode layer covering the organic light emitting layer.
10. The method for manufacturing an array substrate according to claim 9, wherein forming an anode layer on the planarization layer, the anode layer including the first anode and the second anode, comprises:
forming a first anode layer, and carrying out graphical processing on the first anode layer to form a plurality of first anodes positioned in the first area;
and forming a second anode layer, and performing graphical processing on the second anode layer to form a plurality of second anodes positioned in the second area.
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