CN111180451A

CN111180451A - 3D memory device and method of manufacturing the same

Info

Publication number: CN111180451A
Application number: CN201911414935.3A
Authority: CN
Inventors: 刘沙沙
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-05-19
Anticipated expiration: 2039-12-31
Also published as: CN111180451B

Abstract

Disclosed are a 3D memory device and a method of manufacturing the same, the 3D memory device including: a substrate; a gate stack structure over the substrate; the channel column penetrates through the gate laminated structure and comprises a functional layer, a channel layer and a filling layer; the epitaxial layer is positioned below the channel column and is in contact with the channel layer; the functional layer comprises a gate oxide layer, a charge storage layer and a tunneling oxide layer; an oxide layer over the charge storage layer at the top of the channel pillar; the plug structure is positioned at the top of the channel column and completely covers the channel column; wherein the charge storage layer on the top of the channel column is isolated from the plug structure by the oxide layer. According to the embodiment of the invention, the charge storage layer on the top of the channel column is isolated from the plug structure above the charge storage layer, so that the charge storage layer is isolated from the channel layer on the top of the channel column, the charge on the charge storage layer is prevented from leaking into the channel layer through the plug structure, and the stability of the threshold voltage of the top selection gate of the 3D memory is improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the aperture of a semiconductor manufacturing process becomes smaller, the memory density of a memory device becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

The formation process of existing 3D NAND memories generally includes: forming an insulating stacked structure 150 (not shown) in which a silicon nitride layer 151 and a silicon oxide layer 152 (not shown) are alternately stacked on a substrate; etching the insulation laminated structure, forming a channel hole in the insulation laminated structure, etching the substrate at the bottom of the channel hole after the channel hole is formed, and forming a groove in the substrate; forming an Epitaxial silicon layer, also commonly referred to as SEG, in the recess at the bottom of the channel hole by Selective Epitaxial Growth (Selective Epitaxial Growth); forming a functional layer (an ONO layer) and a channel layer in the side wall and the bottom of the channel hole, wherein the channel layer is connected with an epitaxial silicon layer (SEG), the functional layer comprises a gate oxide layer 114, a charge storage layer 113 positioned on the gate oxide layer and a tunneling oxide layer 112 positioned on the charge storage layer, and the selected material can be a single-layer and/or multi-layer combined structure of oxide-nitride-oxide (ONO); forming a filling layer 115 on the channel layer by adopting Atomic Layer Deposition (ALD), etching back the filling layer to form a groove, and depositing polysilicon (Poly) in the groove to form a polysilicon Plug 116(Poly Plug) with an ONO layer along the side wall of the channel hole; the silicon nitride layer is removed and

gate metals

121, 122 and 123 are formed at the locations where the silicon nitride layer is removed, forming a gate stack structure 120. A metal Via 117(metal Via) is formed on the polysilicon Plug 116(Poly Plug), and the polysilicon Plug 116 is connected to the metal layer in the subsequent process (BEOL) through the metal Via 117, as shown in fig. 1 a. In order to effectively align the polysilicon plug with the metal via, the aperture of the polysilicon plug is expanded to be the same as that of the channel hole, as shown in fig. 1 b.

The charge storage layer 113 of the functional layer is now in contact with the channel layer 111 on top via the polysilicon plug 116. Due to the poor charge confinement capability of the Top Select Gate (TSG), charges on the charge storage layer easily leak into the channel layer through the polysilicon plug, which may cause a shift of the threshold voltage Vt of the Top Select Gate TSG, affecting the performance of the 3D memory device, especially during erasing or reading/writing. After repeated erasing or reading/writing, a large amount of charge will accumulate at the corners, further shifting the threshold voltage Vt of the top select gate TSG.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a 3D memory device and a method of fabricating the same, in which a charge storage layer and a polysilicon plug are separated at the top of a functional layer, thereby improving stability of a threshold voltage of a top select gate of the 3D memory device.

According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming an insulating stack structure over a substrate, the insulating stack structure including sacrificial layers and insulating layers alternately stacked; forming a plurality of channel columns penetrating through the insulation laminated structure, wherein each channel column comprises a functional layer, a channel layer located on the functional layer and a filling layer located on the channel layer, and the functional layer comprises a gate oxide layer, a charge storage layer located on the gate oxide layer and a tunneling oxide layer located on the charge storage layer; removing the charge storage layer at the top of the channel column to form a gap and forming an oxide layer in the gap; removing the gate oxide layer, the tunneling oxide layer, the oxide layer and the filling layer on the top of the channel column to form a groove; depositing polycrystalline silicon in the groove to form a plug structure; and the charge storage layer at the top of the channel column is isolated from the plug structure by the oxide layer.

Preferably, before forming the channel pillar, the method further includes: and forming a first hard mask layer on the insulation laminated structure, wherein the first hard mask layer is an oxide layer.

Preferably, the manufacturing method further includes: a second hard mask layer is formed on the first hard mask layer.

Preferably, the first hard mask layer is removed while the charge storage layer at the top of the channel pillar is removed.

Preferably, an oxide layer is formed on the first hard mask layer while forming an oxide layer in the void.

Preferably, the removing the gate oxide layer, the tunneling oxide layer, the oxide layer and the filling layer on the top of the channel pillar to form a groove comprises: sequentially forming an anti-reflection coating and a light resistance layer on the oxide layer; patterning the light resistance layer and etching the anti-reflection coating according to the patterned light resistance layer to form an opening; etching the gate oxide layer, the tunneling oxide layer, the oxide layer and the filling layer by using an anti-reflection coating with an opening as a mask to form a groove; wherein the recess does not extend to the charge storage layer.

Preferably, the step of forming the channel pillar includes: forming a plurality of channel holes through the insulating stack structure and a portion of the substrate; forming an epitaxial layer at the bottom of the channel hole, wherein the epitaxial layer is in contact with the substrate; forming a functional layer, a channel layer and a filling layer on the side wall and the bottom of the channel hole in sequence; wherein the channel layer is located above the epitaxial layer and is in contact with the epitaxial layer.

Preferably, the step of forming the voids comprises: and when the charge storage layer at the top of the channel column is removed, the charge storage layer has a high etching selection ratio relative to the gate oxide layer and the tunneling oxide layer.

Preferably, the ratio of the etching rate of the charge storage layer to the etching rate of the gate oxide layer, the etching rate of the tunneling oxide layer, the etching rate of the oxide layer and the etching rate of the channel layer are at least greater than 30: 1.

Preferably, the manufacturing method further includes: the plurality of sacrificial layers are replaced with a plurality of gate conductors to form a gate stack structure.

According to another aspect of the present invention, there is provided a 3D memory device including: a substrate; a gate stack structure over the substrate, the gate stack structure comprising gate conductors and insulating layers that are alternately stacked; and a plurality of channel pillars penetrating through the gate stack structure, the channel pillars including a functional layer, a channel layer, and a filling layer on sidewalls and a bottom of the channel pillars; the epitaxial layer is positioned below the channel column and is in contact with the channel layer; the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer; the oxide layer is positioned above the charge storage layer at the top of the channel column; a plug structure at the top of the channel pillar, the plug structure completely covering the channel pillar; and the charge storage layer at the top of the channel column is isolated from the plug structure by the oxide layer.

Preferably, the 3D memory device further includes: and the first hard mask layer is positioned on the insulation laminated structure and is an oxide layer.

Preferably, the charge storage layer has a high etch selectivity with respect to the gate oxide layer, the tunnel oxide layer, the oxide layer, and the channel layer.

According to the 3D memory device and the manufacturing method thereof provided by the invention, part of the charge storage layer is removed from the top of the channel column, and the plug structure formed on the channel column is isolated from the charge storage layer, so that the charge storage layer is isolated from the channel layer at the top of the channel column, the charge on the charge storage layer is prevented from leaking into the channel layer through the plug structure, and the stability of the threshold voltage of the top selection gate of the 3D memory is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIGS. 1a and 1b show schematic cross-sectional views of different stages of a prior art 3D memory device, respectively;

fig. 2a and 2b show a circuit diagram and a schematic structural diagram, respectively, of a memory cell string of a 3D memory device;

FIG. 3 shows a perspective view of a 3D memory device;

fig. 4a to 4g show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention;

fig. 5a to 5g illustrate cross-sectional views of stages of a method of manufacturing a 3D memory device according to another embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The term "above" as used herein means above the plane of the substrate, and may refer to direct contact between materials or spaced apart.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 2a and 2b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 2a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory cells M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of memory cells M1-M4 are connected to corresponding ones of word lines WL 1-WL 4, respectively.

As shown in fig. 2b, the selection transistors Q1 and Q2 of the memory cell string 100 include the second conductor layer 122 and the third conductor layer 123, respectively, and the memory cells M1 to M4 include the first conductor layer 121, respectively. The first, second, and

third conductor layers

121, 122, and 123 are stacked in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming a gate stack structure.

Further, the memory cell string 100 includes a memory string 110. The memory string 110 is adjacent to or through the gate stack structure. In the middle portion of the memory string 110, the first conductor layer 121 and the channel layer 111 sandwich the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114, thereby forming the memory cells M1 through M4. At both ends of the memory string 110, the gate oxide layer 114 is interposed between the second conductor layers 122 and 123 and the channel layer 111, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

The channel layer 111 is composed of, for example, doped polysilicon, the tunnel oxide layer 112 and the gate oxide layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the first conductor layer 121, the second conductor layer 122 and the third conductor layer 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the memory string 110 is the channel layer 111, and the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 form a stacked structure surrounding the core sidewall. In an alternative embodiment, the core of the memory string 110 is an additional insulating layer, and the channel layer 111, the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory cells M1 to M4 use the common channel layer 111 and gate oxide layer 114. In the memory string 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layers and the gate oxide layers of the first and second selection transistors Q1 and Q2 and the semiconductor layers and the gate oxide layers of the memory cells M1 to M4, respectively, may be formed in steps independent of each other. In the memory string 110, semiconductor layers of the first and second selection transistors Q1 and Q2 and semiconductor layers of the memory cells M1 to M4 are electrically connected to each other.

In a write operation, memory cell string 100 writes data to a selected memory cell of memory cells M1-M4 using FN tunneling efficiency. Taking the memory cell M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the second selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since the word line voltage of only the selected memory cell M2 is higher than the tunneling voltage, electrons in the channel region of the memory cell M2 reach the charge storage layer 113 through the tunneling oxide layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory cell M2.

In a read operation, the memory cell string 100 determines the amount of charge in the functional layer from the on-state of a selected one of the memory cells M1 through M4, thereby obtaining data indicative of the amount of charge. Taking cell M2 as an example, word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory cell M2 is related to its threshold voltage, i.e. to the amount of charge in the functional layer, so that the data value can be determined from the on state of the memory cell M2. The memory cells M1, M3 and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory cell M2. The control circuit determines the conductive state of the memory cell M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory cell M2.

Fig. 3 shows perspective views of the 3D memory devices, respectively. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 3.

The 3D memory device 200 shown in this embodiment includes 4 x 4 for a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 for a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device 200, the memory cell strings 100 respectively include the respective channel pillars 110, and the common first, second, and third conductor layers 121, 122, and 123. The first, second, and third conductor layers 121, 122, and 123 are stacked in accordance with the order of the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming a gate stack structure 120. The insulating layer is not shown in the figure.

The internal structure of the memory string 110 is shown in fig. 2b and will not be described in detail here. In the middle portion of the memory string 110, the first conductor layer 121 forms memory cells M1 through M4 together with the channel layer 111, the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 inside the memory string 110. At both ends of the memory string 110, the second and third conductor layers 122 and 123 form a first selection transistor Q1 and a second selection transistor Q2 together with the channel layer 111 and the gate oxide layer 114 inside the memory string 110.

The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, wherein first ends of the plurality of memory strings 110 in the same column are commonly connected to the same bit line (i.e., one of BL1-BL 4), second ends are commonly connected to the substrate 101, and the second ends form a common source connection through the substrate 100.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 102. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductors 121 of the memory transistors M1 and M4 are integrally connected at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via a conductive path 133.

The gate conductors of the ground select transistors Q2 are connected in one piece. If the gate conductor 123 of the ground selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via a conductive path 133.

Fig. 4a to 4g illustrate cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

The method begins with a semiconductor structure in which a channel pillar 110 has been formed, as shown in figure 4 a.

In this step, an insulating stacked structure 150 formed by alternately stacking a sacrificial layer 151 and an insulating layer 152 on a substrate 101 is formed by a Deposition process, such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD), a first hard mask layer 160 and a second hard mask layer 170 are respectively formed on the insulating stacked structure 150, a channel hole 102 (not shown) penetrating the insulating stacked structure 150 is formed, and an epitaxial layer 103 is formed at the bottom of the channel hole 102. In this embodiment, the substrate 101 is, for example, a single crystalline silicon substrate, the sacrificial layer 151 includes, but is not limited to, silicon oxide, and the insulating layer 152 includes, but is not limited to, silicon nitride. The insulating layer 152 will be replaced with a conductive layer in a subsequent gate formation process. The Epitaxial layer 103 may, for example, be a Selective Epitaxial Growth (SEG).

In the embodiment, the insulating stack structure shown includes 5 insulating layers 152, and the number of the insulating layers 152 is set to be other according to different requirements of different 3D memory devices for the number of memory cells in the manufacturing process of a specific 3D memory device.

Further, a first hard mask layer 160 and a second hard mask layer 170 are formed on the insulation stack structure 150, respectively, as shown in fig. 4 a.

In the present embodiment, the first hard mask layer 160 includes, but is not limited to, silicon oxide, and the second hard mask layer 170 includes, but is not limited to, silicon nitride.

Further, a channel pillar 110 is formed within the channel hole 102, as shown in fig. 4 a.

In this step, the channel pillar 110 includes a functional layer (ONO layer) including a gate oxide layer 114, a charge storage layer 113 on the gate oxide layer, and a tunnel oxide layer 112 on the charge storage layer, a channel layer 111, and a filling layer 115.

Specifically, the gate oxide layer 114, the charge storage layer 113, the tunnel oxide layer 112, the channel layer 111, and the filling layer 115 are formed in the channel hole 102 along the sidewalls and bottom thereof, and the selected material may be a single-layer and/or multi-layer combination structure of oxide-nitride-oxide-polysilicon-oxide (ONOPO), but is not limited to the materials and combinations mentioned herein. In this embodiment, the gate oxide layer 114 and the tunnel oxide layer 112 are, for example, silicon oxide, and the charge storage layer 113 is, for example, silicon nitride. The gate oxide layer 114, the charge storage layer 113, the tunnel oxide layer 112, the channel layer 111 and the filling layer 115 are formed by a chemical vapor deposition process. The material of the filling layer 115 is silicon oxide or other suitable material.

Further, the first hard mask layer 170 and a portion of the charge storage layer 113 on the sidewall of the channel hole 102 are removed to form a void, as shown in fig. 4 b.

In this step, the first hard mask layer 170 and a portion of the charge storage layer 113 on the sidewall of the channel hole 102 are removed by dry etching, which is anisotropic plasma etching in an embodiment. Removing the first hard mask layer 170 and a part of the charge storage layer 113 on the side wall of the channel hole 102, wherein the charge storage layer 113 has a high etching selectivity ratio relative to the gate oxide layer 114, the tunneling oxide layer 112 and the channel layer 111, and the etching rate ratio of the charge storage layer 113 relative to the gate oxide layer 114, the tunneling oxide layer 112 and the channel layer 111 is at least more than 30: 1. since the charge storage layer 113 and the first hard mask layer 170 are nitride layers, and the gate oxide layer 114 and the tunnel oxide layer 112 are oxide layers, that is, the first hard mask layer 170 and a portion of the charge storage layer 113 on the sidewall of the channel hole 102 are removed by using an etching process with a high etch selectivity (hghetchselectricity) for the nitride layer (e.g., silicon nitride SiN) and the oxide layer (e.g., silicon oxide SiO2), so that the gate oxide layer 114 and the tunnel oxide layer 112 on the sidewall of the channel hole 102 are etched by a small amount.

Further, an oxide layer is formed within the void 105 and on the first hard mask layer 160, as shown in fig. 4 c.

In this step, a gate oxide layer 114 is formed within the void 105 and on the surface of the first hard mask layer 160, such that the oxide layer on top of the channel hole 102 includes the gate oxide layer 114 and the tunnel oxide layer 112 on the gate oxide layer.

Further, an Anti-Reflection Coating (ARC) 180 and a photoresist mask layer (PR) 190 are formed on the semiconductor structure, and the photoresist layer 190 is patterned by a photolithography process, as shown in fig. 4 c.

Further, the anti-reflective coating layer 180 is etched using the patterned photoresist layer 190 to form an opening, and the photoresist layer 190 is removed, as shown in FIG. 4 d.

In this step, the characteristic dimension of the opening is the same as the aperture of the channel hole.

Further, using the anti-reflection coating 180 with an opening as a mask, a groove is formed by etching and removing a part of the gate oxide layer 114 and a part of the tunnel oxide layer 112, and the charge storage layer 113 is still covered by the gate oxide layer 114 at the top of the channel hole, as shown in fig. 4 e.

In this step, an anisotropic dry etching process is used to etch the gate oxide layer 114 and a portion of the tunnel oxide layer 112 on top of the trench hole. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a fluorocarbon-containing gas. The characteristic dimension of the recess is the same as the characteristic dimension of the opening, i.e. as the aperture of the channel hole.

Further, polysilicon is deposited within the recess to form plug structure 116, as shown in fig. 4 f.

In the present embodiment, the plug structure 116 is formed to completely cover the gate oxide layer 114, the charge storage layer 113, the tunnel oxide layer 112, the channel layer 111 and the filling layer 115 of the channel pillar 110, the plug structure 116 is isolated from the charge storage layer 113, and the plug structure 116 is in contact with the channel layer 111.

Further, the plurality of insulating layers 152 are replaced with a plurality of gate conductors to form a gate stack structure 120, as shown in fig. 4 g.

In this step, the insulating layer 152 is replaced with the

gate conductors

121, 122 and 123, thereby forming the gate stack structure 120. The material of the

gate conductors

121, 122 and 123 may be metal or other conductive material (e.g., polysilicon, etc.). In this embodiment, the conductive material is a metal, and the metal is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. Wherein the epitaxial layer 103 and the gate conductor 121 form a first select transistor; the channel layer 111 and gate conductor 122 form a plurality of memory transistors; the channel layer 111 and the gate conductor 123 form a second selection transistor.

The method begins with a semiconductor structure in which a channel pillar 110 has been formed, as shown in figure 5 a.

Further, a first hard mask layer 160 is formed on the insulation stack structure 150, as shown in fig. 5 a.

In the present embodiment, the first hard mask layer 160 is an oxide layer, including but not limited to silicon oxide.

Further, a channel pillar 110 is formed within the channel hole 102, as shown in fig. 5 a.

Further, a portion of the charge storage layer 113 on the sidewall of the channel hole 102 is removed to form a void, as shown in fig. 5 b.

In this step, a portion of the charge storage layer 113 on the sidewall of the channel hole 102 is removed by dry etching, which is anisotropic plasma etching in one embodiment. Removing a portion of the charge storage layer 113 on the sidewall of the channel hole 102, wherein the charge storage layer 113 has a high etching selectivity with respect to the gate oxide layer 114, the tunnel oxide layer 112 and the channel layer 111. Since the charge storage layer 113 is a nitride layer and the gate oxide layer 114 and the tunnel oxide layer 112 are oxide layers, the first hard mask layer 170 and a portion of the charge storage layer 113 on the sidewall of the channel hole 102 are removed by using an etching process with a High Etch selectivity (High Etch selectivity) for a nitride layer (e.g., silicon nitride SiN) and an oxide layer (e.g., silicon oxide SiO2), so that the gate oxide layer 114 and the tunnel oxide layer 112 on the sidewall of the channel hole 102 are etched by a small amount.

Further, an oxide layer 170 is formed within the void 105 and on the first hard mask layer 160, as shown in fig. 5 c.

In this step, an oxide layer 170 is formed in the void 105 and on the surface of the first hard mask layer 160, and the material of the oxide layer 170 includes, but is not limited to, silicon oxide.

Further, an Anti-Reflection Coating (ARC) 180 and a photoresist mask layer (PR) 190 are formed on the semiconductor structure, and the photoresist layer 190 is patterned by a photolithography process, as shown in fig. 5 c.

Further, the anti-reflective coating layer 180 is etched using the patterned photoresist layer 190 to form an opening, and the photoresist layer 190 is removed, as shown in FIG. 5 d.

Further, using the anti-reflection coating 180 with an opening as a mask, etching to remove a portion of the gate oxide layer 114, a portion of the tunnel oxide layer 112, and a portion of the oxide layer 170 to form a recess, and the charge storage layer 113 is still covered by the gate oxide layer 114 at the top of the channel hole, as shown in fig. 5 e.

In this step, an anisotropic dry etching process is used to etch the gate oxide layer 114, a portion of the tunnel oxide layer 112, and a portion of the oxide layer 170 on top of the trench hole. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a fluorocarbon-containing gas. The characteristic dimension of the recess is the same as the characteristic dimension of the opening, i.e. as the aperture of the channel hole.

Further, polysilicon is deposited within the recess to form plug structure 116, as shown in fig. 5 f.

In the present embodiment, the plug structure 116 is formed to completely cover the gate oxide layer 114, the charge storage layer 113, the tunnel oxide layer 112, the channel layer 111 and the filling layer 115 of the channel pillar 110, the plug structure 116 is isolated from the charge storage layer 113 by the oxide layer 170, and the plug structure 116 is in contact with the channel layer 111, so that the charge storage layer 113 is isolated from the channel layer 111 at the top of the channel pillar 110.

Further, the plurality of insulating layers 152 are replaced with a plurality of gate conductors to form a gate stack structure 120, as shown in fig. 5 g.

In this step, the insulating layer 152 is replaced with the

gate conductors

Other details of the 3D memory device, such as the structure of the memory array, the peripheral interconnections, etc., are not important to the present invention and will not be described herein.

In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D nand flash memory.

Further, the plug structure covers the entire channel pillar, i.e., the aperture of the plug structure is the same as that of the channel pillar, so that the metal through hole formed subsequently can be easily aligned with the plug structure.

Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes. For example, certain steps are not required and thus may be omitted or replaced with other steps.

The semiconductor structure formed by the above embodiments may be processed by the following conventional steps to obtain a three-dimensional memory device.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of fabricating a 3D memory device, comprising:

forming an insulating stack structure over a substrate, the insulating stack structure including sacrificial layers and insulating layers alternately stacked;

forming a plurality of channel columns penetrating through the insulation laminated structure, wherein each channel column comprises a functional layer, a channel layer located on the functional layer and a filling layer located on the channel layer, and the functional layer comprises a gate oxide layer, a charge storage layer located on the gate oxide layer and a tunneling oxide layer located on the charge storage layer;

removing the charge storage layer at the top of the channel column to form a gap and forming an oxide layer in the gap;

removing the gate oxide layer, the tunneling oxide layer, the oxide layer and the filling layer on the top of the channel column to form a groove;

depositing polycrystalline silicon in the groove to form a plug structure;

and the charge storage layer at the top of the channel column is isolated from the plug structure by the oxide layer.

2. The method of manufacturing of claim 1, further comprising, prior to forming the channel pillar:

and forming a first hard mask layer on the insulation laminated structure, wherein the first hard mask layer is an oxide layer.

3. The manufacturing method according to claim 2, further comprising:

a second hard mask layer is formed on the first hard mask layer.

4. The method of claim 3, wherein the first hard mask layer is removed while the charge storage layer on top of the channel pillar is removed.

5. The manufacturing method according to claim 2 or 4, wherein an oxide layer is formed on the first hard mask layer simultaneously with formation of an oxide layer in the void.

6. The manufacturing method according to claim 5, wherein removing the gate oxide layer, the tunneling oxide layer, the oxide layer and the filling layer on the top of the channel pillar to form a groove comprises:

sequentially forming an anti-reflection coating and a light resistance layer on the oxide layer;

patterning the light resistance layer and etching the anti-reflection coating according to the patterned light resistance layer to form an opening;

etching the gate oxide layer, the tunneling oxide layer, the oxide layer and the filling layer by using an anti-reflection coating with an opening as a mask to form a groove;

wherein the recess does not extend to the charge storage layer.

7. The method of manufacturing of claim 1, wherein the step of forming the channel pillar comprises:

forming a plurality of channel holes through the insulating stack structure and a portion of the substrate;

forming an epitaxial layer at the bottom of the channel hole, wherein the epitaxial layer is in contact with the substrate; and

forming a functional layer, a channel layer and a filling layer on the side wall and the bottom of the channel hole in sequence;

wherein the channel layer is located above the epitaxial layer and is in contact with the epitaxial layer.

8. The method of manufacturing of claim 1, wherein the step of forming the void comprises:

and when the charge storage layer at the top of the channel column is removed, the charge storage layer has a high etching selection ratio relative to the gate oxide layer and the tunneling oxide layer.

9. The method of manufacturing of claim 8, wherein the ratio of the etch rate of the charge storage layer to the gate oxide and the tunnel oxide is at least greater than 30: 1.

10. The manufacturing method according to claim 1, further comprising:

the plurality of sacrificial layers are replaced with a plurality of gate conductors to form a gate stack structure.

11. A 3D memory device, comprising:

a substrate;

a gate stack structure over the substrate, the gate stack structure comprising gate conductors and insulating layers that are alternately stacked; and

a plurality of channel pillars penetrating through the gate stack structure, the channel pillars including a functional layer, a channel layer, and a filling layer on sidewalls and a bottom of the channel pillars;

the epitaxial layer is positioned below the channel column and is in contact with the channel layer;

the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer;

the oxide layer is positioned above the charge storage layer at the top of the channel column;

a plug structure at the top of the channel pillar, the plug structure completely covering the channel pillar;

12. The 3D memory device of claim 11, further comprising:

and the first hard mask layer is positioned on the insulation laminated structure and is an oxide layer.

13. The 3D memory device of claim 11, wherein the charge storage layer has a high etch selectivity ratio with respect to the gate oxide, the tunnel oxide, and the oxide layer.

14. The 3D memory device of claim 13, wherein an etch rate ratio of the charge storage layer to the gate oxide, the tunnel oxide, and the oxide layer is at least greater than 30: 1.