CN111162126B - 高压半导体装置 - Google Patents

高压半导体装置 Download PDF

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CN111162126B
CN111162126B CN201811619517.3A CN201811619517A CN111162126B CN 111162126 B CN111162126 B CN 111162126B CN 201811619517 A CN201811619517 A CN 201811619517A CN 111162126 B CN111162126 B CN 111162126B
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buried layer
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CN111162126A (zh
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韦维克
陈柏安
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Nuvoton Technology Corp
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Abstract

本发明提供了一种高压半导体装置,包含半导体衬底具有第一导电型,第一阱设置于半导体衬底上,第一阱具有第一导电型,第二阱和第三阱与第一阱相邻,且具有与第一导电型相反的第二导电型,具有第二导电型的第一源极区和第一漏极区分别设置于第一阱和第二阱中,第一栅极结构设置于第一阱和第二阱上,具有第二导电型的第二源极区和第二漏极区分别设置于第一阱和第三阱中,第二栅极结构设置于第一阱和第三阱上,以及埋置层设置于半导体衬底中且具有第一导电型,埋置层与第一阱、第二阱和第三阱重叠且位于第一源极区下方。

Description

高压半导体装置
技术领域
本发明是有关于半导体装置,特别为有关于高压半导体装置。
背景技术
高压半导体装置技术适用于高电压与高功率的集成电路领域。传统高压半导体装置,例如垂直式扩散金属氧化物半导体(vertically diffused metal oxidesemiconductor,VDMOS)晶体管及水平扩散金属氧化物半导体(laterally diffused metaloxide semiconductor,LDMOS)晶体管,主要用于12V以上的元件应用领域。高压装置技术的优点在于符合成本效益,且易相容于其它工艺,已广泛应用于显示器驱动IC元件、电源供应器、电力管理、通信、车用电子或工业控制等领域中。
虽然现存的高压半导体装置已逐步满足它们既定的用途,但它们仍未在各方面皆彻底的符合要求。因此,关于高压半导体装置和制造技术仍有一些问题需要克服。
发明内容
根据一些实施例,提供高压半导体装置。高压半导体装置包含半导体衬底,具有第一导电型;第一阱,设置于半导体衬底上,其中第一阱具有第一导电型;第二阱,与第一阱相邻,其中第二阱具有与第一导电型相反的第二导电型;第一源极区和第一漏极区,分别设置于第一阱和第二阱中,其中第一源极区和第一漏极区具有第二导电型,且对第一漏极区施加一第一电压;第一栅极结构,设置于第一阱和第二阱上;第三阱,设置于半导体衬底上,且与第一阱相邻,其中第三阱具有第二导电型;第二源极区和第二漏极区,分别设置于第一阱和第三阱中,其中第二源极区和第二漏极区具有第二导电型,且对第二漏极区施加一第二电压,第二电压不同于第一电压;第二栅极结构,设置于第一阱和第三阱上;以及埋置层,设置于半导体衬底中且具有第一导电型,其中埋置层与第一阱、第二阱和第三阱重叠,且埋置层位于第一源极区下方。
根据一些实施例,提供高压半导体装置。高压半导体装置包含半导体衬底,具有第一导电型;第一阱,设置于半导体衬底上,其中第一阱具有第一导电型;第二阱和第三阱,设置于半导体衬底上,且位于第一阱的两侧,其中第二阱和第三阱具有与第一导电型相反的第二导电型;第一源极区和第一漏极区,分别设置于第一阱和第二阱中,其中第一源极区和第一漏极区具有第二导电型;第二源极区和第二漏极区,分别设置于第一阱和第三阱中,其中第二源极区和第二漏极区具有第二导电型;第一栅极结构,设置于第一阱和第二阱上;第二栅极结构,设置于第一阱和第三阱上;以及埋置层,设置于半导体衬底中,且与第一源极区和第二源极区垂直重叠,其中埋置层具有第一导电型。
附图说明
图1显示依据本发明的一些实施例的高压半导体装置的剖面示意图。
图2显示依据本发明的一些实施例的高压半导体装置的上视图。
图3显示依据本发明的一些实施例的高压半导体装置的剖面示意图。
图4显示依据本发明的一些实施例的高压半导体装置的剖面示意图。
图5-图6显示依据本发明的一些实施例的高压半导体装置的掺杂轮廓示意图。
附图标号:
100、200、300 高压半导体装置;
101 半导体衬底;
102 第一阱;
103 第二阱;
104 第一源极区;
105 第一漏极区;
106 第一栅极结构;
107、207、307 埋置层;
108 第三阱;
109 第二源极区;
110 第二漏极区;
111 第二栅极结构;
112 第一隔离结构;
113 第二隔离结构;
114 第一漂移区;
115 第二漂移区;
116 重掺杂区;
117 基体区;
118 第四阱;
121 外延层;
w1、w2、w3、wA、wB、wA’、wB’ 宽度。
具体实施方式
以下揭露提供了很多不同的实施例或范例,用于实施所提供的高压半导体装置的不同元件。各元件和其配置的具体范例描述如下,以简化本发明实施例。当然,这些仅仅是范例,并非用以限定本发明。举例而言,叙述中若提及第一元件形成在第二元件之上,可能包含第一和第二元件直接接触的实施例,也可能包含额外的元件形成在第一和第二元件之间,使得它们不直接接触的实施例。此外,本发明实施例可能在不同的范例中重复参考数字及/或字母。如此重复是为了简明和清楚,而非用以表示所讨论的不同实施例及/或形态之间的关系。
以下描述实施例的一些变化。在不同图式和说明的实施例中,相似的参考数字被用来标明相似的元件。可以理解的是,在方法的前、中、后可以提供额外的操作,且一些叙述的操作可为了该方法的其他实施例被取代或删除。
请参照图1,其显示出依据本发明的一些实施例的高压半导体装置100的剖面示意图。高压半导体装置100包含半导体衬底101。半导体衬底101可由硅或其他半导体材料制成,或者,半导体衬底101可包含其他元素半导体材料,例如锗(Ge)。在一些实施例中,半导体衬底101由化合物半导体制成,例如碳化硅、氮化镓、砷化镓、砷化铟或磷化铟。在一些实施例中,半导体衬底101由合金半导体制成,例如硅锗、碳化硅锗、磷化砷镓或磷化铟镓。
此外,半导体衬底101可包含绝缘层上覆硅(silicon-on-insulator,SOI)衬底。在一些实施例中,半导体衬底101可为轻掺杂的P型或N型衬底。在本实施例中,半导体衬底101为P型,其内部具有P型掺质(例如硼(B)),且后续形成的高压半导体装置100可包含N型的水平扩散金属氧化物半导体(LDMOS)晶体管。
在一些实施例中,高压半导体装置100包含外延层121。外延层121设置于半导体衬底101上。在本实施例中,外延层121为P型。在一些实施例中,外延层121可藉由金属有机物化学气相沉积法(metal organic chemical vapor deposition,MOCVD)、等离子体增强化学气相沉积法(plasma-enhanced CVD,PECVD)、分子束外延法(molecular beam epitaxy,MBE)、氢化物气相外延法(hydride vapour phase epitaxy,HVPE)、液相外延法(liquidphase epitaxy,LPE)、氯化物气相外延法(chloride-vapor phase epitaxy,Cl-VPE)、其他相似的工艺方法或前述的组合以形成。在一些其他实施例中,高压半导体装置100可不包含外延层121,后续形成于外延层121内的阱和掺杂区可直接形成于半导体衬底101内(即靠近半导体衬底101的顶面的位置)。
如图1所示,在一些实施例中,高压半导体装置100包含第一阱102。第一阱102设置于半导体衬底101上。在本实施例中,第一阱102为P型。第一阱102具有水平宽度w1。在一些实施例中,水平宽度w1在约4μm至约6μm的范围内。在一些实施例中,第一阱102的掺杂浓度在约1x1015atoms/cm3至约5x1017atoms/cm3的范围内。在一些实施例中,第一阱102通过离子注入工艺和热驱入(drive in)工艺形成。在一些其他实施例中,在高压半导体装置100包含外延层121的情况下,高压半导体装置100可不包含第一阱102,外延层121可具有与第一阱102类似的功用并占据第一阱102的位置。
在一些实施例中,高压半导体装置100包含第二阱103。第二阱103设置于半导体衬底101上,且与第一阱102相邻。在本实施例中,第二阱103为N型。在一些实施例中,第二阱103的掺杂浓度在约1x1015atoms/cm3至约5x1017atoms/cm3的范围内。在一些实施例中,第二阱103通过离子注入工艺和热驱入工艺形成。
如图1所示,高压半导体装置100包含第一源极区104和第一漏极区105。第一源极区104和第一漏极区105分别设置于第一阱102和第二阱103中。在本实施例中,第一源极区104和第一漏极区105为N型。在一些实施例中,第一源极区104和第一漏极区105的掺杂浓度高于第一阱102和第二阱103的掺杂浓度。在一些实施例中,第一源极区104和第一漏极区105的掺杂浓度在约1x1019atoms/cm3至约5x1020atoms/cm3的范围内。在一些实施例中,第一源极区104和第一漏极区105通过离子注入工艺形成。
如图1所示,高压半导体装置100包含第一栅极结构106。第一栅极结构106设置于外延层121上,且第一栅极结构106设置于第一阱102和第二阱103上。在一些实施例中,第一栅极结构106包含栅极介电层(未显示)以及设置于其上的栅极电极(未显示)。在一些实施例中,可先依序毯覆性沉积介电材料层(用以形成栅极介电层)及位于其上的导电材料层(用以形成栅极电极)于半导体衬底101上,再藉由光刻工艺与刻蚀工艺将介电材料层及导电材料层分别图案化以形成包含栅极介电层及栅极电极的第一栅极结构106。
在一些实施例中,上述介电材料层的材料(即栅极介电层的材料)可包含氧化硅、氮化硅、氮氧化硅、高介电常数(high-k)的介电材料、前述的组合或其它合适的介电材料。一些实施例中,介电材料层可通过化学气相沉积(chemical vapor deposition,CVD)或旋转涂布(spin coating)形成。上述导电材料层的材料(即栅极电极的材料)可为非晶硅、多晶硅、一或多种金属、金属氮化物、导电金属氧化物、前述的组合或其他合适的导电材料。导电材料层可通过化学气相沉积法(CVD)、溅射(sputtering)、电阻加热蒸镀法、电子束蒸镀法、或其它合适的沉积方式形成。另外,第一栅极结构106可包含设置于第一栅极结构106的两侧侧壁上的绝缘间隙物(未显示)。
如图1所示,在一些实施例中,高压半导体装置100包含埋置(buried)层107。埋置层107设置于半导体衬底101中。在一些实施例中,埋置层107与第一阱102和第二阱103重叠。也就是说,在一些实施例中,埋置层107延伸进入外延层121中的第一阱102和第二阱103中。埋置层107具有水平宽度w2。在一些实施例中,埋置层107的水平宽度w2大于第一阱102的水平宽度w1。在一些实施例中,水平宽度w2在约7μm至约15μm的范围内。在本实施例中,埋置层107为P型。在一些实施例中,埋置层107的掺杂浓度在约1x1016atoms/cm3至约1x1019atoms/cm3的范围内。
在一些实施例中,可在形成第一阱102和第二阱103之后,通过离子注入工艺将P型掺质(例如硼(B))注入半导体衬底101、第一阱102和第二阱103中来形成埋置层107。在一些其他实施例中,可在形成第一阱102和第二阱103之前,通过离子注入工艺将P型掺质(例如硼(B))注入半导体衬底101中来形成埋置层107。
如图1所示,在一些实施例中,高压半导体装置100包含第三阱108。第三阱108设置于半导体衬底101上,且与第一阱102相邻。在本实施例中,第二阱103和第三阱108位于第一阱102的两侧。在本实施例中,第三阱108为N型。在一些实施例中,第三阱108的掺杂浓度在约1x1015atoms/cm3至约5x1017atoms/cm3的范围内。在一些实施例中,第三阱108通过离子注入工艺和热驱入工艺形成。
在一些实施例中,高压半导体装置100包含第二源极区109和第二漏极区110。第二源极区109和第二漏极区110分别设置于第一阱102和第三阱108中。在本实施例中,第二源极区109和第二漏极区110为N型。在一些实施例中,第二源极区109和第二漏极区110的掺杂浓度高于第一阱102和第三阱108的掺杂浓度。在一些实施例中,第二源极区109和第二漏极区110的掺杂浓度在约1x1019atoms/cm3至约5x1020atoms/cm3的范围内。在一些实施例中,第二源极区109和第二漏极区110通过离子注入工艺形成。
如图1所示,高压半导体装置100包含第二栅极结构111。第二栅极结构111设置于外延层121上,且第二栅极结构111设置于第一阱102和第三阱108上。在一些实施例中,第二栅极结构111包含栅极介电层(未显示)以及设置于其上的栅极电极(未显示)。在一些实施例中,可先依序毯覆性沉积介电材料层(用以形成栅极介电层)及位于其上的导电材料层(用以形成栅极电极)于半导体衬底101上,再藉由光刻工艺与刻蚀工艺将介电材料层及导电材料层分别图案化以形成包含栅极介电层及栅极电极的第二栅极结构111。
在一些实施例中,埋置层107与第一阱102、第二阱103和第三阱108重叠。也就是说,在一些实施例中,埋置层107延伸进入外延层121中的第一阱102、第二阱103和第三阱108中。在一些实施例中,埋置层107位于第一源极区104和第二源极区109的正下方。也就是说,埋置层107与第一源极区104和第二源极区109垂直重叠。
通过埋置层107的设置,可大幅加宽第二阱103的掺杂轮廓与第三阱108的掺杂轮廓之间的距离,因此降低电荷从第二阱103打穿(punch)至第三阱108的情形,也可降低电荷从第三阱108打穿(punch)至第二阱103的情形,进而减少漏电流(leakage)。因此,具有埋置层107的高压半导体装置100可达到高击穿电压(breakdown voltage,bv)。也就是说,埋置层107改善高压半导体装置100的耐压能力。在一些实施例中,通过埋置层107的设置,高压半导体装置100的击穿电压约为98V。再者,在一些实施例中,随着埋置层107的水平宽度逐渐增加(例如从7μm增加至10μm),高压半导体装置100的击穿电压也逐渐增加(例如从70V增加至98V)。
另一方面,在未设置埋置层107的情况下,第二阱103的掺杂轮廓较靠近第三阱108的掺杂轮廓,电荷较容易从第二阱103打穿至第三阱108,电荷也较容易从第三阱108打穿至第二阱103,因此较容易有漏电流,且击穿电压较低。在一些实施例中,在未设置埋置层107的情况下,半导体装置的击穿电压约为4V。由此可见,通过设置埋置层107,半导体装置的击穿电压可从约4V提升至约98V。后续将以图式说明半导体装置是否有设置埋置层所造成的区别。
再者,由于埋置层107埋置于半导体衬底101中并远离高压半导体装置100的顶表面,因此埋置层107可不影响表面电场,进而不影响高压半导体装置100的阈值电压(threshold voltage,Vth)。
由于埋置层107的设置可降低电荷在阱之间打穿,因此在第一漏极区105和第二漏极区110施加不同的电压时,可避免装置失效的情形发生。在一些实施例中,可在第一漏极区105施加电压40V,并在第二漏极区110施加电压80V。
再者,在第一漏极区105和第二漏极区110施加不同的电压时,更进一步地,为了避免装置失效,可同时于第一栅极结构106和第二栅极结构111施加不同的电压,以在不同沟道有不同的饱和电流,使得元件应用更具有弹性。
在一些实施例中,高压半导体装置100包含第一隔离结构112和第二隔离结构113。第一隔离结构112设置于第二阱103上,且第一栅极结构106的一部分延伸至第一隔离结构112上。第二隔离结构113设置于第三阱108上,且第二栅极结构111的一部分延伸至第二隔离结构113上。在一些实施例中,第一隔离结构112的一部分埋置于第二阱103中。在一些实施例中,第二隔离结构113的一部分埋置于第三阱108中。在一些实施例中,第一隔离结构112和第二隔离结构113由氧化硅制成,且为藉由热氧化法所形成的硅局部氧化(localoxidation of silicon,LOCOS)隔离结构。
在一些实施例中,高压半导体装置100包含第一漂移(drift)区114和第二漂移区115。第一漂移区114围绕第一漏极区105,且第一漂移区114的一部分与第一隔离结构112重叠。第二漂移区115围绕第二漏极区110,且第二漂移区115的一部分与第二隔离结构113重叠。在本实施例中,第一漂移区114和第二漂移区115为N型。在一些实施例中,第一漂移区114和第二漂移区115的掺杂浓度在约5x1016atoms/cm3至约5x1018atoms/cm3的范围内。在一些实施例中,第一漂移区114和第二漂移区115通过离子注入工艺形成。
通过第一漂移区114和第二漂移区115分别围绕第一漏极区105和第二漏极区110,可增加区的大小,进而达到降低表面电场(reduced surface field,RESURF)的效果,并提升装置的击穿电压。
在一些实施例中,高压半导体装置100包含重掺杂区116。重掺杂区116设置于第一阱102中,且位于第一源极区104与第二源极区109之间。在本实施例中,重掺杂区116为P型。在一些实施例中,重掺杂区116的掺杂浓度在约1x1019atoms/cm3至约5x1020atoms/cm3的范围内。在一些实施例中,重掺杂区116通过离子注入工艺形成。
在一些实施例中,高压半导体装置100包含基体(body)区117。基体区117设置于第一阱102中,并围绕第一源极区104、第二源极区109和重掺杂区116。在一些实施例中,第一栅极结构106覆盖基体区117的一部分,第二栅极结构111覆盖基体区117的另一部分。在本实施例中,基体区117为P型。在一些实施例中,基体区117的掺杂浓度在约5x1016atoms/cm3至约5x1018atoms/cm3的范围内。在一些实施例中,基体区117通过离子注入工艺形成。
请参照图2,其显示出依据本发明的一些实施例的高压半导体装置100的上视图。图1是沿图2的线a-a’的剖面示意图。如图2所示,在一些实施例中,埋置层107的一部分在第二阱103与第三阱108之间的第一阱102中,且埋置层107的一部分延伸进入第二阱103和第三阱108。在本实施例中,埋置层107的边界可超出第二阱103的边界和第三阱108的边界,但是埋置层107的边界不超出第一阱102的边界。也就是说,从上视图来看,埋置层107具有突出部分延伸超出第二阱103和第三阱108。在一些实施例中,埋置层107的突出部分具有宽度w3。在一些实施例中,宽度w3大于约2μm。在一些其他实施例中,埋置层107的一部分在第二阱103与第三阱108之间的第一阱102中,且埋置层107的边界不超出第一阱102的边界、第二阱103的边界和第三阱108的边界。
从上视图来看,通过埋置层107具有突出部分延伸超出第二阱103和第三阱108,可更进一步降低电荷从第二阱103打穿至第三阱108的情形,也可降低电荷从第三阱108打穿至第二阱103的情形,因此更进一步减少漏电流,并提升装置的击穿电压。
如图2所示,在一些实施例中,高压半导体装置100更包含第四阱118。第一阱102在第二阱103与第四阱118之间,且第一阱102在第三阱108与第四阱118之间。也就是说,第一阱102将第二阱103、第三阱108和第四阱118彼此隔开。在本实施例中,第四阱118为N型。在一些实施例中,第四阱118的掺杂浓度在约1x1015atoms/cm3至约5x1017atoms/cm3的范围内。在一些实施例中,第四阱118通过离子注入工艺和热驱入工艺形成。
可以理解的是,第四阱118上方也具有栅极结构、隔离结构、漏极区和漂移区,这些元件的工艺和材料相同或相似于第一栅极结构106、第一隔离结构112、第一漏极区105和第一漂移区114,在此便不重复叙述。
如图2所示,在一些实施例中,埋置层107的一部分在第二阱103与第四阱118之间的第一阱102中,且埋置层107的一部分延伸进入第二阱103和第四阱118。在一些实施例中,埋置层107的一部分在第三阱108与第四阱118之间的第一阱102中,且埋置层107的一部分延伸进入第三阱108和第四阱118。在一些实施例中,埋置层107的边界可超出第二阱103的边界和第四阱118的边界,但是埋置层107的边界不超出第一阱102的边界。在一些实施例中,埋置层107的边界可超出第三阱108的边界和第四阱118的边界,但是埋置层107的边界不超出第一阱102的边界。也就是说,从上视图来看,埋置层107具有突出部分延伸超出第二阱103和第四阱118,且埋置层107具有突出部分延伸超出第三阱108和第四阱118。在本实施例中,从上视图来看,埋置层107为T形。可以理解的是,图2中埋置层107从上视图来看的形状仅作为范例说明,并不限定于此,埋置层107从上视图来看的形状取决于设计需求。
请参照图3,其显示出依据本发明的一些实施例的高压半导体装置200的剖面示意图,其中相同于图1中的部件是使用相同的标号并省略其说明。
图3中的高压半导体装置200的结构类似于图1中的高压半导体装置100的结构,差异处在于高压半导体装置200的埋置层207包含多个区段,且这些区段彼此隔开。在本实施例中,埋置层207的多个区段为矩形,经过后续热处理工艺后,这些多个区段会连接在一起。如图3所示,将埋置层207的多个区段连接在一起的部分的宽度小于这些区段的宽度,进一步地说,埋置层207连接在一起的部分形成波浪状。可以理解的是,图3中埋置层207的多个区段的形状仅作为范例说明,并不限定于此,埋置层207的多个区段的形状取决于设计需求。
请参照图4,其显示出依据本发明的一些实施例的高压半导体装置300的剖面示意图,其中相同于图1中的部件是使用相同的标号并省略其说明。
图4中的高压半导体装置300的结构类似于图1中的高压半导体装置100的结构,差异处在于高压半导体装置300的埋置层307的厚度沿着第一阱102往第二阱103的方向减少,且埋置层307的厚度沿着第一阱102往第三阱108的方向减少。埋置层307具有水平宽度w2。在一些实施例中,水平宽度w2在约7μm至约15μm的范围内。
请参照图5-图6,其显示依据本发明的一些实施例的高压半导体装置的掺杂轮廓示意图。图5的高压半导体装置与图6的高压半导体装置之间的差异在于是否具有埋置层。如图5所示,在一些实施例中,高压半导体装置不具有埋置层,第二阱103与第三阱108之间具有上部距离wA和下部距离wB,其中下部距离wB为第二阱103与第三阱108之间的最短直线距离。如图6所示,在本实施例中,高压半导体装置具有埋置层,第二阱103与第三阱108之间具有上部距离wA’和下部距离wB’,其中上部距离wA’和下部距离wB’距离半导体装置的顶表面的深度分别与上部距离wA和下部距离wB距离半导体装置的顶表面的深度相同。如图5-图6所示,上部距离wA’大于上部距离wA,且下部距离wB’大于下部距离wB。也就是说,通过埋置层的设置,可加宽第二阱103与第三阱108之间的距离,且扩大在第二阱103与第三阱108之间的第一阱102(或外延层121)的掺杂轮廓。
根据本发明的一些实施例,高压半导体装置通过埋置层的设置,可大幅加宽相邻阱的掺杂轮廓之间的距离,因此降低电荷在阱之间打穿,进而减少漏电流。因此,具有埋置层的高压半导体装置可达到高击穿电压,也就是说,埋置层改善高压半导体装置的耐压能力。再者,由于埋置层的设置可降低电荷在阱之间打穿,因此在相邻两漏极区施加不同的电压时,可减少装置失效的情形发生。再者,由于埋置层埋置于半导体衬底中并远离高压半导体装置的顶表面,因此埋置层不影响表面电场,进而不影响高压半导体装置的阈值电压。
此外,根据本发明的一些实施例,从上视图来看高压半导体装置,通过埋置层具有突出部分延伸超出相邻的两个阱,可更进一步降低电荷在阱之间打穿,因此更进一步减少漏电流,并提升装置的击穿电压,使装置具有较高的品质因数(figure of merit,FOM)。
以上概述数个实施例,以便本领域技术人员可以更理解本发明实施例的观点。本领域技术人员应该理解,他们能以本发明实施例为基础,设计或修改其他工艺和结构,以达到与在此介绍的实施例相同的目的及/或优势。本领域技术人员也应该理解到,此类等效的工艺和结构并无悖离本发明的精神与范围,且他们能在不违背本发明的精神和范围之下,做各式各样的改变、取代和替换。

Claims (12)

1.一种高压半导体装置,其特征在于,包括:
一半导体衬底,具有一第一导电型;
一第一阱,设置于该半导体衬底上,其中该第一阱具有该第一导电型;
一第二阱,与该第一阱相邻,其中该第二阱具有与该第一导电型相反的一第二导电型;
一第一源极区和一第一漏极区,分别设置于该第一阱和该第二阱中,其中该第一源极区和该第一漏极区具有该第二导电型,且对该第一漏极区施加一第一电压;
一第一栅极结构,设置于该第一阱和该第二阱上;
一第三阱,设置于该半导体衬底上,且与该第一阱相邻,其中该第三阱具有该第二导电型;
一第二源极区和一第二漏极区,分别设置于该第一阱和该第三阱中,其中该第二源极区和该第二漏极区具有该第二导电型,且对该第二漏极区施加一第二电压,该第二电压不同于该第一电压;
一第二栅极结构,设置于该第一阱和该第三阱上;以及
一埋置层,设置于该半导体衬底中且具有该第一导电型,其中该埋置层与该第一阱、该第二阱和该第三阱重叠,且该埋置层位于该第一源极区下方,其中该埋置层的边界超出该第二阱的边界,且该第二阱的该边界远离该第一阱。
2.如权利要求1所述的高压半导体装置,其特征在于,更包括:
一第一隔离结构,设置于该第二阱上,其中该第一栅极结构延伸至该第一隔离结构上;
一第二隔离结构,设置于该第三阱上,其中该第二栅极结构延伸至该第二隔离结构上;以及
一第一漂移区,围绕该第一漏极区且具有该第二导电型。
3.如权利要求1所述的高压半导体装置,其特征在于,更包括:
一第二漂移区,围绕该第二漏极区且具有该第二导电型。
4.如权利要求1所述的高压半导体装置,其特征在于,更包括:
一重掺杂区,与该第一源极区相邻并具有该第一导电型;以及
一基体区,围绕该第一源极区和该重掺杂区,并具有该第一导电型。
5.如权利要求1所述的高压半导体装置,其特征在于,更包括:
一重掺杂区,设置于该第一源极区与该第二源极区之间,并具有该第一导电型;以及
一基体区,围绕该第一源极区、该第二源极区和该重掺杂区,并具有该第一导电型。
6.如权利要求1所述的高压半导体装置,其特征在于,该埋置层包括多个区段,所述多个区段彼此隔开。
7.如权利要求1所述的高压半导体装置,其特征在于,该埋置层的厚度沿着该第一阱往该第二阱的一第一方向减少,且该埋置层的厚度沿着该第一阱往该第三阱的一第二方向减少。
8.一种高压半导体装置,其特征在于,包括:
一半导体衬底,具有一第一导电型;
一第一阱,设置于该半导体衬底上,其中该第一阱具有该第一导电型;
一第二阱和一第三阱,设置于该半导体衬底上,且位于该第一阱的两侧,其中该第二阱和该第三阱具有与该第一导电型相反的一第二导电型;
一第一源极区和一第一漏极区,分别设置于该第一阱和该第二阱中,其中该第一源极区和该第一漏极区具有该第二导电型;
一第二源极区和一第二漏极区,分别设置于该第一阱和该第三阱中,其中该第二源极区和该第二漏极区具有该第二导电型;
一第一栅极结构,设置于该第一阱和该第二阱上;
一第二栅极结构,设置于该第一阱和该第三阱上;以及
一埋置层,设置于该半导体衬底中,且与该第一源极区和该第二源极区垂直重叠,其中该埋置层具有该第一导电型,其中在该第一漏极区和该第二漏极区施加不同的电压。
9.如权利要求8所述的高压半导体装置,其特征在于,该埋置层的水平宽度大于该第一阱的水平宽度。
10.如权利要求8所述的高压半导体装置,其特征在于,该埋置层与该第一阱、该第二阱和该第三阱重叠。
11.如权利要求10所述的高压半导体装置,其特征在于,从上视图来看,该埋置层具有一突出部分延伸超出该第二阱和该第三阱。
12.如权利要求8所述的高压半导体装置,其特征在于,更包括:
一第一隔离结构,设置于该第二阱上,其中该第一栅极结构延伸至该第一隔离结构上;以及
一第二隔离结构,设置于该第三阱上,其中该第二栅极结构延伸至该第二隔离结构上。
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