CN111157877B - Off-state load open circuit detection circuit - Google Patents
Off-state load open circuit detection circuit Download PDFInfo
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- CN111157877B CN111157877B CN201911422481.4A CN201911422481A CN111157877B CN 111157877 B CN111157877 B CN 111157877B CN 201911422481 A CN201911422481 A CN 201911422481A CN 111157877 B CN111157877 B CN 111157877B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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Abstract
The invention discloses an off-state load on-off detection circuit, which comprises a switch module, a load on-off judgment module and a control module, wherein the switch module is connected to a load circuit to be detected and supplies current to the load circuit to be detected; the load on-off judging module is connected to the load circuit to be detected and used for receiving the load voltage from the load circuit to be detected and generating a voltage judging signal according to the load voltage; the control module is connected to the load on-off judgment module and the switch module and used for judging whether the load circuit to be tested is in an open circuit or not according to the voltage judgment signal and controlling the switch module to be in an off state continuously when the load circuit to be tested is in the open circuit. The off-state load disconnection detection circuit can identify whether the load circuit is disconnected or not under the condition that the power tube is disconnected, and controls the power tube to be kept disconnected when the load circuit is disconnected so as to prevent damage to a chip circuit.
Description
Technical Field
The invention belongs to the technical field of detection circuits, and particularly relates to an off-state load break detection circuit.
Background
The high-side power driving chip is used for providing output current for a load to the ground, the internal logic circuit of the chip controls the power tube to be turned on, and the internal power tube of the chip provides current for the load to the ground. In order to know the working state of the load circuit, whether the load circuit is broken or not needs to be detected under the condition that the power tube is turned off. When the power tube of the chip is in the off state and the load is in an open circuit due to misoperation or other reasons, the error state needs to be reported to the logic control circuit, and the power tube is closed through the logic control circuit. The circuit for realizing the part of functions is an off-state load open circuit detection circuit.
Referring to fig. 1, fig. 1 is a circuit diagram of an off-state load break detection circuit in the prior art. The existing off-state load break detection circuit mostly adopts a high-voltage shaping circuit to carry a voltage VoutSampling is performed. As shown in the figure, the power tube NM is connected to the load circuit for turning on the load circuit in the normal operation process, and if the power tube NM is in the off state, the load RloadWhen the connection is normal, the load voltage V isoutIs low level; if the power tube NM is in the off state and the load R isloadIn the off state, the load voltage VoutIs high. The shaping circuit is able to recognize a high level of the load voltage and output an open-circuit state signal to the logic circuit, which then locks the power transistor NM in an off-state to avoid the load RloadWhen the power tube NM is turned on again, the power tube NM is in an off state, and other devices of the chip are damaged.
However, in the load circuit open state, the load voltage VoutClose to the larger supply voltage VhighWhen V ishighWhen the voltage works in a wide range, the voltage-resistant shaping circuit can damage a rear-stage shaping unit, the requirement on the voltage resistance of the rear-stage shaping unit is high, and the shaping circuit is a high-voltage circuit, so that the occupied layout area is large.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an off-state load open circuit detection circuit. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides an off-state load open-circuit detection circuit, which comprises a switch module, a load open-circuit judgment module and a control module, wherein,
the switch module is connected to the load circuit to be tested and used for controlling the current to be supplied to the load circuit to be tested;
the load on-off judging module is connected to the load circuit to be detected and used for receiving load voltage from the load circuit to be detected and generating a voltage judging signal according to the load voltage;
the control module is connected to the load on-off judgment module and the switch module, and is used for judging whether the load circuit to be tested is in an open circuit according to the voltage judgment signal and controlling the switch module to be in an off state continuously when the load circuit to be tested is in the open circuit.
In an embodiment of the present invention, the switch module includes a first NMOS transistor, a drain of the first NMOS transistor is connected to an input terminal of a first power voltage, a source of the first NMOS transistor is connected to the load circuit to be tested, and a gate of the first NMOS transistor is connected to the control module;
the first NMOS tube is in a turn-off state in a load break detection process, and is continuously in the turn-off state according to a control signal from the control module when the load circuit to be detected is judged to be broken.
In an embodiment of the present invention, the load on/off determining module includes a first high-resistance unit, a diode, a second NMOS transistor, and a second high-resistance unit,
the first end of the first high-resistance unit is connected to the input end of the first power voltage, the second end of the first high-resistance unit is connected to the input end of the diode, the drain electrode of the second NMOS tube is connected to the output end of the diode, the grid electrode of the second NMOS tube is connected to the input end of the second power voltage, and the second high-resistance unit is connected between the source electrode of the second NMOS tube and the ground end;
and the source electrodes of the load circuit to be tested and the first NMOS tube are connected to the input end of the diode.
In one embodiment of the invention, the first supply voltage is greater than the second supply voltage.
In one embodiment of the invention, the supply voltage range of the first supply voltage is 4V-100V, and the supply voltage range of the second supply voltage is 3V-5.5V.
In one embodiment of the present invention, the first high resistance unit and the second high resistance unit are both resistors.
In an embodiment of the present invention, the resistances of the first high resistance unit and the second high resistance unit are both higher than 500 kilo-ohms.
In one embodiment of the invention, the control module comprises a shaping unit and a logic unit, wherein,
the shaping unit is connected to a source electrode of the second NMOS tube and used for converting the voltage judgment signal generated by the load on-off judgment module into a digital judgment signal;
the logic unit is connected to the shaping unit and used for judging the on-off state of the load circuit to be detected according to the digital judgment signal and controlling the first NMOS tube to be in the off state continuously when the on-off state of the load circuit to be detected is judged and judged.
In an embodiment of the present invention, the logic unit is further connected to an input end of a power tube control signal, and is configured to control the switching module to be turned on and off during a normal operation of the load circuit to be tested.
In an embodiment of the present invention, the control module further includes a driving unit, an input end of the driving unit is connected to an output end of the logic unit, and an output end of the driving unit is connected to the gate of the first NMOS transistor; the driving unit is used for driving the first NMOS tube to be in a turn-off state continuously when the load circuit to be tested is broken according to the control signal from the logic unit.
Compared with the prior art, the invention has the beneficial effects that:
1. the off-state load disconnection detection circuit can identify whether the load circuit is disconnected or not under the condition that the power tube is disconnected, and controls the power tube to be kept disconnected when the load circuit is disconnected so as to prevent damage to a chip circuit.
2. The shaping unit in the off-state load open circuit detection circuit is a low-voltage circuit, so that the layout area is greatly reduced, and the reliability of the circuit is improved.
3. The off-state load break detection circuit can control the power tube to be kept disconnected when the load circuit is broken, effectively avoids the circuit no-load condition and improves the circuit output efficiency.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a circuit diagram of an off-state load break detection circuit of the prior art;
FIG. 2 is a block diagram of an off-state load break detection circuit according to an embodiment of the present invention;
fig. 3 is a circuit diagram of an off-state load break detection circuit according to an embodiment of the present invention;
fig. 4 is a schematic current flow diagram of an off-state load disconnection detection circuit provided in an embodiment of the present invention when a load circuit to be detected is connected normally;
fig. 5 is a schematic current flow diagram of an off-state load break detection circuit according to an embodiment of the present invention when a load circuit to be tested is broken.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, a detailed description is provided below with reference to the accompanying drawings and the detailed description of the present invention for an off-state load break detection circuit according to the present invention.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.
Referring to fig. 2, fig. 2 is a block diagram of an off-state load break detection circuit according to an embodiment of the present invention. The off-state load break detection circuit comprises a switch module 101, a load on-off judgment module 102 and a control module 103. The off-state load disconnection detection circuit is used for detecting whether the load circuit is disconnected or not when the switch module 101 is in a disconnected state, and controlling the switch module 101 to be continuously in the disconnected state when the load circuit is detected to be disconnected, so that damage to a subsequent circuit caused by high voltage is avoided.
Further, the switch module 101 is connected to the load circuit 104 to be tested, and is configured to control on/off of the load circuit 104 to be tested; the load on-off determining module 102 is connected to the load circuit 104 to be tested, and is configured to receive a load voltage V from the load circuit 104 to be testedoutAnd according to the load voltage VoutGenerating a voltage judgment signal; the control module 103 is connected to the load on-off judging module 102 and the switch module 101, and is configured to judge whether the load circuit 104 to be tested is open according to the voltage judging signal, and control the switch module 101 to be continuously in an off state when the load circuit 104 to be tested is open.
Further, referring to fig. 3, fig. 3 is a circuit diagram of an off-state load disconnection detection circuit according to an embodiment of the present invention. The switch module 101 of this embodiment is a first NMOS transistor N1, which is used as a switch to control the on/off of the load circuit. Specifically, the drain of the first NMOS transistor N1 is connected to a first power voltage VhighThe source is connected to the load circuit 104 to be tested, and the gate is connected to the control module 103; the first NMOS transistor N1 is in an off state during the load break detection process, and continues to be in the off state according to the control signal from the control module 103 when it is determined that the load circuit 104 to be tested is broken.
Specifically, the first NMOS transistor N1 is used as a switch transistor for connecting the load circuit to be tested to the first power voltage VhighTo energize the load circuit to be tested. It should be noted that, during the normal operation of the load circuit, the gate of the first NMOS transistor N1 is connected to the power transistor control signal VinThe input terminal of the circuit is used for controlling the on-off of the switch module 101 in the normal working process of the load circuit 104 to be tested, and the open-state load break detection circuit of the embodiment is used for detecting whether a break occurs in the load circuit to be tested when the first NMOS transistor N1 is broken.
Further, the load on/off determination module 102 includes a first high impedance unit 1021, a diode D1, a second NMOS transistor N2, and a second high impedance unit 1022, wherein a first end of the first high impedance unit 1021 is connected to a first power voltage VhighA second terminal of the second NMOS transistor N2 is connected to an input terminal of the diode D1, a drain of the second NMOS transistor N2 is connected to an output terminal of the diode D1, and a gate of the second NMOS transistor N2 is connected to a second power voltage VlowThe second high impedance unit 1022 is connected between the source of the second NMOS transistor N2 and the ground GND; the sources of the load circuit 104 to be tested and the first NMOS transistor N1 are both connected to the input terminal of the diode D1.
In the present embodiment, the first power supply voltage VhighGreater than the second supply voltage Vlow. Preferably, the first supply voltage VhighIs in the range of 4V-100V, and a second power supply voltage VlowThe supply voltage range of (2) is 3V-5.5V.
Further, the first high impedance unit 1021 and the second high impedance unit 1022 mainly function to provide a large resistance value to obtain a large voltage drop. In the present embodiment, the first high resistance unit 1021 and the second high resistance unit 1022 are both resistors. Preferably, the resistances of the first high impedance unit 1021 and the second high impedance unit 1022 are both higher than 500 kilo-ohms. However, in other embodiments, the first high impedance unit 1021 and the second high impedance unit 1022 may also select other high impedance devices, such as using MOS device body resistance and the like.
The second NMOS transistor N2 is used as a linear switch for controlling the voltage at point B not higher than the second power voltage VlowWhen the voltage at point B is higher than the second power supply voltage VlowAt this time, the second NMOS transistor N2 is turned off.
Further, the control module 103 includes a shaping unit 1031 and a logic unit 1032, wherein the shaping unit 1031 is connected to the source of the second NMOS transistor N2 and is configured to convert the voltage determination signal generated by the load on-off determination module 102 into a digital determination signal; the logic unit 1032 is connected to the shaping unit 1031, and is configured to determine on/off of the load circuit 104 to be tested according to the digital determination signal, and control the first NMOS transistor N1 to be continuously in an off state when it is determined that the load circuit 104 to be tested is open.
The logic unit 1032 is also coupled to the power transistor control signal VinFor controlling the on and off of the switch module 101 during the normal operation of the load circuit 104 to be tested.
In the present embodiment, the shaping unit 1031 further includes a comparison subunit (not shown in the drawing), in which a comparison threshold is set for comparing with the analog determination signal from the load on-off determination module. Specifically, when the analog determination signal is smaller than the comparison threshold, it indicates that the voltage input into the shaping unit 1031 is small, at this time, it indicates that the internal connection of the load circuit 104 to be tested is normal, and the logic unit 1032 controls the normal on and off of the switch module 101 according to the determination result; when the analog determination signal is greater than the comparison threshold, it indicates that the voltage input to the shaping unit 1031 is large, and at this time, it indicates that a circuit break phenomenon occurs inside the load circuit 104 to be tested, and the logic unit 1032 controls the switch module 101 to maintain the off state according to the determination result. The comparison threshold is preset, and a user can set and adjust the comparison threshold according to actual requirements and experience.
Further, the control module 103 further includes a driving unit 1033, an input terminal of the driving unit 1033 is connected to the output terminal of the logic unit 1032, and an output terminal of the driving unit 1033 is connected to the gate of the first NMOS transistor N1; the driving unit 1033 is configured to drive the first NMOS transistor N1 to be continuously in an off state when the load circuit 104 to be tested is disconnected according to the control signal from the logic unit 1032.
Specifically, referring to fig. 4 and fig. 5, fig. 4 is a schematic current flow diagram of an on-state load disconnection detection circuit provided in an embodiment of the present invention when a load circuit to be detected is connected normally; fig. 5 is a schematic current flow diagram of an open load disconnection detection circuit according to an embodiment of the present invention when a load circuit to be tested is disconnected.
As shown in FIG. 4, the first power voltage VhighIs a high voltage, a second supply voltage VlowIs a low voltage. In the open-state load break detection circuit of the present embodiment, the first high-resistance unit is used to collect the load voltage V from the load circuit 104 to be testedout. During the test, the first NMOS transistor N1 is in an off state, i.e., an off state. At this time, if the load circuit (in the drawing, R is used)loadRepresenting a load) is normally connected, Ibias＝IA+Id，Iload>>Id，IA＝Iload，IdThe current is small, so the voltage V at point BBAnd if the voltage signal is smaller, the generated voltage signal is processed by the shaping unit, and is compared with a set comparison threshold value in the comparison subunit, and the comparison threshold value is smaller than the comparison threshold value, so that the internal connection of the load circuit is judged to be normal. Then, the logic unit 1032 controls the first NMOS transistor N1 to operate normally according to the determination result, i.e. according to the power transistor control signal VinControls the on/off of the first NMOS transistor N1.
As shown in fig. 5, the first NMOS transistor N1 is also in the off state, if the load circuit (denoted by R in the figure) is in the on stateloadRepresenting a load) has an internal open circuit, Id＝Ibias+IA，IdThe voltage V at the point B is larger when the current is largerBIf the voltage signal is larger, the generated voltage signal is processed by the shaping unit, compared with a set comparison threshold in the comparison subunit, and is larger than the comparison threshold, so that the condition that the inside of the load circuit is broken is judged, and the signal is input to the logic unit 1032. The logic unit 1032 controls the gate of the first NMOS transistor N1 via the driving unit 1033, so that the control signal V is no matter what the power transistor isinWhen any signal is input, the first NMOS transistor N1 is always in the off state.
Further, since the second NMOS transistor N2 is an NMOS transistor, and the gate is electrically connectedPressure is VlowWhen V isB>Vlow-VthTime (V)thThreshold of the second NMOS transistor N2), the second NMOS transistor N2 is turned off, and the diode D1 guarantees VBVoltage not higher than VoutVoltage, hence VB<VlowThereby avoiding the risk of high voltage input of the latter shaping unit.
The off-state load break detection circuit can identify whether the load circuit is broken or not under the condition that the power tube is turned off, and controls the power tube to be kept turned off when the load circuit is broken, so that damage to a chip circuit is prevented, and the output efficiency of a chip is effectively improved. The shaping unit in the off-state load break detection circuit of the embodiment is a low-voltage circuit, so that the layout area is greatly reduced, and the reliability of the circuit is improved. In addition, the off-state load break detection circuit of the embodiment can control the power tube to keep off when the load circuit is broken, effectively avoids the circuit no-load condition, and improves the circuit output efficiency.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. An off-state load break detection circuit is characterized by comprising a switch module (101), a load break judgment module (102) and a control module (103), wherein,
the switch module (101) is connected to the load circuit (104) to be tested and used for providing current for the load circuit (104) to be tested;
the load on-off judging module (102) is connected to the load circuit (104) to be tested and is used for receiving the load voltage (V) from the load circuit (104) to be testedout) And according to the load voltage (V)out) Generating a voltage judgment signal;
the control module (103) is connected to the load on-off judgment module (102) and the switch module (101), and is used for judging whether the load circuit (104) to be tested is in an open circuit according to the voltage judgment signal and controlling the switch module (101) to be in an off state continuously when the load circuit (104) to be tested is in the open circuit;
the switch module (101) comprises a first NMOS transistor (N1), and the drain of the first NMOS transistor (N1) is connected to a first power supply voltage (V)high) The source is connected to the load circuit (104) to be tested, and the gate is connected to the control module (103);
the first NMOS tube (N1) is in an off state in a load break detection process, and is in the off state continuously according to a control signal from the control module (103) when the load circuit (104) to be tested is judged to be broken;
the load on-off judging module (102) comprises a first high-resistance unit (1021), a diode (D1), a second NMOS tube (N2) and a second high-resistance unit (1022), wherein,
a first terminal of the first high impedance unit (1021) is connected to the first supply voltage (V)high) A second terminal of the NMOS transistor (N2) is connected to the input terminal of the diode (D1), a drain of the second NMOS transistor (N2) is connected to the output terminal of the diode (D1), and a gate of the second NMOS transistor (N2) is connected to a second power voltage (V)low) The second high-resistance unit (1022) is connected between the source of the second NMOS transistor (N2) and the Ground (GND);
the sources of the load circuit to be tested (104) and the first NMOS transistor (N1) are connected to the input end of the diode (D1);
the control module (103) comprises a shaping unit (1031) and a logic unit (1032), wherein,
the shaping unit (1031) is connected to the source of the second NMOS transistor (N2) and is configured to convert the voltage determination signal generated by the load on-off determination module (102) into a digital determination signal;
the logic unit (1032) is connected to the shaping unit (1031) and configured to determine, according to the digital determination signal, whether the load circuit (104) to be tested is on or off, and control the first NMOS transistor (N1) to be continuously in an off state when the load circuit (104) to be tested is determined to be off.
2. The off-load disconnection detection circuit of claim 1, wherein the first power supply voltage (V)high) Greater than the second supply voltage (V)low)。
3. The off-load disconnection detection circuit of claim 1, wherein the first power supply voltage (V)high) Is in the range of 4V-100V, the second supply voltage (V)low) The supply voltage range of (2) is 3V-5.5V.
4. The off-state load break detection circuit according to claim 1, wherein the first high impedance unit (1021) and the second high impedance unit (1022) are both resistors.
5. The off-state load break detection circuit according to claim 1, wherein the resistances of the first high impedance unit (1021) and the second high impedance unit (1022) are both higher than 500 kohms.
6. The off-load detection circuit according to claim 5, wherein the logic unit (1032) is further connected to a power transistor control signal (V ™)in) The input end of the switch module (101) is used for controlling the on and off of the switch module (101) in the normal working process of the load circuit (104) to be tested.
7. The off-state loadbreak detection circuit according to claim 6, wherein the control module (103) further comprises a driving unit (1033), wherein an input terminal of the driving unit (1033) is connected to the output terminal of the logic unit (1032), and an output terminal of the driving unit (1033) is connected to the gate of the first NMOS transistor (N1); the driving unit (1033) is used for driving the first NMOS tube (N1) to be in an off state continuously when the load circuit to be tested (104) is disconnected according to the control signal from the logic unit (1032).
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| CN114243830A (en) * | 2021-12-14 | 2022-03-25 | 东莞新能安科技有限公司 | Identification circuit, battery management system, battery pack and electronic device |
| CN116742840A (en) * | 2022-03-04 | 2023-09-12 | 佛山市顺德区美的电子科技有限公司 | Circuit protection method, device, related equipment and medium |
| CN116660716B (en) * | 2022-06-21 | 2024-06-28 | 上海微创惟美医疗科技(集团)有限公司 | No-load detection method and circuit |
| CN118033381B (en) * | 2024-04-08 | 2024-07-12 | 中国科学院半导体研究所 | Chip load detection method and circuit |
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