CN111133559A - Method for manufacturing silicon wafer - Google Patents

Method for manufacturing silicon wafer Download PDF

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CN111133559A
CN111133559A CN201880046189.4A CN201880046189A CN111133559A CN 111133559 A CN111133559 A CN 111133559A CN 201880046189 A CN201880046189 A CN 201880046189A CN 111133559 A CN111133559 A CN 111133559A
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silicon wafer
amount
thickness
wafer
warpage
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CN111133559B (en
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高奉均
小野敏昭
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Sumco Corp
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Sumco Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/4926—Bases or plates or solder therefor characterised by the materials the materials containing semiconductor material
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

In order to reduce the warpage of a wafer generated in a device process, a target thickness required for ensuring an improved amount of warpage of a silicon wafer is determined from a relationship between the amount of warpage and the thickness of the silicon wafer, and a single crystal silicon ingot is processed.

Description

Method for manufacturing silicon wafer
Technical Field
The present invention relates to a method for manufacturing a silicon wafer as a substrate material of a semiconductor device, and more particularly, to a method for manufacturing a silicon wafer suitable as a substrate material of a highly stacked semiconductor device such as a 3-dimensional NAND flash memory (hereinafter referred to as "3 DNAND").
Background
Recently, 3DNAND has received attention. The 3d NAND is a NAND memory in which memory cell arrays are stacked in the vertical direction, and by setting the number of layers (the number of layers of word lines) to 64 layers, for example, a very large storage capacity of 512Gbit (64 GB) can be realized per single die. Further, it is possible to provide a high-performance flash memory which is not increased in the density in the plane direction but increased in the density in the height direction as in the conventional flat NAND memory, and which is improved in the write speed and excellent in power saving as well as in the capacity.
In the manufacture of semiconductor devices, films of various materials such as oxide films, nitride films, and metal films are stacked on silicon wafers to form device structures. Such a laminated film has different film stress due to the film properties and process conditions, and the silicon wafer is bent due to the film stress of the laminated film. In particular, in 3DNAND, each memory element is vertically stacked by several tens or more, and the number of stacked films is also geometrically increased, so that film stress is also greatly increased in proportion to this, and warpage of a silicon wafer is also greatly increased. In the device process, the silicon wafer is greatly bent, and there occurs an abnormal situation such that the treatment in the subsequent processes such as film formation, processing, and inspection cannot be performed.
As for the manufacture of a semiconductor device having 3 or more wiring layers, for example, patent document 1 describes a method for manufacturing a semiconductor device capable of suppressing the warpage of a silicon substrate to a predetermined value or less without depending on a manufacturing apparatus and without using a special interlayer film step. In the manufacturing method, the thickness of the silicon substrate is T (mum), the diameter is D (inch), the number of wiring layers is n, and the thickness is such that T is more than or equal to 62.4 XDx [1.6 (n-1) +1.0]1/2The silicon substrate of (2) to manufacture a semiconductor device.
Patent documents 2 and 3 describe a method for producing an epitaxial silicon wafer having high flatness by forming an epitaxial layer on the surface of a bowl-shaped curved silicon wafer for epitaxial growth, the surface being provided with a concave central portion.
Documents of the prior art
Patent document
Patent document 1: japanese laid-open patent publication No. 9-266206
Patent document 2: japanese laid-open patent publication No. 2008-140856
Patent document 3: japanese patent laid-open No. 2010-34461.
Disclosure of Invention
Technical problem to be solved by the invention
However, the method for manufacturing a semiconductor device described in patent document 1 ignores the process dependency on the premise that the film stress of the wiring layer is not changed. In fact, since the film stress varies depending on the process conditions, the amount of warpage cannot be evaluated simply by the number of wiring layers, and this technique is difficult to apply. In addition, when the number of wiring layers is 500 in a 12-inch silicon wafer, the thickness T of the silicon wafer is equal to or greater than 777.1 μm according to the above calculation formula, but this is almost the same as 775 μm which is the standard thickness of the 12-inch wafer, and the effect of suppressing warpage is not expected significantly.
The thickness of the silicon wafer and other specifications are specified in advance regardless of the amount of the warp or the shape of the warp. Therefore, even if the silicon wafer is warped in the device process, there is no standard for changing the specification of the silicon wafer, and the warp of the wafer cannot be coped with.
Since the silicon wafer is less likely to bend as the thickness thereof increases, it is considered to use a very thick silicon wafer in which bending hardly occurs under any conditions. However, as the thickness of a silicon wafer is increased, the number of wafers obtained from one single crystal silicon ingot is decreased, and not only is the manufacturing yield deteriorated, but various problems occur in the subsequent processes such as handling problems due to the increase in the weight of the wafers. Therefore, it is desirable to provide a silicon wafer which can reduce the amount of warpage to some extent and is as thin as possible.
Accordingly, an object of the present invention is to provide a silicon wafer and a method for manufacturing the same, which can reduce wafer warpage occurring in a manufacturing process of a semiconductor device such as 3DNAND and can perform a subsequent process in which an abnormality occurs due to a large wafer warpage without any problem.
Means for solving the technical problem
In order to solve the above-described problems, a method for manufacturing a silicon wafer according to the present invention is characterized in that a target thickness of a silicon wafer required to ensure a bend improvement amount of the silicon wafer bent in a device process is determined from a relationship between a thickness and a bend amount of the silicon wafer generated by applying the same film stress to a plurality of silicon wafers having different thicknesses, and a silicon wafer having the target thickness is manufactured by processing a single crystal silicon ingot.
According to the present invention, it is possible to know how much the thickness of the silicon wafer to which the same film stress is applied is bent, and thus to know how much the amount of bending is improved when the thickness of the wafer is increased. Therefore, a predetermined amount of improvement in wafer warpage can be actually secured in consideration of wafer warpage generated in the device process, and a subsequent process, which has not been performed until now because of a large wafer warpage, can be performed without any problem.
The amount of warpage of a wafer varies depending on the type of film stress (tensile stress or compressive stress) or actual process conditions, and therefore cannot be calculated simply from the number of wiring layers. The amount of wafer bow to be improved differs depending on the actual amount of wafer bow generated in the device process or the allowable range of wafer bow in each process. Further, it is not practical to use a very thick wafer in order to suppress the warpage of the wafer, and it is impossible to completely suppress the warpage of the wafer by controlling only the thickness of the wafer. Various measures against warpage are required to sufficiently reduce warpage of a wafer, and thickness control of the wafer is only one of these measures against warpage. Therefore, the present invention is effective as a method for solving the problem of wafer warpage generated in the device process, as long as the warpage can be reduced by, for example, 10% by controlling the thickness of the wafer.
The method for manufacturing a silicon wafer according to the present invention is preferably as follows: a relational expression between the amount of improvement in bending of the silicon wafer bent in a device step and a target thickness of the silicon wafer is obtained from the relation between the amount of bending and the thickness of the silicon wafer, and the target thickness of the silicon wafer is obtained by substituting the amount of improvement in bending into the relational expression. Thus, the target thickness of the wafer required for ensuring the amount of improvement in the warpage of the silicon wafer can be easily determined.
The method for manufacturing a silicon wafer according to the present invention is preferably as follows: the relational expression satisfies y = A (x/t-1) when y represents a warp improvement amount of the silicon wafer, x represents a target thickness of the silicon wafer, t represents a standard thickness of the silicon wafer, and A represents a constant. In this case, the relationship between the amount of warpage of the silicon wafer and the thickness of the silicon wafer preferably includes a relationship between the amount of warpage of the silicon wafer having the standard thickness t and the standard thickness t. Thus, the target thickness of the wafer required for securing the warp improvement amount y of the silicon wafer with respect to the standard thickness of the silicon wafer can be easily obtained.
In the present invention, the constant a is preferably a value corresponding to the amount of warpage of the silicon wafer generated by a device process. Thus, the target thickness of the wafer required for securing the warp improvement amount y of the silicon wafer can be accurately determined.
In the method for manufacturing a silicon wafer according to the present invention, it is preferable that the constant a is 900 or less when the bent shape of the silicon wafer due to the difference in the stress components of the films stacked at the time of device formation is a bowl shape. Thus, the target thickness of the wafer suitable for reducing the bowl-shaped warpage of the wafer can be obtained.
In the method for manufacturing a silicon wafer according to the present invention, it is preferable that the constant a is 1500 or less when the curved shape of the silicon wafer due to the difference in stress components of films stacked at the time of device formation is a saddle shape. Thus, the target thickness of the wafer suitable for reducing the saddle-shaped warpage of the wafer can be obtained.
In the present invention, it is preferable that the device is a 3DNAND flash memory. As described above, the 3DNAND flash memory has a significant problem of warpage of a wafer because the number of stacked memory cell arrays is very large. That is, as the number of layers increases as the device process proceeds, the warpage of the wafer gradually increases, and the amount of warpage of the wafer before reaching the uppermost layer exceeds the allowable range, and the device process after the wafer cannot be performed. However, according to the present invention, by taking a measure to suppress the warpage of the wafer from the stage before the formation of the device, the problem of warpage can be improved, and the failure of the device process can be avoided.
Effects of the invention
According to the present invention, it is possible to provide a method for manufacturing a silicon wafer, which can reduce the warpage of the wafer generated in the device process and can perform the subsequent process in which the wafer is largely warped and abnormal occurs without any problem.
Drawings
Fig. 1 is a flowchart for explaining a method for manufacturing a silicon wafer according to an embodiment of the present invention.
Fig. 2 is a schematic diagram for explaining a difference in the way of bending of a wafer caused by film stress given to a silicon wafer.
Fig. 3 is a schematic diagram for explaining a film pattern on a silicon wafer bent in a saddle shape.
FIG. 4 is a graph showing the relationship between the thickness and the amount of bending of a silicon wafer bent into a bowl shape.
Fig. 5 is a graph showing the relationship between the thickness of the silicon wafer and the amount of warp improvement obtained by conversion of the graph of fig. 4.
Fig. 6 is a graph showing the relationship between the thickness of the wafer and the warpage-improving amount, as in fig. 5.
FIG. 7 shows a constant A and a reference bending amount WARPiA graph of the relationship of (a).
FIG. 8 is a schematic perspective view showing a film formation pattern on a silicon wafer.
FIG. 9 is a graph showing the relationship between the thickness and the amount of bending of a silicon wafer bent in a saddle shape.
Fig. 10 is a graph showing the relationship between the thickness of the silicon wafer and the amount of warp improvement obtained by conversion of the graph of fig. 9.
Fig. 11 is a graph showing the relationship between the thickness of the wafer and the warpage-improving amount, as in fig. 10.
Fig. 12 is a graph showing the relationship between the constant a and the reference bending amount WARPi.
Detailed Description
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a flowchart for explaining a method for manufacturing a silicon wafer according to an embodiment of the present invention.
As shown in fig. 1, the method for manufacturing a silicon wafer according to the present embodiment includes: a 1 st step S1 of obtaining a relation between a thickness and a warpage amount of a silicon wafer generated when a plurality of silicon wafers having different thicknesses are subjected to the same film stress; a 2 nd step S2 of obtaining a relational expression between the bending improvement amount (y) of the silicon wafer bent in the device step and the target thickness (x) of the silicon wafer from the relation between the bending amount and the thickness of the silicon wafer; a 3 rd step S3 of obtaining a target thickness (x) of the silicon wafer required for ensuring the warp improvement amount (y) of the silicon wafer by substituting the desired warp improvement amount (y) into the relational expression; and a 4 th step S4 of processing the silicon single crystal ingot to manufacture a silicon wafer having a target thickness.
The silicon wafer in this embodiment refers to a silicon wafer before device processing is performed, and broadly includes not only a normal silicon wafer (polished wafer) but also an epitaxial wafer, an annealed wafer, an SOI wafer, and the like. The warpage amount (Warp) of the silicon wafer can be defined as the difference between the maximum value and the minimum value of the value obtained by subtracting the reference plane from the measurement plane.
In the present embodiment, the data table showing the relationship between the warpage amount and the thickness of the silicon wafer includes data showing the relationship between the warpage amount and the standard thickness of the silicon wafer having the standard thickness. The standard thickness of the silicon wafer means a thickness depending on the diameter of the silicon wafer, and for example, the standard thickness of a silicon wafer having a diameter of 300mm is 775 μm. In this way, the data indicating the relationship between the warp amount and the thickness of the silicon wafer includes the warp amount corresponding to the standard thickness of the silicon wafer, so that the reliability of the relational expression between the warp improvement amount and the target thickness of the silicon wafer can be improved, and the target thickness of the wafer required for ensuring the warp improvement amount of the silicon wafer can be accurately and easily obtained.
The relational expression between the amount of improvement in bending (y) of the silicon wafer and the target thickness (x) of the silicon wafer can be obtained from the relationship between the amount of bending of the silicon wafer and the thickness of the silicon wafer. The relationship between the amount of warpage of the silicon wafer and the thickness of the silicon wafer is expressed as a linear function, and the amount of warpage decreases as the thickness of the wafer increases. The rate of change (tilt) of the amount of bending of the silicon wafer with respect to the thickness is somewhat changed by the magnitude of the film stress given to the silicon wafer, but is not changed much. The present invention has been made in view of the above, and is very effective as an index for reducing the amount of warpage of a silicon wafer.
After the target thickness of the silicon wafer is determined in this manner, a silicon wafer having the target thickness is manufactured. Generally, a silicon wafer is manufactured by sequentially performing processes such as peripheral grinding, slicing, Lapping (Lapping), etching, double-side Lapping, single-side Lapping, and cleaning on a single crystal silicon ingot grown by the CZ method, and at this time, slicing conditions and Lapping conditions are controlled so that the final thickness of the wafer becomes a target thickness. The silicon wafer thus produced is sent to a process for producing a semiconductor device such as 3DNAND and is used as a substrate material of the semiconductor device.
As described above, in the manufacturing process of a semiconductor device, films of various materials including an oxide film, a nitride film, and a metal film are stacked on a silicon wafer in order to form a device structure on the silicon wafer. The films thus laminated have different film stresses due to the film properties and process conditions, and the silicon wafer is bent according to the stress of the laminated films. In particular, in 3DNAND, since each memory element is fabricated by vertically stacking several tens or more of memory elements, the number of films stacked therewith also increases geometrically, film stress also increases greatly in proportion thereto, and warpage of a silicon wafer also increases greatly.
However, in the present invention, the initial shape of the silicon wafer is logically controlled, so that the warpage generated in the device process can be reduced, and the subsequent process can be performed without problems. That is, the amount of warp can be reduced by providing a silicon wafer having an appropriate thickness based on the amount of warp actually generated in the semiconductor device process. Further, generation of defects such as misalignment due to bending of the silicon wafer can be reduced or prevented.
Fig. 2 is a schematic diagram for explaining a difference in the way of bending of a wafer caused by film stress given to a silicon wafer.
As shown in fig. 2, when a laminated film such as a wiring layer constituting a semiconductor device is formed on a surface of a silicon wafer, a film stress is generated on the silicon wafer, and thus a bowl-shaped bend as shown in (a) or a saddle-shaped bend as shown in (b) is generated. If the warpage of the wafer becomes large, various problems occur in the subsequent process.
On the other hand, the amount of warpage of a silicon wafer on the surface of which a thin film having a film stress is formed varies depending on the thickness of the silicon wafer, and particularly, the amount of warpage decreases as the wafer becomes thicker for the same film stress. This can also be done in the generally known relationship between film stress and wafer bow, the Stoney Equation σftf=Esh2Known in/6R. Here, σfDenotes the film stress, tfRepresents the film thickness, EsDenotes the young's modulus of the substrate, h denotes the thickness of the substrate, and R denotes the bending radius.
The reason why the silicon wafer is bent into the saddle shape shown in fig. 2 (b) in the device process is that anisotropy of film stress occurs due to a difference in sign of the film stress of the film formed on the silicon wafer. For example, as shown in fig. 3, when a wiring layer having tensile stress in the Y direction orthogonal to the X direction is formed in addition to a wiring layer governed by compressive stress in the X direction, the compressive stress in the X direction is emphasized, and the silicon wafer is bent in a saddle shape.
The young's modulus of silicon crystals differs depending on the crystal orientation, and has orientation dependence. [100] 130MPa in the [110] direction, 170MPa in the [111] direction, 189MPa in the [111] direction. The Young's modulus is small and easy to deform. When the wafer is bent in the saddle shape, the wafer is more easily bent if the wafer bending direction coincides with the direction in which the young's modulus of the crystal orientation is small, and the amount of bending increases. Conversely, if the direction in which the wafer is bent coincides with the direction in which the young's modulus of the crystal orientation is large, the wafer is more difficult to bend, and the amount of bending is reduced.
The wafer bow generated when a thin film having a film stress is formed on a silicon wafer can be reproduced by simulation. The thickness dependence of the silicon wafer is determined by a finite element method simulation for the same film stress, and a relational expression between the thickness of the silicon wafer and the amount of warpage of the wafer can be determined.
In this way, the relationship between the amount of warpage of the silicon wafer and the thickness of the silicon wafer, which is caused by the formation of a device with the film laminated thereon, is obtained, and the thickness x of the silicon wafer and the amount of warpage improvement y are expressed mathematically by the relational expression of y = a (x/t-1). Here, t is the standard thickness (μm) of a silicon wafer, for example 775 μm for a silicon wafer having a diameter of 300 mm. A mathematical expression is established for both bowl-shaped and saddle-shaped curvatures of the difference in the curved shape (refer to fig. 2) due to the difference in the stress component of the films stacked at the time of device formation. Then, the thickness of the wafer corresponding to the amount of warp to be improved in the device process is derived from the relational expression between the thickness of the silicon wafer and the amount of warp improvement. Based on the thickness of the wafer thus derived, a silicon wafer having the thickness is manufactured. Silicon wafers are manufactured by processing a single crystal silicon ingot.
The constant a in the above-described relational expression between the thickness of the silicon wafer and the warpage-improving amount is preferably set to a value corresponding to the amount of warpage of the wafer generated in the device process. In this case, when the silicon wafer has a bowl-shaped curvature, the range of a is preferably 900 or less. When the silicon wafer has a saddle-shaped curvature, the range of a is preferably 1500 or less.
As described above, according to the method for manufacturing a silicon wafer according to the present embodiment, in the silicon wafer having a semiconductor device formed on the surface thereof, the amount of warpage of the silicon wafer caused by the film stress of the laminated film such as a wiring layer formed on the silicon wafer can be reduced to a predetermined value or less.
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention, and these modifications are also included in the scope of the present invention.
For example, although the above embodiment describes the method for producing a silicon wafer suitable for producing 3DNAND, the present invention is not limited to such an example, and can be applied to various silicon wafers for semiconductor devices in which the wafer is bent due to film stress.
Examples
(example 1)
When a silicon oxide film having a thickness of 2 μm was formed on a silicon wafer having a diameter of 300mm and a thickness of 775 μm by a CVD (Chemical Vapor Deposition) process, a convex bowl-shaped curve was generated toward the film formation surface of the silicon wafer. The warpage amount (Warp) of the wafer was measured by a wafer flatness/shape measuring apparatus, and as a result, the warpage amount (reference warpage amount) was 610 μm.
After the same film formation was carried out for the silicon wafers having a thickness of 800 μm, 825 μm and 850 μm, the warpage amount of each wafer was measured, and as a result, it was 585 μm, 560 μm and 535 μm.
FIG. 4 is a graph showing the relationship between the thickness of a silicon wafer and the amount of warpage, with the thickness of the silicon wafer on the horizontal axis and the amount of warpage on the silicon wafer on the vertical axis. As is clear from fig. 4, when the film stress is constant, the amount of warpage decreases as the thickness of the silicon wafer increases.
Fig. 5 is a graph showing the relationship between the thickness of the silicon wafer and the amount of warp improvement obtained by converting the graph of fig. 4, in which the horizontal axis shows the thickness of the silicon wafer and the vertical axis shows the amount of warp improvement. The graph of FIG. 5 shows how much the amount of warpage decreases by how much the thickness of the wafer is further increased based on the amount of warpage of a silicon wafer of standard thickness (775 μm) (0). The graph of fig. 5 is expressed by a relation between a target thickness x of a silicon wafer and a bend improvement amount y: y = a (x/775-1), as follows.
y =760.5 (x/775-1) … … (formula 1).
This relational expression means that when the warpage amount to be improved is substituted into y, the thickness x of the wafer required for improving the warpage amount can be obtained.
Next, a confirmation experiment was performed using this relational expression. Substituting the target bend improvement amount y =35 μm into the relation: with y =760.5 (x/775-1), a target thickness of the silicon wafer of x =810.67 μm can be obtained. Therefore, when a silicon wafer having a diameter of 300mm and a thickness of 810.2 μm was prepared and a silicon oxide film having a thickness of 2 μm was formed thereon by a CVD process, a convex bowl-shaped curve was generated on the wafer, and a curve amount of 572.2 μm was given. The actual amount of bend improvement was 610-572.2=37.8 μm relative to the targeted amount of bend improvement y =35 μm, almost as with the targeted results.
(example 2)
Next, the experiment carried out in example 1 was added to prepare 2 silicon wafers having a diameter of 300mm and a thickness of 775 μm, and after a silicon oxide film having a thickness of 0.8 μm was formed on one silicon wafer by a CVD process, convex bowl-shaped warpage was generated with a warpage amount of 233 μm. Then, a silicon oxide film having a thickness of 3.5 μm was formed on the other silicon wafer in the same manner, and then convex bowl-shaped warpage occurred, and the amount of warpage was 1042 μm.
After the same film formation was carried out for the silicon wafers having a thickness of 800 μm, 825 μm and 850 μm, the warpage amount of each wafer was measured, and the relationship between the thickness of the silicon wafer and the warpage amount was determined. Then, the amount of improvement in the warpage of the wafer was calculated by converting the value of the wafer into a relative value when compared with the amount of warpage of a silicon wafer having a standard thickness (775 μm). The results are shown in the graph of fig. 6.
Fig. 6 is a graph showing the relationship between the thickness of the wafer and the warpage-improving amount, as in fig. 5, in which the horizontal axis shows the thickness of the wafer and the vertical axis shows the warpage-improving amount of the wafer. As shown in fig. 6, the slopes of the graphs are slightly different from each other, and the slope of the graph becomes larger as the film stress applied to the wafer becomes larger.
Each graph of fig. 6 is expressed by a relation between a target thickness (x) of a silicon wafer and a warp improvement amount (y): y = A (x/775-1), and as shown in FIG. 7, the constant A is set as the reference bending amount WARPiThe function of (2) is as follows.
A=-0.001×WARPi 2+1.8472×WARPi… … (equation 2).
In addition, the reference bending amount WARPiIt can be said that the wafer is bent at a standard thickness (775 μm), and the silicon oxide film is bent at a reference bending WARP of 0.8 μm, 2 μm, or 3.5 μmi233 μm, 610 μm and 1042 μm, respectively. As can be seen from FIG. 7, the constant A does not coincide with the reference bending amount WARPiThe constant A is 900 or less in the case where the bent shape of the silicon wafer is a bowl shape.
Based on the constant A and the reference bending quantity WARPiThe reference bending amount WARPiThe constant A at 233 μm was 380.59. Thus, the relational expression between the thickness x of the silicon wafer and the warpage-improving amount y is y =380.59 (x/775-1).
Next, a confirmation experiment was performed using this relational expression. Substituting the target bending improvement amount y =20 μm into the relation: y =380.59 (x/775-1), a target thickness of the silicon wafer x =815.73 μm can be obtained. Therefore, when a silicon wafer having a diameter of 300mm and a thickness of 815.5 μm was prepared and a silicon oxide film having a thickness of 0.8 μm was formed thereon by a CVD process, a convex bowl-shaped curve was generated on the wafer, and a curve amount of 210.2 μm was caused. The actual amount of bend improvement was 233-210.2=22.8 μm relative to the targeted amount of bend improvement y =20 μm, almost as with the targeted results.
(example 3)
A film formation pattern as shown in FIG. 8 was formed by forming a silicon oxide film having a thickness of 1 μm on a (100) silicon wafer having a diameter of 300mm and a thickness of 775 μm by a CVD process, etching a part of the silicon oxide film by using a mask, forming a silicon nitride film having a thickness of 0.7 μm in the same manner, and etching a part of the silicon nitride film by using a mask. As a result, saddle-shaped warpage occurs in the wafer. The warpage amount (Warp) of the wafer was measured, and the warpage amount (reference warpage amount) was 608 μm.
After the same film formation was carried out for the silicon wafers having a thickness of 800 μm, 825 μm and 850 μm, the warpage amount of each wafer was measured, and as a result, it was 575 μm, 545 μm and 515 μm.
FIG. 9 is a graph showing the relationship between the thickness of a silicon wafer and the amount of warpage, with the thickness of the silicon wafer on the horizontal axis and the amount of warpage on the silicon wafer on the vertical axis. As is clear from fig. 9, when the film stress is constant, the silicon wafer has a saddle-shaped curved shape, and the amount of curvature decreases as the thickness of the silicon wafer increases.
Fig. 10 is a graph showing the relationship between the thickness of the silicon wafer and the amount of warp improvement obtained by converting the graph of fig. 9, the horizontal axis shows the thickness of the silicon wafer, and the vertical axis shows the amount of warp improvement of the silicon wafer. The graph of fig. 10 shows how much the amount of bending is reduced by how much the thickness of the silicon wafer is further increased based on the amount of bending of the silicon wafer of the standard thickness (775 μm) (0). The graph of fig. 10 is expressed by a relation between a target thickness x of a silicon wafer and a bend improvement amount y: y = a (x/775-1), as follows.
y =925.95 (x/775-1) … … (formula 3).
Next, a confirmation experiment was performed using this relational expression. Substituting the target bending improvement amount y =45 μm into the relation: y =925.95 (x/775-1), a target thickness of the silicon wafer x =812.7 μm can be obtained. Therefore, when a silicon wafer having a diameter of 300mm and a thickness of 812.1 μm was prepared and a silicon oxide film having a thickness of 2 μm was formed thereon by a CVD process, a convex bowl-shaped curve was generated on the wafer, and a curve amount of 565.0 μm was obtained. The actual amount of bend improvement was 608-565.0=43 μm with respect to the targeted amount of bend improvement y =45 μm, almost as with the targeted results.
(example 4)
Next, the experiment carried out in example 3 was added to prepare 2 (100) wafer-shaped silicon wafers having a diameter of 300mm and a thickness of 775 μm, on which silicon oxide films having a thickness of 0.5 μm and 2.0 μm were formed by a CVD process, respectively, and then a part thereof was etched with a mask, and then silicon nitride films having a thickness of 0.24 μm and 1.4 μm were formed by a CVD process, and then a part thereof was etched with a mask, thereby forming a film formation pattern as shown in fig. 8. As a result, the wafer was saddle-warped by 213 μm and 1217 μm, respectively.
After the same film formation was carried out for the silicon wafers having a thickness of 800 μm, 825 μm and 850 μm, the warpage amount of each wafer was measured, and the relationship between the thickness of the silicon wafer and the warpage amount was determined. Then, the amount of improvement in the warpage of the wafer was calculated by converting the value of the wafer into a relative value when compared with the amount of warpage of a silicon wafer having a standard thickness (775 μm). The results are shown in FIG. 11.
Fig. 11 is a graph showing the relationship between the thickness of the wafer and the warpage-improving amount in the same manner as in fig. 10, in which the horizontal axis shows the thickness of the wafer and the vertical axis shows the warpage-improving amount of the wafer. As shown in fig. 11, the slopes of the graphs are slightly different from each other, and the slope of the graph becomes larger as the film stress applied to the wafer becomes larger.
The graph of fig. 11 is expressed by a relation between the thickness (x) of the silicon wafer and the bend improvement amount (y): y = A (x/775-1), and as shown in FIG. 12, the constant A is set as the reference bending amount WARPiThe function of (2) is as follows.
A=-0.0006×WARPi 2+1.8891×WARPi… … (equation 4).
In addition, the reference bending amount WARPiIt can be said that the wafer warpage is the standard wafer warpage (775 μm), and the standard warpage WARP is the standard wafer warpage when the silicon oxide film for applying film stress has a thickness of 0.5 μm, 1 μm, or 2.0 μm (the silicon nitride film has a thickness of 0.24 μm, 0.7 μm, or 1.4 μm)i213 μm, 608 μm, 1217 μm, respectively. As can be seen from FIG. 12, the constant A does not coincide with the reference bending amount WARPiThe constant A is 1500 or less in the case where the silicon wafer has a saddle-shaped curved shape.
Based on the constant A and the reference bending quantity WARPiThe reference bending amount WARPiThe constant A in the case of 213 μm was 362.54. Thus, the relational expression between the thickness x of the silicon wafer and the warpage-improving amount y is y =362.54 (x/775-1).
Next, a confirmation experiment was performed using this relational expression. Substituting the target bending improvement amount y =20 μm into the relation: y =362.54 (x/775-1), a target thickness of the silicon wafer x =817.75 μm can be obtained. Therefore, when a silicon wafer having a diameter of 300mm and a thickness of 817.6 μm was prepared and a silicon oxide film having a thickness of 0.5 μm was formed thereon by a CVD process, a convex bowl-shaped curve was generated on the wafer, and a curve amount of 191.8 μm was obtained. The actual amount of bend improvement was 213-191.8=21.2 μm relative to the targeted amount of bend improvement y =20 μm, almost as with the targeted results.
Description of the reference numerals
S1-a step of finding the relation between the amount of warp and the thickness of the silicon wafer (step 1), S2-a step of finding the relation between the amount of improvement in warp and the target thickness (x) (step 2), S3-a step of finding the target thickness of the silicon wafer by substituting the desired amount of improvement in warp into the relation (step 3), S4-a step of manufacturing a silicon wafer having the target thickness (step 4).

Claims (8)

1. A method for manufacturing a silicon wafer is characterized in that,
determining a target thickness of the silicon wafer required for securing a bend improvement amount of the silicon wafer bent in a device process from a relationship between a bend amount and a thickness of the silicon wafer generated by applying the same film stress to a plurality of silicon wafers having different thicknesses,
processing a single crystal silicon ingot to produce a silicon wafer having the target thickness.
2. The manufacturing method of a silicon wafer according to claim 1, wherein,
a relational expression between the amount of improvement in bending of the silicon wafer bent in a device step and a target thickness of the silicon wafer is obtained from the relation between the amount of bending and the thickness of the silicon wafer, and the target thickness of the silicon wafer is obtained by substituting the amount of improvement in bending into the relational expression.
3. The manufacturing method of a silicon wafer according to claim 2, wherein,
the relational expression satisfies y = A (x/t-1) when y represents a warp improvement amount of the silicon wafer, x represents a target thickness of the silicon wafer, t represents a standard thickness of the silicon wafer, and A represents a constant.
4. The manufacturing method of a silicon wafer according to claim 3, wherein,
the relation of the bending amount of the silicon wafer to the thickness comprises the relation of the bending amount of the silicon wafer with the standard thickness t to the standard thickness t.
5. The manufacturing method of a silicon wafer according to claim 3 or 4, wherein,
the constant A is a value corresponding to the amount of warpage of the silicon wafer generated by a device process.
6. The manufacturing method of a silicon wafer according to any one of claims 3 to 5, wherein,
when the bent shape of the silicon wafer caused by the difference in the stress components of the films stacked during device formation is a bowl shape, the constant A is 900 or less.
7. The manufacturing method of a silicon wafer according to any one of claims 3 to 5, wherein,
when the silicon wafer has a saddle-shaped curvature due to a difference in stress components of films stacked during device formation, the constant A is 1500 or less.
8. The manufacturing method of a silicon wafer according to any one of claims 1 to 7, wherein,
the device is a 3DNAND flash memory.
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