CN111130522B

CN111130522B - Gate switch time sequence generating circuit in multichannel infrared detector reading circuit

Info

Publication number: CN111130522B
Application number: CN202010026436.3A
Authority: CN
Inventors: 赵毅强; 王秋玮; 李尧; 郑肖; 叶茂
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2020-01-10
Filing date: 2020-01-10
Publication date: 2023-10-17
Anticipated expiration: 2040-01-10
Also published as: CN111130522A

Abstract

The application discloses a gating switch time sequence generating circuit in a multichannel infrared detector reading circuit, which is provided with only one external input signal, namely an INT signal, wherein the gating switch time sequence generating circuit is divided into two parts, the first part is an input code generating circuit and is controlled by a clock signal and used for generating an input code of a decoder; the second part is a decoding circuit for decoding the input code and outputting a gating signal successively. The circuit input signal of the application can output the control time sequence of the multi-channel gating switch by only needing one external input clock signal INT besides the power supply VDD and the ground VSS, and the pulse width of the output signal can be controlled by INT, namely the single-channel gating time is controllable. The application has less input signals and simple structure, and the output signals can be controlled by the input signals, thereby reducing the complexity of the overall design of the reading circuit and being more beneficial to realizing integration and intellectualization.

Description

Gate switch time sequence generating circuit in multichannel infrared detector reading circuit

Technical Field

The application relates to the technical field of mixed signal integrated circuits, in particular to a gating switch time sequence generating circuit in a multi-channel infrared detector reading circuit.

Background

In recent years, integrated circuits have been developed at a high speed, and new integrated circuit industries have been developed. At present, microelectronic technology marked by the development of integrated circuits is ubiquitous and has become the basis of modern information society. With the increase of system integration and application demands, more and more digital circuit modules and analog circuit modules are embedded in the same chip, so that the development of electronic equipment towards miniaturization, low cost and high efficiency is promoted, and the electronic equipment is widely applied to various fields such as electronic communication, target detection and the like.

In a mixed signal integrated circuit, especially a detector readout circuit, such as an infrared detector readout circuit, a detector is generally formed into a detector array, and a multichannel signal readout is performed by matching with a multichannel readout circuit, so that a multichannel gating switch is required to control an output signal, and the signal is ensured to be output according to a correct time sequence.

Generally, there are two main ways to generate the control timing of the multi-channel output strobe switch. The first is to write codes of corresponding functions by using digital codes, such as hardware description languages of Verilog and the like, and compile the codes by a digital tool to automatically convert the digital codes into a circuit layout. The second is to design a schematic diagram of the circuit by a circuit design tool, realize the required control time sequence by simulation and manually draw the circuit layout. Since the front end of the readout circuit is often an analog circuit, the first method requires using digital-analog mixing in the overall circuit design, which increases the complexity of the operation. Meanwhile, the circuit layout generated in the first mode is often unreadable, the layout shape is not easy to change according to the requirement, and the interference of the digital signal on the output signal can be caused. The second mode is to manually customize the circuit, so that the drawn circuit layout is easy to change according to the requirement, and the circuit layout is more beneficial to being integrated into a circuit, in particular to a large-scale integrated circuit of a detector array readout circuit.

Disclosure of Invention

The application aims at a gating switch time sequence generating circuit in a multichannel infrared detector reading circuit.

In order to achieve the purpose of the application, the application provides a gating switch time sequence generating circuit in a multi-channel infrared detector reading circuit, which only has one external input signal, namely a clock signal INT,

the gating switch time sequence generating circuit is divided into two parts, wherein the first part is an input code generating circuit and is controlled by a clock signal and used for generating an input code of a decoder; the second part is a decoding circuit for decoding the input code and outputting a gating signal successively.

Wherein, the liquid crystal display device comprises a liquid crystal display device,

the input code generation circuit outputs a group of cyclic 4-bit binary numbers as input codes of a decoder under the control of a clock signal; the decoding circuit is a 4-16 decoder formed by 4 NOT gates and 16 AND gates, the 4-16 decoder decodes the 4-bit binary input code, sequentially outputs 16 output signals, only 1 output signal is high level at a time, and the other 15 output signals are low level, namely, 16-channel sequential gating signals are generated.

the input code generation circuit comprises 4 half adder circuits and 4D trigger circuits, wherein the half adder has two input ends and two output ends, A is an summand input end, and B is an summand input end; s is the sum output end, and C is the carry output end. The D trigger is provided with two input ends and an output end, wherein CP is an input clock, D is an input signal, and Q is an output signal; the circuit is divided into 4 stages, and the S output end of the half adder in each stage is connected with the D input end of the D trigger; the output end of the C of the half adder is connected with the input end of the B of the half adder of the next stage, and the carry of the previous stage is used as the addition of the next stage; the Q output end of the D trigger is connected with the A input end of the half adder while outputting, so as to form feedback. The D trigger is triggered by rising edge, namely when the rising edge of the INT clock signal arrives, the Q output end outputs the signal of the D input end at the last moment, and the function of delay output is realized.

Compared with the prior art, the application has the beneficial effects that the control time sequence generating circuit of the gating switch in the multichannel reading circuit is provided, and sequential gating of multiple channels is realized. The circuit input signal of the application can output the control time sequence of the multi-channel gating switch by only needing one external input clock signal INT besides the power supply VDD and the ground VSS, and the pulse width of the output signal can be controlled by INT, namely the single-channel gating time is controllable. The application has less input signals and simple structure, and the output signals can be controlled by the input signals, thereby reducing the complexity of the overall design of the reading circuit and being more beneficial to realizing integration and intellectualization.

Drawings

FIG. 1 is a schematic diagram of the overall circuit of the present application;

FIG. 2 is a schematic diagram of an input code generation circuit according to the present application;

FIG. 3 is a circuit diagram of a half adder of the present application;

FIG. 4 is a circuit diagram of a D flip-flop of the present application;

FIG. 5 is a timing diagram of an input code generating circuit according to the present application;

FIG. 6 is a circuit diagram of a decoding circuit according to the present application;

FIG. 7 is a timing diagram of a decoding circuit according to the present application;

FIG. 8 is a timing diagram of the overall circuit of the present application.

Detailed Description

The application is described in further detail below with reference to the drawings and the specific examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the singular is "a," an, "and/or" the "include" when used in this specification is taken to mean that there are features, steps, operations, components or modules, assemblies, and/or combinations thereof.

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.

The embodiment of the application provides a time sequence generating circuit structure of a multi-channel output gating switch. The circuit is composed of a half adder, a D trigger, a decoder and the like, and finally outputs the control time sequence of the multi-channel gating through cascade connection, feedback and combination of the half adder, the D trigger, the decoder and the like. The overall circuit has only one external input signal, i.e. the clock signal INT. Taking a 16-channel readout circuit as an example, in the embodiment of the application, an adder and a D flip-flop cascade are used as an input code generating circuit, an INT clock signal is applied to the input code generating circuit cascaded by 4 adders and 4D flip-flops to generate a set of cyclic 4-bit binary numbers, the set is sequentially added with 1, and delayed output is realized by the D flip-flops, so that the cyclic 4-bit binary input codes of 0000, 0001, 0010, 0011 … … 1110, 1111, 0000 and 0001 … … are sequentially output. The set of cyclic 4-bit binary numbers is used as the input code of a decoder, which decodes the cyclic 4-bit binary numbers to generate the strobe signal of each channel in turn. The decoding is carried out through the 4-16 decoder, 16 output signals are output each time, only 1 output signal is high level each time, and the other 15 output signals are low level signals, namely, the control time sequence of the 16-channel output gating switch is output, the 16-channel sequential gating is realized, and the schematic diagram of the whole circuit is shown in figure 1.

The application finally generates the control time sequence of the gating switch in the 16-channel reading circuit through the combination, cascade connection, feedback and time delay of the simple logic gate structure, so that 16 channels are sequentially gated and output. The circuit has a simple overall structure and only has one external input clock signal INT. The clock period of INT can determine the pulse width of the output signal, and the gating time of a single channel is controllable.

In order to generate the correct control time sequence of the multi-channel gating switch, the application provides a time sequence generating circuit structure of the multi-channel output gating switch. The circuit is composed of a half adder, a D trigger, a decoder and the like, and finally outputs the control time sequence of the multi-channel gating through cascade connection, feedback and combination of the half adder, the D trigger, the decoder and the like. The overall circuit has only one external input signal, i.e. the clock signal INT. Taking a 16-channel readout circuit as an example, the whole circuit is mainly divided into two parts, wherein the first part is an input code generation circuit, and a group of circulating 4-bit binary numbers are output as input codes of a decoder under the control of a clock signal. The second part is a decoding circuit, the 4-16 decoder decodes the 4-bit binary input code, sequentially outputs 16 output signals, only 1 output signal is high level at a time, and the other 15 output signals are low level, namely 16-channel sequential gating signals are generated.

The first part of the circuit is an input code generating circuit. Consists of 4 half adder circuits and 4D trigger circuits. The schematic diagram of the input code generation circuit is shown in fig. 2, the half adder circuit diagram is shown in fig. 3, and the D flip-flop circuit diagram is shown in fig. 4. The half adder is provided with two input ends and two output ends, wherein A is an added number input end, and B is an added number input end; s is the sum output end, and C is the carry output end. The D trigger has two input ends and an output end, CP is input clock, D is input signal, Q is output signal. The circuit is divided into 4 stages, and the S output end of the half adder in each stage is connected with the D input end of the D trigger; the output end of the C of the half adder is connected with the input end of the B of the half adder of the next stage, and the carry of the previous stage is used as the addition of the next stage; the Q output end of the D trigger is connected with the A input end of the half adder while outputting, so as to form feedback. The D trigger is triggered by rising edge, namely when the rising edge of the INT clock signal arrives, the Q output end outputs the signal of the D input end at the last moment, and the function of delay output is realized.

The timing diagram of the input code generation circuit is shown in fig. 5. In the initial state, the outputs A1, A2, A3, A4 are all 0, A4 is defined as high, A1 is defined as low, and the outputs a4a3a2a1=0000. b=0, e=0, h=0, k=0, and the added numbers of the four half adders are all 0 through the feedback loop. The B input of the half adder 1 is always connected to VDD high, i.e. the half adder 1 performs an add 1 operation on the summand a each time. Then at the next moment the half adder 1 performs an add 1 operation, outputting s=1, c=0, i.e. a=1, c=0. The input terminal d=1 of the D flip-flop 1 waits for the rising edge of the first INT clock signal to come, and outputs q=1, i.e. a1=1. Meanwhile, b=1 sets the added number of the half adder 1 to 1 through a feedback loop, and the half adder 1 performs addition 1 operation again at the next moment to output s=0 and c=1, namely a=0 and c=1. The input terminal d=0 of the D flip-flop 1 waits for the rising edge of the second INT clock signal to come, and outputs q=0, i.e. a1=0. b=0, and the added number of the half adder 1 is set to 0 again through the feedback loop, and the half adder 1 performs the addition 1 operation again at the next moment. The rising edge of the third INT clock signal comes, the output A1=1, the rising edge of the fourth INT clock signal comes, the output A1=0, and so on, with the rising edge of each INT clock signal coming, A1 performs a 0 to 1 transition. Meanwhile, the carry signal of the half adder 1 performs 0-1 conversion once per INT clock signal, i.e. the addend of the half adder 2 performs 0-1 conversion once per INT clock signal. The first INT clock signal comes with c=1 and the addend of the half adder 2 is set to 1. At the next moment the half adder 2 performs an addition, the output s=1, c=0, i.e. d=1, f=0. Waiting for the arrival of the second INT clock signal, D flip-flop 2 outputs q=1, i.e. a2=1. e=1, the added number of the half adder 2 is set to 1 through the feedback loop, and at the same time, the carry signal c of the half adder 1 is c=0 when the second INT clock signal arrives, and at the next moment, the half adder 2 outputs s=1, c=0. Waiting for the arrival of the third INT clock signal, D flip-flop 2 outputs q=1, i.e. a2=1 unchanged. The summand of the half adder 2 is still 1, while the carry signal c of the half adder 1 is c=1 when the third INT clock signal arrives, and the half adder 2 outputs s=0, c=1 at the next time. Waiting for the fourth INT clock signal to come, D flip-flop 2 outputs q=0, i.e. a2=0. e=0, the added number of the half adder 2 is set to 0 through the feedback loop, and at the same time, the carry signal c of the half adder 1 is c=0 when the fourth INT clock signal arrives, and at the next moment, the half adder 2 outputs s=0, c=0. Waiting for the fifth INT clock signal to come, the D flip-flop 2 outputs q=0, i.e. a2=0 unchanged. The summand of the half adder 2 is still 0, while the carry signal c of the half adder 1 is c=1 when the fifth INT clock signal arrives, and the half adder 2 outputs s=1, c=0 at the next time. Waiting for the arrival of the sixth INT clock signal, D flip-flop 2 outputs q=1, i.e. a2=1. Similarly, with the arrival of every two INT clock signals, A2 performs a 0-1 conversion, while the carry signal of the half adder 2 performs a 0-1 conversion every two INT clock signals, i.e. the addend of the half adder 3 changes every two INT clock signals. Similarly, A3 varies once every four INT clock signals and A4 varies once every eight INT clock signals. Finally, the A4A3A2A1 sequentially outputs 0000, 0001, 0010 … … 1110, 1111, 0000 and 0001 … … circulating 4-bit binary numbers, and the circulating 4-bit binary numbers are used as input codes of a decoder.

The second part of the circuit is a decoding circuit. The structure is a 4-16 decoder consisting of 4 NOT gates and 16 AND gates. A schematic diagram of the decoding circuit is shown in fig. 6. The 3-8 decoder typically has three chip select signal inputs S3, S2, S1 in addition to the three inputs A3, A2, A1, which can be extended by cascading multiple 3-8 decoders. Although this method can be used to extend a 3-line-8-line decoder to a 4-line-16-line decoder, three chip select signals S3, S2, S1 need to be added, increasing the number of ports of the circuit, and increasing the complexity of the circuit. The design is thus made using a 4-16 decoder architecture with only 4 inputs. The 4-16 decoder operates in a similar manner to the 3-8 decoder, having four input signals as 4-bit input codes, and outputting 16 output signals by decoding. The 4-bit binary number output by the input code generating circuit is used as the input end of the 4-16 decoder, A4 is defined as high order, and A1 is defined as low order. If a4a3a2a1=0000, only the Y0 output end outputs 1 finally through the logical operation of the not gate and the and gate, and the other output ends all output 0. If a4a3a2a1=0110, only the Y6 output outputs 1, the remaining outputs output 0, and so on. The timing diagram of the decoding circuit is shown in fig. 7.

Since the signal output from the input code generation circuit is related to the timing of the INT clock signal, the decoding circuit will also decode according to the timing generated by the input code, and finally output the 16-channel gating switch control timing signal.

The timing diagram of the overall circuit is shown in fig. 8.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims

1. A gating switch time sequence generating circuit in a multichannel infrared detector reading circuit is characterized in that the gating switch time sequence generating circuit only has one external input signal, namely a clock signal INT,

the gating switch time sequence generating circuit is divided into two parts, wherein the first part is an input code generating circuit and is controlled by a clock signal and used for generating an input code of a decoder; the second part is a decoding circuit for decoding the input code and outputting a gating signal successively;

the input code generation circuit outputs a group of cyclic 4-bit binary numbers as input codes of a decoder under the control of a clock signal; the decoding circuit is a 4-16 decoder formed by 4 NOT gates and 16 AND gates, the 4-16 decoder is used for decoding 4-bit binary input codes, 16 output signals are sequentially output, only 1 output signal is high level at each time, and the other 15 output signals are low level, namely 16-channel sequential gating signals are generated;

the input code generation circuit comprises 4 half adder circuits and 4D trigger circuits, wherein the half adder has two input ends and two output ends, A is an summand input end, and B is an summand input end; s is a sum output end, and C is a carry output end; the D trigger is provided with two input ends and an output end, wherein CP is an input clock, D is an input signal, and Q is an output signal; the circuit is divided into 4 stages, and the S output end of the half adder in each stage is connected with the D input end of the D trigger; the output end of the C of the half adder is connected with the input end of the B of the half adder of the next stage, and the carry of the previous stage is used as the addition of the next stage; the Q output end of the D trigger is connected with the A input end of the half adder while outputting, so as to form feedback; the D trigger is triggered by rising edge, namely when the rising edge of the INT clock signal arrives, the Q output end outputs the signal of the D input end at the last moment, and the function of delay output is realized.