CN111130522A

CN111130522A - Gating switch time sequence generating circuit in multichannel infrared detector reading circuit

Info

Publication number: CN111130522A
Application number: CN202010026436.3A
Authority: CN
Inventors: 赵毅强; 王秋玮; 李尧; 郑肖; 叶茂
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2020-01-10
Filing date: 2020-01-10
Publication date: 2020-05-08
Anticipated expiration: 2040-01-10
Also published as: CN111130522B

Abstract

The invention discloses a gating switch time sequence generating circuit in a multichannel infrared detector reading circuit, wherein the gating switch time sequence generating circuit only has one external input signal, namely a clock signal INT, and is divided into two parts, wherein the first part is an input code generating circuit and is controlled by the clock signal and used for generating an input code of a decoder; the second part is a decoding circuit for decoding the input code and outputting the strobe signal successively. The input signal of the circuit of the invention can output the control time sequence of the multi-channel gating switch only by an external input clock signal INT except for a power supply VDD and a ground VSS, and the pulse width of the output signal can be controlled by INT, namely the single-channel gating time is controllable. The invention has less input signals and simple structure, and the output signals can be controlled by the input signals, thereby reducing the complexity of the overall design of the reading circuit and being more beneficial to realizing integration and intellectualization.

Description

Gating switch time sequence generating circuit in multichannel infrared detector reading circuit

Technical Field

The invention relates to the technical field of mixed signal integrated circuits, in particular to a gating switch time sequence generating circuit in a read-out circuit of a multi-channel infrared detector.

Background

In recent years, the development of integrated circuits has been accelerated, and a new integrated circuit industry has been developed. At present, the development of integrated circuits as a mark of microelectronic technology is ubiquitous, and has become the foundation of modern information society. With the increase of system integration and application requirements, more and more digital circuit modules and analog circuit modules are embedded in the same chip, so that the development of electronic equipment towards miniaturization, low cost and high efficiency is promoted, and the electronic equipment is widely applied to various fields such as electronic communication, target detection and the like.

In a mixed signal integrated circuit, especially a detector readout circuit, such as an infrared detector readout circuit, detectors are usually combined into a detector array, and a multi-channel readout circuit is used for multi-channel signal readout, so that a multi-channel gating switch is required to control output signals, and the signals are ensured to be output according to a correct time sequence.

Generally, there are two main ways to generate the control timing of the multi-channel output gating switch. The first method is to use digital codes, such as Verilog and other hardware description languages, to write codes of corresponding functions, and to compile the codes by digital tools, so as to automatically convert the digital codes into circuit layouts. The second is to design a schematic diagram of a circuit through a circuit design tool, realize a required control time sequence through simulation, and manually draw a circuit layout. Because the front end of the reading circuit is often an analog circuit, digital-analog mixed simulation is needed in the whole circuit design by adopting the first mode, and the complexity of work is increased. Meanwhile, the circuit layout generated by the first mode is often unreadable, the shape of the layout is not easy to change according to requirements, and interference of digital signals on output signals can be caused. In the second mode, a drawn circuit layout is easy to change according to requirements by a method of manually customizing a circuit, and the integration into the circuit is more facilitated, particularly a large-scale integrated circuit such as a detector array reading circuit.

Disclosure of Invention

The application aims at providing a gating switch time sequence generating circuit in a multichannel infrared detector reading circuit.

In order to achieve the object of the present invention, the present invention provides a gate switch timing generation circuit in a multi-channel infrared detector readout circuit, wherein the gate switch timing generation circuit has only one external input signal, i.e. a clock signal INT,

the gating switch time sequence generating circuit is divided into two parts, wherein the first part is an input code generating circuit and is controlled by a clock signal and used for generating an input code of a decoder; the second part is a decoding circuit for decoding the input code and outputting the strobe signal successively.

Wherein the content of the first and second substances,

the input code generating circuit outputs a group of circulating 4-bit binary numbers as the input codes of the decoder under the control of a clock signal; the decoding circuit is a 4-16 decoder consisting of 4 NOT gates and 16 AND gates, the 4-16 decoder decodes the 4-bit binary input code and outputs 16 output signals one by one, only 1 output signal is at high level each time, and the other 15 output signals are at low level, namely, 16-channel sequential gating signals are generated.

Wherein the content of the first and second substances,

the input code generating circuit comprises 4 half adder circuits and 4D trigger circuits, wherein the half adder is provided with two input ends and two output ends, A is an addend input end, and B is an addend input end; s is a sum output end, and C is a carry output end. The D trigger is provided with two input ends and an output end, CP is an input clock, D is an input signal, and Q is an output signal; the circuit is divided into 4 stages, and the S output end of the half adder in each stage is connected with the D input end of the D trigger; the output end of the half adder C is connected with the input end of the half adder B of the next stage, and the carry of the previous stage is used as the addend of the next stage; the Q output end of the D trigger is connected with the A input end of the half adder while outputting, and feedback is formed. The D trigger is triggered by a rising edge, namely when the rising edge of an INT clock signal arrives, the Q output end outputs a signal of the D input end at the previous moment, and the function of delay output is realized.

Compared with the prior art, the control time sequence generation circuit of the gating switch in the multi-channel reading circuit has the beneficial effects that the control time sequence generation circuit of the gating switch in the multi-channel reading circuit is provided, and multi-channel sequential gating is realized. The input signal of the circuit of the invention can output the control time sequence of the multi-channel gating switch only by an external input clock signal INT except for a power supply VDD and a ground VSS, and the pulse width of the output signal can be controlled by INT, namely the single-channel gating time is controllable. The invention has less input signals and simple structure, and the output signals can be controlled by the input signals, thereby reducing the complexity of the overall design of the reading circuit and being more beneficial to realizing integration and intellectualization.

Drawings

FIG. 1 is a schematic diagram of the overall circuit of the present application;

FIG. 2 is a schematic diagram of an input code generating circuit according to the present application;

FIG. 3 is a circuit diagram of the present application half-adder;

FIG. 4 is a circuit diagram of a D flip-flop of the present application;

FIG. 5 is a timing diagram of an input code generating circuit according to the present application;

FIG. 6 is a circuit diagram of a decoding circuit of the present application;

FIG. 7 is a timing diagram of the decoding circuit of the present application;

fig. 8 is a timing diagram of the overall circuit of the present application.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when used in this specification the singular forms "a", "an" and/or "the" include "specify the presence of stated features, steps, operations, elements, or modules, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

The embodiment of the invention provides a time sequence generating circuit structure of a multi-channel output gating switch. The circuit is composed of a half adder, a D trigger, a decoder and the like, and finally outputs the control time sequence of multi-channel gating through cascade connection, feedback and combination among the circuit. The whole circuit has only one external input signal, namely the clock signal INT. Taking a 16-channel readout circuit as an example, in the embodiment of the present invention, an adder and a D flip-flop cascade are used as an input code generation circuit, an INT clock signal is applied to the input code generation circuit formed by cascading 4 adders and 4D flip-flops to generate a set of cyclic 4-bit binary numbers, the set is sequentially added with 1, and delayed output is realized by the D flip-flops, so that cyclic 4-bit binary input codes of 0000, 0001, 0010, 0011 … … 1110, 1111, 0000, and 0001 … … are sequentially output. The set of 4-bit binary numbers of the cycle serves as an input code of a decoder, and the decoder decodes the input code to generate a gating signal of each channel in turn. The decoding is performed by the 4-16 decoder, 16 output signals are output each time, only 1 output signal is high level each time, and the other 15 output signals are all low level signals, that is, the control time sequence of the 16-channel output gating switch is output, so that the sequential gating of the 16 channels is realized, and the schematic diagram of the whole circuit is shown in fig. 1.

The invention finally generates the control time sequence of the gating switch in the 16-channel reading circuit through the combination, cascade connection, feedback and time delay among each other by a simple logic gate structure, so that 16 channels are sequentially gated and output. The whole circuit structure is simple, and only one external input clock signal INT is provided. The INT clock period can determine the pulse width of an output signal, and single-channel gating time control is achieved.

In order to generate correct control time sequence of the multi-channel gating switch, the invention provides a time sequence generating circuit structure of the multi-channel output gating switch. The circuit is composed of a half adder, a D trigger, a decoder and the like, and finally outputs the control time sequence of multi-channel gating through cascade connection, feedback and combination among the circuit. The whole circuit has only one external input signal, namely the clock signal INT. Taking a 16-channel reading circuit as an example, the whole circuit is mainly divided into two parts, the first part is an input code generating circuit, and a group of circulating 4-bit binary numbers are output as input codes of a decoder through clock signal control. The second part is a decoding circuit, a 4-16 decoder decodes the 4-bit binary input code, 16 output signals are output successively, only 1 output signal is at high level each time, and the other 15 output signals are at low level, namely, 16-channel sequential gating signals are generated.

The first part of the circuit is an input code generating circuit. The circuit is composed of 4 half adder circuits and 4D flip-flop circuits. The schematic diagram of the input code generating circuit is shown in fig. 2, wherein the circuit diagram of the half-adder is shown in fig. 3, and the circuit diagram of the D flip-flop is shown in fig. 4. The half adder is provided with two input ends and two output ends, wherein A is an addend input end, and B is an addend input end; s is a sum output end, and C is a carry output end. The D flip-flop has two input ends and an output end, CP is the input clock, D is the input signal, Q is the output signal. The circuit is divided into 4 stages, and the S output end of the half adder in each stage is connected with the D input end of the D trigger; the output end of the half adder C is connected with the input end of the half adder B of the next stage, and the carry of the previous stage is used as the addend of the next stage; the Q output end of the D trigger is connected with the A input end of the half adder while outputting, and feedback is formed. The D trigger is triggered by a rising edge, namely when the rising edge of an INT clock signal arrives, the Q output end outputs a signal of the D input end at the previous moment, and the function of delay output is realized.

The timing diagram of the input code generation circuit is shown in fig. 5. In the initial state, the outputs a1, A2, A3, A4 are all 0, A4 is defined as high, a1 is defined as low, and the output A4A3A2a1 is 0000. b is 0, e is 0, h is 0, k is 0, and the summands of the four half adders are all 0 through a feedback loop. The B input of the half-adder 1 is always connected to the VDD high level, i.e. the half-adder 1 adds 1 to the summand a each time. At the next time, the half adder 1 performs the addition 1 operation, and the output S is 1, C is 0, i.e., a is 1 and C is 0. The input end D of the D flip-flop 1 is equal to 1, and waits for the rising edge of the first INT clock signal to arrive, and the output Q is equal to 1, that is, the output a1 is equal to 1. At the same time, b is 1, the number of summations of the half adder 1 is set to 1 by a feedback loop, and at the next moment, the half adder 1 performs the 1 addition operation again, and the output S is 0, C is 1, that is, a is 0, and C is 1. The input end D of the D flip-flop 1 is equal to 0, and waits for the rising edge of the second INT clock signal to arrive, and the output Q is equal to 0, that is, the output a1 is equal to 0. When b is 0, the adder-half 1 sets the addend of the adder-half 1 to 0 again by the feedback loop, and the adder-half 1 performs the 1 addition operation again at the next timing. The rising edge of the third INT clock signal arrives, output a1 equals 1, the rising edge of the fourth INT clock signal arrives, output a1 equals 0, and so on, a1 makes 0-to-1 transitions with each rising edge of the INT clock signal. At the same time, the carry signal of half-adder 1 makes a 0-to-1 transition per INT clock signal, i.e., the addend of half-adder 2 makes a 0-to-1 transition per INT clock signal. The first INT clock signal arrives with c 1 and the addend of half-adder 2 is set to 1. At the next time, the half adder 2 performs addition, and outputs S ═ 1, C ═ 0, i.e., d ═ 1, and f ═ 0. When waiting for the second INT clock signal, D flip-flop 2 outputs Q ═ 1, i.e., a2 ═ 1. The e-1 sets the addend of the half adder 2 to 1 through a feedback loop, meanwhile, the carry signal C of the half adder 1 is 0 when the second INT clock signal arrives, and the half adder 2 outputs S-1 and C-0 at the next moment. When waiting for the third INT clock signal, D flip-flop 2 outputs Q ═ 1, i.e., a2 ═ 1. The summand of half-adder 2 remains 1, while the carry signal C of half-adder 1 is 1 when the third INT clock signal arrives, and at the next moment half-adder 2 outputs S0, C1. Waiting for the fourth INT clock signal to arrive, D flip-flop 2 outputs Q ═ 0, i.e., a2 ═ 0. The e is 0, the addend of the half adder 2 is set to 0 through a feedback loop, meanwhile, the carry signal C of the half adder 1 is 0 when the fourth INT clock signal arrives, the half adder 2 outputs S is 0 at the next moment, and C is 0. When waiting for the fifth INT clock signal, D flip-flop 2 outputs Q ═ 0, i.e., a2 ═ 0. The summand of half-adder 2 is still 0, while the carry signal C of half-adder 1 is equal to 1 when the fifth INT clock signal arrives, and at the next moment half-adder 2 outputs S equal to 1, C equal to 0. Waiting for the sixth INT clock signal to arrive, D flip-flop 2 outputs Q ═ 1, i.e., a2 ═ 1. By analogy, a2 makes 0 and 1 transitions with every two INT clock signals, while the carry signal of half-adder 2 makes 0 and 1 transitions every two INT clock signals, i.e., the addend of half-adder 3 changes every two INT clock signals. Similarly, A3 changes every fourth INT clock signal and a4 changes every eight INT clock signals. Finally, the A4A3A2A1 sequentially outputs cycle 4-bit binary numbers of 0000, 0001, 0010 … … 1110, 1111, 0000 and 0001 … …, and the binary numbers are used as input codes of the decoder.

The second part of the circuit is a decoding circuit. The structure is a 4-16 decoder consisting of 4 NOT gates and 16 AND gates. A schematic diagram of the decoding circuit is shown in fig. 6. The 3-8 decoder generally has three chip selection signal input terminals of S3, S2 and S1 in addition to three input terminals of A3, A2 and A1, and a plurality of 3-8 decoders can be cascaded to expand the three chip selection signal input terminals. Although the 3-line-8-line decoder can be extended to a 4-line-16-line decoder by adopting the method, three chip selection signals of S3, S2 and S1 are required to be added, the port number of the circuit is increased, and the complexity of the circuit is increased. So the design is made with a 4-16 decoder architecture with only 4 inputs. The 4-16 decoder operates in a similar manner to the 3-8 decoder, having four input signals as a 4-bit input code, and outputting 16 output signals by decoding. The 4-bit binary number output by the input code generating circuit is used as the input end of the 4-16 decoder, and A4 is defined as high bit and A1 is defined as low bit. If A4A3A2a1 is 0000, only the output terminal Y0 finally outputs 1 and the other output terminals all output 0 through the logical operation of the not gate and the and gate. If A4A3A2a1 is 0110, only the output terminal of Y6 outputs 1, and the other output terminals all output 0, and so on. The timing diagram of the decoding circuit is shown in fig. 7.

Since the signal output by the input code generation circuit is related to the timing of the INT clock signal, the decoding circuit also decodes the signal according to the timing of the input code generation, and finally outputs the 16-channel gate switch control timing signal.

The timing diagram of the overall circuit is shown in fig. 8.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The gate switch time sequence generating circuit in the multichannel infrared detector reading circuit is characterized in that the gate switch time sequence generating circuit only has one external input signal, namely a clock signal INT,

2. The multi-channel infrared detector readout circuit of claim 1, wherein,

3. The multi-channel infrared detector readout circuit of claim 2, wherein,