CN111129153A - LDMOS (laterally diffused Metal oxide semiconductor) manufacturing method and LDMOS device - Google Patents
LDMOS (laterally diffused Metal oxide semiconductor) manufacturing method and LDMOS device Download PDFInfo
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- CN111129153A CN111129153A CN201911324628.6A CN201911324628A CN111129153A CN 111129153 A CN111129153 A CN 111129153A CN 201911324628 A CN201911324628 A CN 201911324628A CN 111129153 A CN111129153 A CN 111129153A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 229910044991 metal oxide Inorganic materials 0.000 title description 4
- 150000004706 metal oxides Chemical class 0.000 title description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 112
- 238000000034 method Methods 0.000 claims abstract description 72
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 56
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 56
- 238000002955 isolation Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 108091006146 Channels Proteins 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 4
- 230000007704 transition Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention relates to a manufacturing method of LDMOS and an LDMOS device, relating to a manufacturing process of a semiconductor integrated circuit.A silicon dioxide layer is formed on the surface of a semiconductor substrate by a thermal oxidation growth process, and the thickness of the silicon dioxide layer is set according to the thickness required by an LDMOS step oxide layer, so that the silicon dioxide layer not only serves as a transition layer between a hard mask layer and the semiconductor substrate, but also serves as the step oxide layer of the LDMOS device, and the forming process of the silicon dioxide layer is integrated in the forming process of an isolation trench, therefore, compared with the process of forming the LDMOS device in the prior art, the process of the invention is simpler and has low; and the quality of the silicon dioxide layer formed by the thermal oxidation growth process is good, so that the step oxide layer formed by the silicon dioxide layer has fewer defects, and the performance of the LDMOS device can be greatly improved.
Description
Technical Field
The invention relates to a semiconductor integrated circuit manufacturing process, in particular to a manufacturing method of an LDMOS and an LDMOS device.
Background
In the field of semiconductor technology, LDMOS (Laterally Diffused Metal oxide semiconductor) is widely used in communication semiconductor devices due to its advantages in terms of gain, linearity, switching performance, heat dissipation, etc.
The on-resistance and breakdown voltage of the LDMOS are two main parameters thereof, and there is a mutual constraint relationship therebetween. At present, in order to improve the breakdown voltage of the LDMOS, a gate field plate structure is generally adopted. The conventional gate field plate structure has three types, a step-oxide (step-oxide) structure, a LOCOS structure, and an STI structure. Specifically, referring to fig. 1a, 1b and 1c, fig. 1a is a schematic diagram of a gate field plate structure with a step oxide structure in the prior art, fig. 1b is a schematic diagram of a gate field plate structure with a LOCOS structure in the prior art, and fig. 1c is a schematic diagram of a gate field plate structure with an STI structure in the prior art. In which the path of current of the LOCOS structure of fig. 1b is not a straight line, the on-resistance becomes high compared to the step-oxide structure of fig. 1 a. In addition, the STI structure of fig. 1c is the least good in terms of quality of silicon dioxide and current path, high in on-resistance and poor in reliability.
However, although the step-oxide structure shown in fig. 1a has a short current path, the process of forming the step-oxide 101 in the prior art is complicated, and the formed step-oxide 101 has many defects, such as residual charges, which may affect the reliability of the device.
Disclosure of Invention
The invention aims to provide a manufacturing method of an LDMOS (laterally diffused metal oxide semiconductor), so that the manufacturing process is simpler, the cost is low, and the performance of an LDMOS device can be greatly improved.
The manufacturing method of the LDMOS provided by the invention comprises the following steps: s1: providing a semiconductor substrate, defining a deep well in the semiconductor substrate, and defining a drift region and a channel region in the deep well; s2: forming a silicon dioxide layer on the surface of the semiconductor substrate by a thermal oxidation growth process, wherein the thickness of the silicon dioxide layer is equal to the thickness required by the step oxide layer of the LDMOS device, and forming a hard mask layer on the silicon dioxide layer; s3: forming at least one isolation trench in the semiconductor substrate by adopting a photoetching process; s4: filling a dielectric layer in the isolation groove, performing a planarization process, and then performing an isolation groove step height adjustment process to enable the dielectric layer to be lower than the hard mask layer; s5: removing the silicon nitride layer; s6: forming photoresist on the silicon dioxide layer, forming a photoresist pattern on a region corresponding to the drift region through a photoetching exposure process, and removing the unprotected silicon dioxide layer through a photoetching process by taking the photoresist pattern as a mask; s7: removing the residual silicon dioxide layer, and removing and cleaning the photoresist; s8: growing a grid oxide layer and depositing grid polycrystalline silicon, and carrying out grid photoetching and etching processes to form a grid structure, wherein the grid structure spans across a channel region and a drift region, and the grid polycrystalline silicon spans across a step formed by the grid oxide layer and a silicon dioxide layer; and S9: and carrying out a side wall forming process of the grid structure to form a side wall, forming a source drain region and forming a contact layer of the electrode.
Furthermore, the semiconductor substrate is a silicon substrate.
Furthermore, the deep well is an N well, the drift region is an N-type drift region, and the channel region is a P-type channel region.
Furthermore, the deep well is a P-well, the drift region is a P-type drift region, and the channel region is an N-type channel region.
Further, a deposition process is used to form the hard mask layer.
Furthermore, the hard mask layer is a silicon nitride layer.
Further, the at least one isolation trench is formed by a dry etching process.
Further, the at least one isolation trench includes two isolation trenches located in the channel region and one isolation trench located in the drift region.
Furthermore, the planarization process is a chemical mechanical polishing process.
Furthermore, the dielectric layer is an insulating dielectric layer.
Furthermore, the dielectric layer is a silicon dioxide layer.
Furthermore, the height of the isolation trench step is adjusted by adopting a wet process.
Furthermore, the silicon nitride layer is removed by a wet process.
Furthermore, a wet process is used to remove the residual silicon dioxide layer.
Further, the thickness of the silicon dioxide layer formed in step S2 is greater than 200 angstroms.
The invention also provides an LDMOS device manufactured according to the manufacturing method of the LDMOS.
According to the LDMOS manufacturing method and the LDMOS device, the silicon dioxide layer is formed on the surface of the semiconductor substrate through the thermal oxidation growth process, and the thickness of the silicon dioxide layer is set according to the thickness required by the LDMOS step oxide layer, so that the silicon dioxide layer is not only used as a transition layer between the hard mask layer and the semiconductor substrate, but also can be used as the step oxide layer of the LDMOS device, and the forming process of the silicon dioxide layer is integrated in the forming process of the isolation trench, so that compared with the process for forming the LDMOS device in the prior art, the process is simpler and is low in cost; and the quality of the silicon dioxide layer formed by the thermal oxidation growth process is good, so that the step oxide layer formed by the silicon dioxide layer has fewer defects, and the performance of the LDMOS device can be greatly improved.
Drawings
Fig. 1a is a schematic diagram of a gate field plate structure with a step oxide structure in the prior art.
Fig. 1b is a schematic diagram of a gate field plate structure of a LOCOS structure in the prior art.
Fig. 1c is a schematic diagram of a gate field plate structure of a prior art STI structure.
Fig. 2 is a flowchart of a method for manufacturing an LDMOS according to an embodiment of the invention.
Fig. 3a to 3i are schematic views illustrating a process of a method for manufacturing an LDMOS according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, a method for manufacturing an LDMOS is provided. Referring to fig. 2, fig. 2 is a flowchart illustrating a method for manufacturing an LDMOS according to an embodiment of the invention, and fig. 3a to 3i are combined with fig. 3a to 3i to illustrate a process of the method for manufacturing an LDMOS according to an embodiment of the invention. Specifically, the method for manufacturing the LDMOS according to an embodiment of the present invention includes:
s1: a semiconductor substrate 100 is provided, a deep well 110 is defined in the semiconductor substrate 100, and a drift region 210 and a channel region 220 are defined in the deep well 110. Please refer to fig. 3 a;
in an embodiment of the present invention, the semiconductor substrate 100 is a silicon substrate.
S2: forming a silicon dioxide layer 120 on the surface of the semiconductor substrate by a thermal oxidation growth process, wherein the thickness of the silicon dioxide layer 120 is equal to the thickness required by the step oxide layer of the LDMOS device, and forming a hard mask layer 130 on the silicon dioxide layer 120, as shown in fig. 3 b;
in an embodiment of the present invention, the hard mask layer 130 is formed by a deposition process. In an embodiment of the present invention, the hard mask layer 130 is a silicon nitride layer.
S3: forming at least one isolation trench 230 in the semiconductor substrate 100 by using a photolithography and etching process, please refer to fig. 3 c;
in an embodiment of the present invention, the at least one isolation trench 230 is formed by a dry etching process.
In an embodiment of the present invention, the at least one isolation trench 230 includes two isolation trenches located in the channel region 220 and one isolation trench located in the drift region 210 as shown in fig. 3 c.
S4: filling a dielectric layer 240 in the isolation trench 230, performing a planarization process, and then performing an isolation trench step-height (STI step-height) adjustment process to make the dielectric layer 240 lower than the hard mask layer 130, as shown in fig. 3 d;
in an embodiment of the invention, the planarization process is a chemical mechanical polishing process. In an embodiment of the present invention, the dielectric layer 240 is an insulating dielectric layer. Specifically, in an embodiment of the present invention, the dielectric layer 240 is a silicon dioxide layer. In an embodiment of the invention, a wet process is adopted to adjust the step height of the isolation trench.
S5: removing the silicon nitride layer 130, as shown in fig. 3 e;
in an embodiment of the present invention, the silicon nitride layer 130 is removed by a wet process.
S6: forming a photoresist on the silicon dioxide layer 120, forming a photoresist pattern 310 on a region corresponding to the drift region 210 through a photolithography exposure process, and performing a photolithography etching process using the photoresist pattern 310 as a mask to remove the unprotected silicon dioxide layer 120, as shown in fig. 3 f;
s7: removing the residual silicon dioxide layer 120, and performing photoresist removal and cleaning, as shown in fig. 3 g;
in an embodiment of the invention, a wet process is used to remove the residual silicon dioxide layer.
S8: growing the gate oxide layer 122 and depositing the gate polysilicon 410, and performing gate photolithography and etching processes to form the gate structure 400, wherein the gate structure 400 crosses the channel region 220 and the drift region 210, and the gate polysilicon 410 crosses the step formed by the gate oxide layer 122 and the silicon dioxide layer 120, as shown in fig. 3 h.
S9: a sidewall formation process of the gate structure 400 is performed to form a sidewall 420, a source/drain region and a contact layer 430 for forming an electrode, as shown in fig. 3 i.
In an embodiment of the present invention, a deep well may be formed in the defined deep well 110 region by performing photolithography and ion implantation processes on the semiconductor substrate, and a drift region and a channel region may be formed in the defined drift region 210 and the channel region 220, respectively. The photolithography and ion implantation processes may be performed in one of the above steps according to the process requirements, but the invention is not limited thereto, and may be performed in step S1, or may be performed after the planarization process in step S4. In an embodiment of the present invention, the deep well 110 is an N-well, the drift region 210 is an N-type drift region, and the channel region 220 is a P-type channel region, or the deep well 110 is a P-well, the drift region 210 is a P-type drift region, and the channel region 220 is an N-type channel region, so as to form an LDNMOS device or an LDPMOS device.
In the prior art, in order to form the isolation trench 230, it is also necessary to form a silicon dioxide layer on the surface of the semiconductor substrate, and form a hard mask layer on the silicon dioxide layer, wherein the silicon dioxide layer is a transition layer between the hard mask layer and the semiconductor substrate, and the thickness of the silicon dioxide layer is generally between 100 angstroms and 150 angstroms, and the silicon dioxide layer and the hard mask layer are only auxiliary layers for forming the isolation trench 230. In the invention, a silicon dioxide layer 120 is formed on the surface of the semiconductor substrate through a thermal oxidation growth process, the thickness of the silicon dioxide layer 120 is set according to the thickness required by the LDMOS step oxide layer, generally, the thickness of the silicon dioxide layer 120 is more than 200 angstroms, for example, for an LDMOS device with a withstand voltage of 50V, the thickness of the silicon dioxide layer 120 can be set to be about 800 angstroms, and for an LDMOS device with a withstand voltage of 100V, the thickness of the silicon dioxide layer 120 can be set to be about more than 1000 angstroms, so that the silicon dioxide layer 120 in the invention not only serves as a transition layer between a hard mask layer and the semiconductor substrate, but also serves as the step oxide layer of the LDMOS device, and the formation process of the silicon dioxide layer is integrated in the formation process of the isolation trench 230, so that compared with the; and the quality of the silicon dioxide layer formed by the thermal oxidation growth process is good, so that the step oxide layer formed by the silicon dioxide layer has fewer defects, and the performance of the LDMOS device can be greatly improved.
In an embodiment of the invention, an LDMOS device manufactured by the above process is also provided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (16)
1. A method for manufacturing an LDMOS is characterized by comprising the following steps:
s1: providing a semiconductor substrate, defining a deep well in the semiconductor substrate, and defining a drift region and a channel region in the deep well;
s2: forming a silicon dioxide layer on the surface of the semiconductor substrate by a thermal oxidation growth process, wherein the thickness of the silicon dioxide layer is equal to the thickness required by the step oxide layer of the LDMOS device, and forming a hard mask layer on the silicon dioxide layer;
s3: forming at least one isolation trench in the semiconductor substrate by adopting a photoetching process;
s4: filling a dielectric layer in the isolation trench, and performing a planarization process,
then, carrying out a step height adjustment process of the isolation trench to enable the dielectric layer to be lower than the hard mask layer;
s5: removing the silicon nitride layer;
s6: forming photoresist on the silicon dioxide layer, forming a photoresist pattern on a region corresponding to the drift region through a photoetching exposure process, and removing the unprotected silicon dioxide layer through a photoetching process by taking the photoresist pattern as a mask;
s7: removing the residual silicon dioxide layer, and removing and cleaning the photoresist;
s8: growing a grid oxide layer and depositing grid polycrystalline silicon, and carrying out grid photoetching and etching processes to form a grid structure, wherein the grid structure spans across a channel region and a drift region, and the grid polycrystalline silicon spans across a step formed by the grid oxide layer and a silicon dioxide layer; and
s9: and carrying out a side wall forming process of the grid structure to form a side wall, forming a source drain region and forming a contact layer of the electrode.
2. The method of making the LDMOS of claim 1, wherein the semiconductor substrate is a silicon substrate.
3. The method of fabricating the LDMOS of claim 1, wherein the deep well is an N-well, the drift region is an N-type drift region, and the channel region is a P-type channel region.
4. The method of making the LDMOS of claim 1, wherein the deep well is a P-well, the drift region is a P-type drift region, and the channel region is an N-type channel region.
5. The method of making the LDMOS of claim 1, wherein the hard mask layer is formed by a deposition process.
6. The method of manufacturing the LDMOS as set forth in claim 1, wherein said hard mask layer is a silicon nitride layer.
7. The method of making the LDMOS of claim 1, wherein the at least one isolation trench is formed by a dry etching process.
8. The method of making an LDMOS as set forth in claim 1, wherein said at least one isolation trench comprises two isolation trenches located in the channel region and one isolation trench located in the drift region.
9. The method of fabricating the LDMOS of claim 1, wherein the planarization process is a chemical mechanical polishing process.
10. The method of making the LDMOS of claim 1, wherein the dielectric layer is an insulating dielectric layer.
11. The method of making the LDMOS of claim 1, wherein the dielectric layer is a silicon dioxide layer.
12. The method of manufacturing the LDMOS as set forth in claim 1, wherein a wet process is used to adjust the isolation trench step height.
13. The method of making the LDMOS as set forth in claim 1, wherein the silicon nitride layer is removed by a wet process.
14. The method of making the LDMOS of claim 1, wherein a wet process is used to remove the residual silicon dioxide layer.
15. The method for manufacturing the LDMOS of claim 1, wherein the thickness of the silicon dioxide layer formed in the step S2 is greater than 200 angstroms.
16. An LDMOS device, manufactured according to the method of claim 1.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090072308A1 (en) * | 2007-09-18 | 2009-03-19 | Chin-Lung Chen | Laterally diffused metal-oxide-semiconductor device and method of making the same |
| CN101625998A (en) * | 2008-07-09 | 2010-01-13 | 东部高科股份有限公司 | Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device |
| CN102931089A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华半导体有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090072308A1 (en) * | 2007-09-18 | 2009-03-19 | Chin-Lung Chen | Laterally diffused metal-oxide-semiconductor device and method of making the same |
| CN101625998A (en) * | 2008-07-09 | 2010-01-13 | 东部高科股份有限公司 | Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device |
| CN102931089A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华半导体有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) and manufacturing method thereof |
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