CN111129053B - Pixel unit structure of CMOS image sensor and forming method - Google Patents
Pixel unit structure of CMOS image sensor and forming method Download PDFInfo
- Publication number
- CN111129053B CN111129053B CN201911334323.3A CN201911334323A CN111129053B CN 111129053 B CN111129053 B CN 111129053B CN 201911334323 A CN201911334323 A CN 201911334323A CN 111129053 B CN111129053 B CN 111129053B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon substrate
- photodiode
- upper layer
- metal interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 100
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 100
- 239000010703 silicon Substances 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 230000003287 optical effect Effects 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 342
- 229910052751 metal Inorganic materials 0.000 claims description 86
- 239000002184 metal Substances 0.000 claims description 86
- 230000005540 biological transmission Effects 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 27
- 239000000725 suspension Substances 0.000 claims description 25
- 238000010521 absorption reaction Methods 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003086 colorant Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010070834 Sensitisation Diseases 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004297 night vision Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000008313 sensitization Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a pixel unit structure of a CMOS image sensor, which is arranged on an upper silicon substrate and a lower silicon substrate which are stacked up and down; the upper layer silicon substrate is provided with an upper layer photodiode, the lower layer silicon substrate is provided with a lower layer photodiode, the upper layer photodiode corresponds to the lower layer photodiode up and down, and an optical channel is arranged between the upper layer photodiode and the lower layer photodiode; wherein, the optical signals received by any pair of the upper layer photodiode and the lower layer photodiode respectively are subjected to photoelectric conversion and then are subjected to signal output through the same pixel unit. The invention realizes the interconnection between the upper pixel unit and the lower pixel unit through the hybrid bonding of the two CMOS image sensor chips, thereby utilizing the photodiodes positioned at the lower layers to collect near infrared incident light rays and improving the quantum efficiency of the pixel units.
Description
Technical Field
The invention relates to the technical field of image sensors, in particular to a pixel unit structure of a CMOS image sensor and a forming method.
Background
Image sensors refer to devices that convert optical signals into electrical signals, and typically large-scale commercial image sensor chips include two broad categories, charge Coupled Devices (CCDs) and Complementary Metal Oxide Semiconductor (CMOS) image sensor chips.
Compared with the traditional CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, compatibility with the CMOS process and the like, and therefore, the CMOS image sensor is more widely applied. CMOS image sensors are now used not only in consumer electronics, such as miniature digital cameras (DSC), cell phone cameras, video cameras and digital single contrast (DSLR), but also in automotive electronics, monitoring, biotechnology and medicine.
The pixel unit of the CMOS image sensor is a core device for realizing the sensitization of the image sensor. The most common pixel cell is an active pixel structure comprising a photodiode and a plurality of transistors. The photodiodes in the devices are photosensitive units, so that light collection and photoelectric conversion are realized, and other MOS transistors are control units, and mainly control the selection, reset, signal amplification and readout of the photodiodes.
The absorption coefficient of the silicon material for incident light decreases with increasing wavelength. Conventional pixel cells typically use filter layers for the three primary colors red, green, and blue. Wherein the wavelength of blue light is 450 nanometers, the wavelength of green light is 550 nanometers, and the wavelength of red light is 650 nanometers. Therefore, the absorption position of red light in the silicon wafer is the deepest, and the blue light is the shallowest. Blue light is absorbed at the position closest to the surface of the silicon wafer, and the absorption coefficient is the highest; red light enters the silicon wafer deepest, can enter about 2.3 microns of the silicon wafer, and has the lowest absorption coefficient; the absorption coefficient of green light is between that of blue and red light, while absorption of near infrared light requires an absorption thickness greater than 2.3 microns.
A conventional back-illuminated CMOS image sensor pixel cell is constructed as shown in fig. 1. Among them, the photodiode 13 formed in the silicon substrate 12 is a photosensitive device of a pixel unit, and blue, green, and red portions of incident light are absorbed at positions generally within 3 μm of the silicon substrate 12 due to shorter wavelengths, so that photoelectric conversion can be realized in the photodiode 13. Whereas near infrared light has a longer wavelength and therefore requires a silicon substrate thickness of greater than 3 microns to be absorbed. As shown in fig. 1, the near infrared portion (near infrared light) of the incident light will pass directly through the silicon substrate 12 and then into the interlayer dielectric 14. Since the interlayer dielectric 14 in the semiconductor process is usually made of a light-transmitting material such as silicon dioxide, the near infrared incident light will directly pass through the silicon substrate 12 and the interlayer dielectric 14 and enter the carrier 15, and normal photoelectric conversion cannot be achieved, so that the quantum efficiency is extremely low.
The depth of the photodiode 13 in the silicon substrate 12 is typically around 3 microns, and is mainly limited by the ion implantation process and the charge transfer characteristics of the pixel cell. The photodiode 13 needs to be formed by an ion implantation process, and the implantation limit depth of a typical high-energy implanter or ultra-high-energy implanter in the silicon substrate 12 is around 3 μm. Meanwhile, the charges collected in the photodiode 13 need to be output through the transfer tube 11, and when the thickness of the silicon substrate 12 of the pixel unit is greater than 3 μm, the output of the charges through the transfer tube 11 and the metal interconnection layer 10 becomes difficult, which easily causes a smear phenomenon of an image.
Meanwhile, in the application of the current security monitoring, machine vision and intelligent traffic system, the light wavelength of the infrared light supplement at night is concentrated at 850-940 nanometers, so that the conventional back-illuminated pixel unit is insensitive to the light of the wave band, and the application effect is influenced.
Therefore, new CMOS image sensor pixel cell structures and methods of formation are needed to improve the sensitivity and quantum efficiency in the near infrared band and to improve the night vision effect of the product.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a CMOS image sensor pixel unit structure and a forming method, wherein the interconnection between an upper pixel unit and a lower pixel unit is realized through the hybrid bonding of two CMOS image sensor chips, so that a photodiode positioned at the lower layer can be used for collecting near infrared incident light, and the quantum efficiency of the pixel unit is improved.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a CMOS image sensor pixel unit structure, which is arranged on an upper silicon substrate and a lower silicon substrate which are stacked up and down;
the upper layer silicon substrate is provided with an upper layer photodiode, the lower layer silicon substrate is provided with a lower layer photodiode, the upper layer photodiode corresponds to the lower layer photodiode up and down, and an optical channel is arranged between the upper layer photodiode and the lower layer photodiode; wherein, the optical signals received by any pair of the upper layer photodiode and the lower layer photodiode respectively are subjected to photoelectric conversion and then are subjected to signal output through the same pixel unit.
Further, the light channel is filled with a light-transmitting medium.
Further, an upper layer transmission transistor and an upper layer suspension drain electrode which are connected with the upper layer photodiode are arranged on the upper layer silicon substrate, and a lower layer transmission transistor and a lower layer suspension drain electrode which are connected with the lower layer photodiode are arranged on the lower layer silicon substrate; the upper layer transmission transistor is connected with the lower layer transmission transistor, the upper layer suspension drain electrode is connected with the lower layer suspension drain electrode, and photoelectric conversion signals of the upper layer photodiode and the lower layer photodiode are output through a selection transistor of a pixel unit arranged on the upper layer silicon substrate or the lower layer silicon substrate.
Further, the upper photodiode, the upper transmission transistor, the upper suspension drain and the selection transistor are arranged on the front surface of the upper silicon substrate, an upper dielectric layer is arranged on the front surface of the upper silicon substrate, and one or more upper metal interconnection layers are arranged in the upper dielectric layer; the lower photodiode, the lower transmission transistor and the lower suspension drain are arranged on the front surface of the lower silicon substrate, a lower layer interlayer dielectric layer is arranged on the front surface of the lower silicon substrate, and one to more lower metal interconnection layers are arranged in the lower layer interlayer dielectric layer; the upper layer interlayer dielectric layer is connected with the lower layer interlayer dielectric layer, the upper layer metal interconnection layer is connected with the lower layer metal interconnection layer, the upper layer transmission transistor is connected with the lower layer transmission transistor through the upper layer metal interconnection layer and the lower layer metal interconnection layer, and the upper layer suspension drain is connected with the lower layer suspension drain through the upper layer metal interconnection layer and the lower layer metal interconnection layer.
Further, the upper interlayer dielectric layer and the lower interlayer dielectric layer are connected through bonding, the upper metal interconnection layer and the lower metal interconnection layer are connected through bonding, the upper silicon substrate and the lower silicon substrate are connected through bonding of the upper interlayer dielectric layer and the lower interlayer dielectric layer and bonding of the upper metal interconnection layer and the lower metal interconnection layer.
Further, the upper metal interconnection layer is provided with an upper bonding point, the lower metal interconnection layer is provided with a lower bonding point, and the upper metal interconnection layer and the lower metal interconnection layer are connected through bonding between the upper bonding point and the lower bonding point.
Further, the surface of the upper bonding point is flush with the surface of the upper dielectric layer, and the surface of the lower bonding point is flush with the surface of the lower dielectric layer.
Further, the upper metal interconnection layer and the lower metal interconnection layer are respectively arranged in the upper layer interlayer dielectric layer and the lower layer interlayer dielectric layer outside the optical channel.
Further, the area of the upper layer photodiode is equal to the area of the lower layer photodiode.
A method for forming a pixel unit structure of a CMOS image sensor comprises the following steps:
providing an upper layer silicon substrate, and forming an upper layer photodiode, an upper layer transmission transistor and a selection transistor on the front surface of the upper layer silicon substrate;
forming an upper layer dielectric layer on the front surface of the upper silicon substrate, forming one to more upper metal interconnection layers in the upper layer dielectric layer, and forming upper bonding points on the surface of the uppermost upper metal interconnection layer;
providing a lower silicon substrate, and forming a lower photodiode and a lower transmission transistor on the front surface of the lower silicon substrate;
forming a lower layer laminated dielectric layer on the front surface of the lower silicon substrate, forming one to more lower metal interconnection layers in the lower laminated dielectric layer, and forming lower bonding points on the surface of the uppermost lower metal interconnection layer;
inverting the upper silicon substrate, aligning the upper dielectric layer with the lower dielectric layer, and aligning the upper bonding point with the lower bonding point for bonding;
and thinning the back surface of the upper silicon substrate.
According to the technical scheme, the near infrared incident light is collected through stacking of the upper pixel units and the lower pixel units, and after the near infrared incident light penetrates through the upper photodiode, the near infrared incident light finally reaches the photodiode in the lower pixel unit and realizes photoelectric conversion due to the fact that the interlayer medium which is completely transparent is arranged below the upper photodiode, so that the near infrared quantum efficiency is improved. Meanwhile, the upper pixel unit and the lower pixel unit are used as a pixel unit to work simultaneously, so that the transmission tube and the suspension drain electrode of the upper pixel unit and the lower pixel unit are electrically connected through the metal interconnection layer and the upper and lower bonding points, and finally signals after the upper pixel unit and the lower pixel unit are combined are controlled by the selection transistor in the upper pixel unit to realize the output of voltage signals to the peripheral circuit.
Drawings
Fig. 1 is a schematic diagram of a pixel unit structure of a conventional back-illuminated CMOS image sensor.
Fig. 2 is a schematic diagram of a pixel unit structure of a CMOS image sensor according to a preferred embodiment of the invention.
Fig. 3 to fig. 7 are schematic views illustrating a method for forming a pixel unit structure of a CMOS image sensor according to a preferred embodiment of the invention.
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale, and the structures in the drawings are partially enlarged, deformed, and simplified, so that the present invention should not be construed as being limited thereto.
In the following detailed description of the invention, please refer to fig. 2, fig. 2 is a schematic diagram of a pixel unit structure of a CMOS image sensor according to a preferred embodiment of the invention. As shown in fig. 2, a CMOS image sensor pixel cell structure of the present invention is provided on two upper silicon substrates 20 and a lower silicon substrate 30 stacked one above the other. The upper and lower silicon substrates 20 and 30 may employ silicon wafers, but are not limited thereto.
Please refer to fig. 2. An upper layer pixel unit array formed by densely arranging a plurality of upper layer pixel units is arranged on the upper layer silicon substrate 20; each upper pixel cell may include an upper photodiode 25, an upper transfer transistor 24, and an upper floating drain 23 disposed on the front side of the upper silicon substrate 20. A lower layer pixel unit array formed by densely arranging a plurality of lower layer pixel units is arranged on the lower layer silicon substrate 30; each of the lower pixel cells may include a lower photodiode 33, a lower transfer transistor 34, and a lower floating drain 35 disposed on the front side of the lower silicon substrate 30.
Each upper pixel unit further includes a selection transistor 22 provided on the front surface of the upper silicon substrate 20, and a signal output point 21 connected to the selection transistor 22.
Please refer to fig. 2. An upper dielectric layer 28 may be disposed on the front surface of the upper silicon substrate 20, and one or more upper metal interconnect layers 26, such as the illustrated two upper metal interconnect layers 26, may be disposed in the upper dielectric layer 28. An underlying dielectric layer 36 may be provided on the front surface of the underlying silicon substrate 30, with one or more underlying metal interconnect layers 32, such as the illustrated two underlying metal interconnect layers 32, being provided in the underlying dielectric layer 36.
Please refer to fig. 2. The upper layer pixel units are correspondingly arranged with the lower layer pixel units. The area of the upper photodiode 25 and the area of the lower photodiode 33 may be identical, and the positions thereof may be vertically corresponding. An optical channel is provided between the upper layer photodiode 25 and the lower layer photodiode 33; the upper dielectric layer 28 and the lower dielectric layer 36 may be made of materials such as silicon dioxide, and may be used as a light-transmitting medium filled in the optical channel, and the upper metal interconnect layer 26 and the lower metal interconnect layer 32 are respectively disposed in the upper dielectric layer 28 and the lower dielectric layer 36 outside the optical channel.
In the upper pixel unit, an upper photodiode 25 is connected to an upper transfer transistor 24, an upper floating drain 23, and a selection transistor 22; in the lower pixel unit, the lower photodiode 33 is connected to the lower transfer transistor 34 and the lower floating drain 35.
And, the upper dielectric layer 28 is connected with the lower dielectric layer 36, and the upper metal interconnection layer 26 is connected with the lower metal interconnection layer 32; the upper layer transmission transistor 24 is electrically connected with the lower layer transmission transistor 34 through the upper layer metal interconnection layer 26 and the lower layer metal interconnection layer 32, and the upper layer transmission transistor 24 and the lower layer transmission transistor 34 can be simultaneously turned on and off through peripheral voltage timing control; similarly, the upper floating drain 23 is electrically connected to the lower floating drain 35 through the upper metal interconnect layer 26 and the lower metal interconnect layer 32, and the charge signals transferred through the upper transfer transistor 24 and the lower transfer transistor 34 are converted to final voltage values at the upper floating drain 23 and the lower floating drain 35, respectively. The signal output points 21 are connected to peripheral circuits through the upper metal interconnection layer 26.
Since the absorption capacity of incident light is directly related to the thickness of the silicon substrate, near infrared light is absorbed to a depth far greater than that of conventional blue-green-red colors due to the longer wavelength. In order to enhance the absorption capability of the pixel unit near infrared light, the near infrared incident light passing through the silicon substrate needs to be collected.
The invention realizes the collection of near infrared incident light through the stacking of the upper and lower pixel units, and utilizes any pair of upper photodiodes 25 and lower photodiodes 33 on the upper and lower layers to respectively receive optical signals with different wavelengths. For example, the upper photodiode 25 may be used to receive visible light such as red, green, blue, etc. light in the incident light, and the lower photodiode 33 may be used to receive near infrared light in the incident light. After the near infrared incident light penetrates the upper layer photodiode 25, since an interlayer medium that is completely transparent is under the upper layer photodiode 25, the near infrared incident light finally reaches the lower layer photodiode 33 and photoelectric conversion is achieved, thereby improving the quantum efficiency of near infrared.
Meanwhile, the upper and lower pixel units need to operate as one pixel unit at the same time, so that electrical connection is realized between the upper layer transmission transistor 24 and the lower layer transmission transistor 34, between the upper layer floating drain 23 and the lower layer floating drain 35 of the upper and lower pixel units through bonding of the upper layer metal interconnection layer 26 and the lower layer metal interconnection layer 32, and signals after the upper layer pixel unit and the lower layer pixel unit are combined are finally output to a peripheral circuit through control of the selection transistor 22 and output of the signal output point 21 arranged in the upper layer pixel unit. That is, the photoelectric converted signals of the upper-layer photodiode 25 and the lower-layer photodiode 33 are outputted through the same pixel unit.
It can be seen that in the above pixel unit structure of the present invention, the upper pixel unit and the lower pixel unit share one selection transistor 22 and one signal output point 21 provided in the upper pixel unit. Therefore, the arrangement of the selection transistor and the signal output point in the lower pixel unit can be omitted, so that the saved area can be utilized, and more other device structures can be arranged, and the application value of the image sensor is obviously improved.
Please refer to fig. 2. The upper dielectric layer 28 and the lower dielectric layer 36 are connected by bonding, and the upper metal interconnect layer 26 and the lower metal interconnect layer 32 are connected by bonding. In this way, the upper silicon substrate 20 and the lower silicon substrate 30 are bonded together by bonding the upper dielectric layer 28 and the lower dielectric layer 36, and bonding the upper metal interconnect layer 26 and the lower metal interconnect layer 32, so as to form a hybrid bond, thereby realizing the connection between the upper silicon substrate 20 and the lower silicon substrate 30.
Further, an upper bonding point 27 may be provided on a surface of a second one of the upper metal interconnect layers 26; meanwhile, an under-layer bonding point 31 may be provided on a surface of a second one of the under-layer metal interconnection layers 32. The surface of the upper bond site 27 is flush with the surface of the upper dielectric layer 28 and the surface of the lower bond site 31 is flush with the surface of the lower dielectric layer 36. The upper metal interconnect layer 26 is connected to the lower metal interconnect layer 32 by bonding at an upper bond site 27 to a lower bond site 31.
A method for forming a pixel cell structure of a CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 3-7, fig. 3-7 are schematic views illustrating a method for forming a pixel unit structure of a CMOS image sensor according to a preferred embodiment of the invention. As shown in fig. 3-7, a method for forming a pixel unit structure of a CMOS image sensor according to the present invention can be used to manufacture the above-mentioned pixel unit structure of a CMOS image sensor such as that of fig. 2. The invention relates to a method for forming a pixel unit structure of a CMOS image sensor, which comprises the following steps:
first, as shown in fig. 3, one silicon wafer substrate may be used as the upper silicon substrate 20, and a CMOS image sensor process flow may be used, forming an upper photodiode 25, an upper transfer transistor 24, an upper floating drain 23, and a selection transistor 22, a signal output point 21 on the front side of the upper silicon substrate 20.
Next, an upper dielectric layer 28 is deposited on the front surface of the upper silicon substrate 20, and two upper metal interconnect layers 26, for example, as shown, are formed in the upper dielectric layer 28. Wherein upper layer bond sites 27 for subsequent upper and lower layer metal bonding may be formed by chemical mechanical polishing on the surface of the second upper layer metal interconnect layer 26.
Also, as shown in fig. 4, another silicon wafer substrate is used as the lower silicon substrate 30, and a CMOS image sensor process flow may be used, forming a lower photodiode 33, a lower transfer transistor 34, and a lower floating drain 35 on the front side of the lower silicon substrate 30. An underlying dielectric layer 36 is then deposited on the front surface of the underlying silicon substrate 30, and two underlying metal interconnect layers 32, such as those illustrated, are formed in the underlying dielectric layer 36. Wherein the underlying bond sites 31 for subsequent upper and lower metal bonding may be formed by chemical mechanical polishing on the surface of the second underlying metal interconnect layer 32.
In order to ensure that near infrared light can fully reach the lower layer photodiode 33, the layout design can be adopted to ensure that the metal interconnection structure is not arranged below the upper layer photodiode 25 and above the lower layer photodiode 33, so that the reflection and refraction of the metal layer on incident near infrared light are prevented.
Next, as shown in fig. 5, the upper silicon substrate 20 is inverted, the upper dielectric layer 28 is aligned with the lower dielectric layer 36, and the upper bonding points 27 are aligned with the lower bonding points 31, and hybrid bonding is performed on the upper silicon substrate 20 and the lower silicon substrate 30. Wherein the upper dielectric layer 28 and the lower dielectric layer 36, and the upper bonding point 27 and the lower bonding point 31 are connected by annealing.
Next, as shown in fig. 6, the back surface of the upper silicon substrate 20 is thinned. The thinned upper silicon substrate 20 has a thickness of about 3 microns as is conventional.
Finally, as shown in fig. 7, an anti-reflection layer 41 may be deposited on the surface of the upper silicon substrate 20 using a backside process, and a metal light blocking layer 42 may be formed on the back surface of the upper silicon substrate 20 by deposition of metal materials such as aluminum, tungsten, and copper, photolithography, etching, and the like.
According to the invention, through stacking the upper layer of pixel units and the lower layer of pixel units, the collection of near infrared rays is realized in the lower layer of pixel units, so that the near infrared quantum efficiency of the pixel units is enhanced.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all the equivalent structural changes made in the description and drawings of the present invention are included in the scope of the invention.
Claims (8)
1. The pixel unit structure of the CMOS image sensor is characterized by being arranged on an upper silicon substrate and a lower silicon substrate which are stacked up and down;
the upper layer silicon substrate is provided with an upper layer photodiode, the lower layer silicon substrate is provided with a lower layer photodiode, the upper layer photodiode corresponds to the lower layer photodiode up and down, and an optical channel is arranged between the upper layer photodiode and the lower layer photodiode; wherein, the optical signals received by any pair of the upper layer photodiode and the lower layer photodiode respectively are subjected to photoelectric conversion and then are subjected to signal output through the same pixel unit;
an upper layer transmission transistor and an upper layer suspension drain electrode which are connected with the upper layer photodiode are arranged on the upper layer silicon substrate, and a lower layer transmission transistor and a lower layer suspension drain electrode which are connected with the lower layer photodiode are arranged on the lower layer silicon substrate; the upper layer transmission transistor is connected with the lower layer transmission transistor, the upper layer suspension drain electrode is connected with the lower layer suspension drain electrode, and photoelectric conversion signals of the upper layer photodiode and the lower layer photodiode are output through a selection transistor of a pixel unit arranged on the upper layer silicon substrate or the lower layer silicon substrate;
the upper layer photodiode, the upper layer transmission transistor, the upper layer suspension drain electrode and the selection transistor are arranged on the front surface of the upper layer silicon substrate, an upper layer interlayer dielectric layer is arranged on the front surface of the upper layer silicon substrate, and one to a plurality of upper layer metal interconnection layers are arranged in the upper layer interlayer dielectric layer; the lower photodiode, the lower transmission transistor and the lower suspension drain are arranged on the front surface of the lower silicon substrate, a lower layer interlayer dielectric layer is arranged on the front surface of the lower silicon substrate, and one to more lower metal interconnection layers are arranged in the lower layer interlayer dielectric layer; the upper layer interlayer dielectric layer is connected with the lower layer interlayer dielectric layer, the upper layer metal interconnection layer is connected with the lower layer metal interconnection layer, the upper layer transmission transistor is connected with the lower layer transmission transistor through the upper layer metal interconnection layer and the lower layer metal interconnection layer, and the upper layer suspension drain is connected with the lower layer suspension drain through the upper layer metal interconnection layer and the lower layer metal interconnection layer.
2. The CMOS image sensor pixel cell structure of claim 1, wherein the optical channel is filled with a light transmissive medium.
3. The CMOS image sensor pixel cell structure of claim 1, wherein the upper dielectric layer and the lower dielectric layer are connected by bonding, the upper metal interconnect layer and the lower metal interconnect layer are connected by bonding, the upper silicon substrate and the lower silicon substrate are connected by bonding the upper dielectric layer and the lower dielectric layer, and the upper metal interconnect layer and the lower metal interconnect layer are connected by bonding.
4. The CMOS image sensor pixel cell structure of claim 3, wherein the upper metal interconnect layer is provided with an upper bonding point, the lower metal interconnect layer is provided with a lower bonding point, and the upper metal interconnect layer and the lower metal interconnect layer are connected through bonding between the upper bonding point and the lower bonding point.
5. The CMOS image sensor pixel cell structure of claim 4, wherein the surface of the upper bond site is flush with the surface of the upper dielectric layer and the surface of the lower bond site is flush with the surface of the lower dielectric layer.
6. The CMOS image sensor pixel cell structure of claim 1, wherein the upper metal interconnect layer and the lower metal interconnect layer are disposed in the upper dielectric layer and the lower dielectric layer, respectively, outside the optical channel.
7. The CMOS image sensor pixel cell structure of claim 1, wherein the area of the upper photodiode is equal to the area of the lower photodiode.
8. The method for forming the pixel unit structure of the CMOS image sensor is characterized by comprising the following steps of:
providing an upper layer silicon substrate, and forming an upper layer photodiode, an upper layer transmission transistor and a selection transistor on the front surface of the upper layer silicon substrate;
forming an upper layer dielectric layer on the front surface of the upper silicon substrate, forming one to more upper metal interconnection layers in the upper layer dielectric layer, and forming upper bonding points on the surface of the uppermost upper metal interconnection layer;
providing a lower silicon substrate, and forming a lower photodiode and a lower transmission transistor on the front surface of the lower silicon substrate;
forming a lower layer laminated dielectric layer on the front surface of the lower silicon substrate, forming one to more lower metal interconnection layers in the lower laminated dielectric layer, and forming lower bonding points on the surface of the uppermost lower metal interconnection layer;
inverting the upper silicon substrate, aligning the upper dielectric layer with the lower dielectric layer, and aligning the upper bonding point with the lower bonding point for bonding; the upper layer silicon substrate is provided with an upper layer transmission transistor and an upper layer suspension drain electrode which are connected with the upper layer photodiode, and the lower layer silicon substrate is provided with a lower layer transmission transistor and a lower layer suspension drain electrode which are connected with the lower layer photodiode; the upper layer transmission transistor is connected with the lower layer transmission transistor, the upper layer suspension drain electrode is connected with the lower layer suspension drain electrode, and photoelectric conversion signals of the upper layer photodiode and the lower layer photodiode are output through a selection transistor of a pixel unit arranged on the upper layer silicon substrate or the lower layer silicon substrate; the upper layer photodiode, the upper layer transmission transistor, the upper layer suspension drain electrode and the selection transistor are arranged on the front surface of the upper layer silicon substrate, an upper layer interlayer dielectric layer is arranged on the front surface of the upper layer silicon substrate, and one to a plurality of upper layer metal interconnection layers are arranged in the upper layer interlayer dielectric layer; the lower photodiode, the lower transmission transistor and the lower suspension drain are arranged on the front surface of the lower silicon substrate, a lower layer interlayer dielectric layer is arranged on the front surface of the lower silicon substrate, and one to more lower metal interconnection layers are arranged in the lower layer interlayer dielectric layer; the upper layer interlayer dielectric layer is connected with the lower layer interlayer dielectric layer, the upper layer metal interconnection layer is connected with the lower layer metal interconnection layer, the upper layer transmission transistor is connected with the lower layer transmission transistor through the upper layer metal interconnection layer and the lower layer metal interconnection layer, and the upper layer suspension drain is connected with the lower layer suspension drain through the upper layer metal interconnection layer and the lower layer metal interconnection layer;
and thinning the back surface of the upper silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911334323.3A CN111129053B (en) | 2019-12-23 | 2019-12-23 | Pixel unit structure of CMOS image sensor and forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911334323.3A CN111129053B (en) | 2019-12-23 | 2019-12-23 | Pixel unit structure of CMOS image sensor and forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111129053A CN111129053A (en) | 2020-05-08 |
| CN111129053B true CN111129053B (en) | 2023-09-26 |
Family
ID=70501346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911334323.3A Active CN111129053B (en) | 2019-12-23 | 2019-12-23 | Pixel unit structure of CMOS image sensor and forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111129053B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113491011A (en) * | 2020-07-31 | 2021-10-08 | 深圳市大疆创新科技有限公司 | Image sensor, method of manufacturing the same, and imaging device having image sensor mounted thereon |
| WO2023272572A1 (en) * | 2021-06-30 | 2023-01-05 | Huawei Technologies Co., Ltd. | Photoelectric conversion element and solid-state image sensing device |
| CN116093022B (en) * | 2023-04-10 | 2024-05-10 | 北京华封集芯电子有限公司 | Chip and chip design method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066086A (en) * | 2012-12-18 | 2013-04-24 | 上海集成电路研发中心有限公司 | Complementary metal-oxide-semiconductor transistor (CMOS) image sensor pixel array and manufacturing method of the same |
| CN105609513A (en) * | 2015-10-29 | 2016-05-25 | 上海集成电路研发中心有限公司 | Double-surface CMOS image sensor chip and manufacture method thereof |
| CN108110017A (en) * | 2016-11-24 | 2018-06-01 | 比亚迪股份有限公司 | Combined pixel cell and preparation method thereof, pel array and its application |
| CN109411492A (en) * | 2018-09-26 | 2019-03-01 | 上海集成电路研发中心有限公司 | A kind of stack image sensor pixel structure and preparation method |
-
2019
- 2019-12-23 CN CN201911334323.3A patent/CN111129053B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066086A (en) * | 2012-12-18 | 2013-04-24 | 上海集成电路研发中心有限公司 | Complementary metal-oxide-semiconductor transistor (CMOS) image sensor pixel array and manufacturing method of the same |
| CN105609513A (en) * | 2015-10-29 | 2016-05-25 | 上海集成电路研发中心有限公司 | Double-surface CMOS image sensor chip and manufacture method thereof |
| CN108110017A (en) * | 2016-11-24 | 2018-06-01 | 比亚迪股份有限公司 | Combined pixel cell and preparation method thereof, pel array and its application |
| CN109411492A (en) * | 2018-09-26 | 2019-03-01 | 上海集成电路研发中心有限公司 | A kind of stack image sensor pixel structure and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111129053A (en) | 2020-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11094729B2 (en) | Semiconductor device and method of manufacturing the same, and electronic apparatus | |
| CN106229322B (en) | A kind of back-illuminated stack overall situation exposing pixels cellular construction and forming method thereof | |
| JP6259418B2 (en) | Back-illuminated image sensor device integrated vertically | |
| US9406711B2 (en) | Apparatus and method for backside illuminated image sensors | |
| US7709872B2 (en) | Methods for fabricating image sensor devices | |
| CN107302008B (en) | Back-illuminated pixel unit structure for enhancing near-infrared photosensitive property and forming method | |
| CN111129053B (en) | Pixel unit structure of CMOS image sensor and forming method | |
| CN107240593B (en) | Stacked global exposure pixel unit structure and forming method thereof | |
| EP1886346A2 (en) | An imaging device having a pixel cell with a transparent conductive interconnect line and the method of making the pixel cell | |
| CN107195648B (en) | Low-noise high-sensitivity global pixel unit structure and forming method thereof | |
| CN108847418A (en) | A kind of image sensor structure and forming method enhancing near-infrared quantum efficiency | |
| CN108305885B (en) | Pixel cell and method of forming the same and imaging system assembly for digital camera | |
| CN109411492B (en) | Stacked image sensor pixel structure and preparation method | |
| US20180342543A1 (en) | Backside illuminated cmos image sensor and method of fabricating the same | |
| JP2015037121A (en) | Solid state image pickup element | |
| CN109509763B (en) | Image sensor pixel unit structure for improving quantum efficiency and forming method | |
| US8951826B2 (en) | Method for increasing photodiode full well capacity | |
| CN105762160B (en) | Back-illuminated global pixel unit structure and preparation method thereof | |
| CN115513230A (en) | Image sensor and manufacturing method thereof | |
| CN107845651A (en) | Imaging sensor and forming method thereof | |
| CN110021618B (en) | Image sensor and manufacturing method thereof | |
| CN109360834B (en) | Stacked image sensor pixel structure and preparation method | |
| CN112992954A (en) | CMOS image sensor and method of manufacturing the same | |
| CN215988760U (en) | Image sensor with a plurality of pixels | |
| CN219040482U (en) | Image sensor and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |