CN116093022B - Chip and chip design method - Google Patents
Chip and chip design method Download PDFInfo
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- CN116093022B CN116093022B CN202310369319.0A CN202310369319A CN116093022B CN 116093022 B CN116093022 B CN 116093022B CN 202310369319 A CN202310369319 A CN 202310369319A CN 116093022 B CN116093022 B CN 116093022B
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000013461 design Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 96
- 239000002184 metal Substances 0.000 claims abstract description 96
- 239000010410 layer Substances 0.000 claims abstract description 60
- 230000008054 signal transmission Effects 0.000 claims abstract description 15
- 239000002344 surface layer Substances 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims 2
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the invention provides a chip and a chip design method, wherein the chip comprises the following components: a base layer (101); a metal layer (102) disposed on the base layer (101), the metal layer (102) comprising at least a surface layer metal (105) and a bottom layer metal (106); a plurality of connection points (103) provided on the surface metal (105); and pin wells (104) are arranged on the bottom metal (106) and are communicated with part of the connecting points (103) in a one-to-one correspondence manner, and the pin wells (104) comprise a plurality of pins (107) which are communicated longitudinally in sequence. The invention effectively reduces the distance of outward signal transmission of the chip by arranging the pin well, provides a high-speed channel for signal transmission, and can effectively transmit high-speed signals when integrating a plurality of chips.
Description
Technical Field
The invention relates to the field of chips, in particular to a chip and a chip design method.
Background
With the development of the age, higher demands are being placed on integration density and memory bandwidth in chip design, where, for example, the chip needs to be connected to multiple DRAM or radio frequency chips, which increases the amount of data transmission between chips. The prior art mainly meets application requirements by increasing the pins of the chip, but the simple increase of the number of the pins greatly increases the manufacturing cost of the chip, even increases the area of the chip, and influences the integration level of the chip.
Disclosure of Invention
An objective of an embodiment of the present invention is to provide a chip and a method for designing a chip, which are used for at least partially solving the above technical problems.
In order to achieve the above object, an embodiment of the present invention provides a chip including: a base layer; the metal layer is arranged on the substrate layer and at least comprises surface layer metal and bottom layer metal; a plurality of connection points disposed on the skin metal; and the pin wells are arranged on the bottom metal and are communicated with part of the connecting points in a one-to-one correspondence manner, and the pin wells comprise a plurality of pins which are communicated longitudinally in sequence.
Optionally, the pins are of a perforated structure; the pin wells are communicated with the surface layer metal and the bottom layer metal.
Optionally, the difference in length between any two pins in the pin well is less than 10%.
Optionally, the pin shaft is provided with a driving gate circuit or a receiving gate circuit.
Optionally, the pin well is perpendicular to the surface metal.
On the other hand, the invention also provides a chip design method, which comprises the following steps: providing a substrate layer; a metal layer is arranged on the basal layer, and the metal layer at least comprises surface metal and bottom metal; and disposing a plurality of connection points on the surface metal; the bottom metal is provided with pin wells which are perpendicular to the surface metal and are communicated with part of the connecting points in a one-to-one correspondence manner, and the pin wells comprise a plurality of sequentially longitudinally communicated pins.
Optionally, the pins are of a perforated structure; the pin wells are communicated with the surface layer metal and the bottom layer metal.
Optionally, the difference in length between any two pins in the pin well is less than 10%.
Optionally, the pin shaft is provided with a driving gate circuit or a receiving gate circuit.
Optionally, the pin well is perpendicular to the surface metal.
The chip of the invention comprises: a base layer; the metal layer is arranged on the substrate layer and at least comprises surface layer metal and bottom layer metal; a plurality of connection points disposed on the skin metal; and the pin wells are arranged on the bottom metal and are communicated with part of the connecting points in a one-to-one correspondence manner, and the pin wells comprise a plurality of pins which are communicated longitudinally in sequence.
The invention provides a high-speed channel for signal transmission by arranging the pin wells, effectively reduces the distance of signal transmission between chips, reduces the area of the chips and increases the integration level of the chips.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIGS. 1a and 1b are schematic diagrams of a chip of the present invention;
FIG. 2 is a schematic diagram of a pin well of the present invention;
FIG. 3 is a schematic diagram of another pin well of the present invention;
FIG. 4 is a schematic diagram of an embodiment of a chip of the invention;
FIGS. 5a and 5b are schematic illustrations of embodiments of a pin well of the present invention;
fig. 6 is a flow chart of a method for designing a chip according to the present invention.
Description of the reference numerals
101-A substrate layer;
102-a metal layer;
103-connection point;
104-pin wells;
105-surface layer metal;
106-underlying metal;
107-pin.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Fig. 1a and 1b are schematic diagrams of a chip of the present invention, and fig. 2 is a schematic diagram of a pin well of the present invention. Referring to fig. 1 and 2, the location of the pin well is determined according to design, and the chip of the present invention includes: a base layer 101; a metal layer 102 disposed on the base layer 101, the metal layer 102 including at least a surface layer metal 105 and a bottom layer metal 106; a plurality of connection points 103 provided on the surface metal 105; and the pin wells 104 are arranged on the bottom metal 106 and are communicated with the partial connection points 103 in a one-to-one correspondence manner, the pin wells 104 comprise a plurality of pins 107 which are sequentially and longitudinally communicated, and the material of the pins 107 is preferably a metal material.
Specifically, the material of the base layer 101 may be silicon or other semiconductor materials, and is mainly used for transistors, such as a driving gate and a receiving gate, that form an underlying circuit. The metal layer 102 may be made of different metals such as copper, aluminum, titanium, etc. according to the transistor design and signal transmission requirements, wherein the surface metal 105 is made of copper, aluminum, titanium, or a multilayer structure made of other metals, the bottom metal 106 is made of a multilayer metal structure matched with the different transistor designs, the surface metal 105 is connected with the bottom metal 106, and the bottom metal 106 is connected with the base layer 101. The metal layer 102 is used for providing signal transmission, triode power supply and the like, the surface layer metal 105 is used for providing connection with other chips, and the bottom layer metal 106 is used for designing different gates. The surface metal 105 of the chip is provided with a plurality of connection points 103, and the connection points 103 are made of copper, nickel, tin, silver or other metals and are used for connecting other chips or intermediaries.
The chip is also provided with at least one pin well 104, the pin wells 104 are arranged on the bottom metal 106 and are communicated with part of the connecting points 103 in a one-to-one correspondence manner, and each pin well 104 comprises a plurality of pins 107 which are communicated longitudinally in sequence. The pin wells 104 may be placed at appropriate positions according to specific needs, as shown in fig. 1a, where the pin wells 104 of the chip are disposed at a central portion of the chip, as shown in fig. 1b, and the pin wells 104 of the chip are disposed at one side of the chip, and as shown in fig. 1a and fig. 1b, the wiring of the chip in the pin wells 104 is in a vertical direction, such as a downward straight line wiring or a downward step distribution, and the peripheral wiring of the chip needs to bypass the pin wells in each layer of metal, such as a Z-type lateral layer-changing distribution.
According to a specific embodiment, the pins 107 are of a multi-layer stacked hole design. Each metal layer is connected by a via, which may be a vertical connection to connect the underlying metal 106 to the surface connection point at the shortest wire distance, which may enable the shortest wires to achieve the greatest bandwidth, or a staggered vertical connection, which may increase the wire length by a small amount, but may reduce pin stress and improve reliability (as shown in fig. 3).
As shown in fig. 4, chip 1 and chip 2 communicate vertically through pin well 104. And, the connection mode of the specific pin wells 104 is shown in fig. 5a or fig. 5b, where fig. 5a is a structure in which two chips are directly connected through two pin wells, and the connection mode makes the distance between the driving gate and the receiving gate smaller than 0.1mm. In fig. 5b, two chips are connected via the substrate or interposer and then via two pin wells 104. The pin wells 104 are perpendicular to the surface metal 105, and signal transmission between the chips of the pin wells 104 can be realized if a substrate is used, so that the total length from the driving gate to the receiving gate is less than 1mm. The total length of pins 107 in the same pin well 104 is very close, which ensures a high degree of synchronization in the signal transmission process in the chip, reducing the signal-to-noise ratio loss of the signal line and the reference line due to the difference.
The bottom of the pin well 104 is provided with a drive gate or a receiving gate, as illustrated in fig. 5 a. The driving gate is a circuit for providing a signal transmission and an amplified signal, and the receiving gate is a circuit for receiving a signal and an amplified signal. The drive/receive gates are implemented in the underlying metal 106. The pin well 104 is provided with a connecting wire and metal for connecting the driving/receiving gate and the surface metal 105.
The chip of the invention can effectively reduce the distance between the driving gate and the receiving gate in the chip by arranging the pin well 104, reduce the Resistance Capacitance (RC) of the chip pin, not only improve the bandwidth and the speed of signal transmission, but also reduce the attenuation of data signals, and realize the high fidelity of chip communication.
The invention also provides a chip design method, as shown in fig. 6, which comprises the following steps:
Step S401: providing a base layer 101;
Step S402: providing a metal layer 102 on the base layer 101, wherein the metal layer 102 at least comprises a surface metal 105 and a bottom metal 106;
Step S403: providing a plurality of connection points 103 on the surface layer metal 105;
step S404: the bottom metal 106 is provided with pin wells 104 which are perpendicular to the surface metal 105 and are in one-to-one correspondence with the partial connection points 103, and the pin wells 104 comprise a plurality of sequentially longitudinally communicated pins 107. The specific preparation process comprises dielectric layer photoetching, sputtering, gluing, metal layer photoetching, electroplating, photoresist removing, chemical mechanical polishing and the like.
The chip of the invention comprises: a base layer 101; a metal layer 102 disposed on the base layer 101, the metal layer 102 including at least a surface layer metal 105 and a bottom layer metal 106; a plurality of connection points 103 provided on the surface metal 105; and the pin wells 104 are arranged on the bottom metal 106 and are communicated with part of the connection points 103 in a one-to-one correspondence manner, and the pin wells 104 comprise a plurality of pins 107 which are communicated longitudinally in sequence. The invention provides a high-speed channel for signal transmission by arranging the pin wells 104, effectively reduces the distance between pins in the chip, reduces the area of the chip and increases the integration level of the chip.
The foregoing details of the optional implementation of the embodiment of the present invention have been described in conjunction with the accompanying drawings, but the embodiment of the present invention is not limited to the specific details of the foregoing implementation, and various simple modifications may be made to the technical solution of the embodiment of the present invention within the scope of the technical concept of the embodiment of the present invention, where all the simple modifications belong to the protection scope of the embodiment of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, various possible combinations of embodiments of the present invention are not described in detail.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (8)
1. A chip, the chip comprising:
a base layer (101);
A metal layer (102) disposed on the base layer (101), the metal layer (102) comprising at least a surface layer metal (105) and a bottom layer metal (106);
a plurality of connection points (103) provided on the surface metal (105); and
The pin wells (104) are arranged on the bottom metal (106) and are communicated with part of the connection points (103) in a one-to-one correspondence manner and are used for providing signal transmission channels, and the pin wells (104) comprise a plurality of pins (107) which are communicated longitudinally in sequence;
The pin well (104) is provided with a driving gate circuit or a receiving gate circuit;
the pin well (104) is internally provided with a connecting wire and metal, and is used for connecting the surface metal (105) with a driving gate circuit or a receiving gate circuit;
The chip comprises a plurality of pin wells (104), the total length of pins (107) in the pin wells (104) is close, so that chip signal transmission is synchronous;
the pins (107) are of a multi-layer stacked hole design;
the pins (107) are connected in staggered vertical communication, and the central axes of adjacent pins (107) are not overlapped.
2. The chip of claim 1, wherein the chip comprises a plurality of chips,
-The pins (107) are of perforated construction;
The pin well (104) is communicated with the surface layer metal (105) and the bottom layer metal (106).
3. The chip of claim 1, wherein the chip comprises a plurality of chips,
The difference in length between any two pins (107) in the pin well (104) is less than 10%.
4. The chip of claim 1, wherein the chip comprises a plurality of chips,
The pin wells (104) are perpendicular to the surface metal (105).
5. A method of designing a chip, the method comprising:
Providing a base layer (101);
Providing a metal layer (102) on the base layer (101), the metal layer (102) comprising at least a surface layer metal (105) and a bottom layer metal (106); and
Providing a plurality of connection points (103) on the surface layer metal (105);
The bottom metal (106) is provided with pin wells (104) which are communicated with part of the connection points (103) in a one-to-one correspondence manner and are used for providing signal transmission channels, and the pin wells (104) comprise a plurality of sequentially longitudinally communicated pins (107);
The pin well (104) is provided with a driving gate circuit or a receiving gate circuit;
the pin well (104) is internally provided with a connecting wire and metal, and is used for connecting the surface metal (105) with a driving gate circuit or a receiving gate circuit;
The chip comprises a plurality of pin wells (104), the total length of pins (107) in the pin wells (104) is close, so that chip signal transmission is synchronous;
the pins (107) are of a multi-layer stacked hole design;
the pins (107) are connected in staggered vertical communication, and the central axes of adjacent pins (107) are not overlapped.
6. The method of designing according to claim 5, wherein,
-The pins (107) are of perforated construction;
The pin well (104) is communicated with the surface layer metal (105) and the bottom layer metal (106);
the pins (107) are of a multi-layer stacked hole design;
The pins (107) are connected in staggered vertical communication.
7. The method of designing according to claim 5, wherein,
The difference in length between any two pins (107) in the pin well (104) is less than 10%.
8. The method of designing according to claim 5, wherein,
The pin wells (104) are perpendicular to the surface metal (105).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310369319.0A CN116093022B (en) | 2023-04-10 | 2023-04-10 | Chip and chip design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310369319.0A CN116093022B (en) | 2023-04-10 | 2023-04-10 | Chip and chip design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116093022A CN116093022A (en) | 2023-05-09 |
| CN116093022B true CN116093022B (en) | 2024-05-10 |
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| CN202310369319.0A Active CN116093022B (en) | 2023-04-10 | 2023-04-10 | Chip and chip design method |
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| JP2004120659A (en) * | 2002-09-30 | 2004-04-15 | Kyocera Corp | Lamination structure for high-frequency signal transmission, and high-frequency semiconductor package using the structure |
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| CN111129053A (en) * | 2019-12-23 | 2020-05-08 | 上海集成电路研发中心有限公司 | CMOS image sensor pixel unit structure and forming method |
| CN112885811A (en) * | 2019-11-29 | 2021-06-01 | 联发科技股份有限公司 | Vertical interconnection structure of multilayer substrate |
| CN115579324A (en) * | 2022-10-25 | 2023-01-06 | 武汉新芯集成电路制造有限公司 | Interposer structure and method of fabricating the same |
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2023
- 2023-04-10 CN CN202310369319.0A patent/CN116093022B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004120659A (en) * | 2002-09-30 | 2004-04-15 | Kyocera Corp | Lamination structure for high-frequency signal transmission, and high-frequency semiconductor package using the structure |
| CN101789391A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
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| CN102110638A (en) * | 2009-12-23 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for overcoming discharge shortcoming of semiconductor device during manufacturing process |
| CN106298715A (en) * | 2015-06-25 | 2017-01-04 | 台湾积体电路制造股份有限公司 | Mixing bond pad structure |
| CN112885811A (en) * | 2019-11-29 | 2021-06-01 | 联发科技股份有限公司 | Vertical interconnection structure of multilayer substrate |
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| CN115579324A (en) * | 2022-10-25 | 2023-01-06 | 武汉新芯集成电路制造有限公司 | Interposer structure and method of fabricating the same |
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| CN116093022A (en) | 2023-05-09 |
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