CN111129052A

CN111129052A - CMOS image sensor structure and manufacturing method

Info

Publication number: CN111129052A
Application number: CN201911334296.XA
Authority: CN
Inventors: 顾学强; 张美丽; 奚鹏程
Original assignee: Shanghai IC R&D Center Co Ltd; Chengdu Light Collector Technology Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Chengdu Light Collector Technology Co Ltd
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2020-05-08
Anticipated expiration: 2039-12-23
Also published as: CN111129052B

Abstract

The invention discloses a CMOS image sensor structure, which is arranged on a first silicon substrate and a second silicon substrate which are stacked up and down, wherein the first silicon substrate comprises a first buried oxide layer and a first silicon layer arranged below the first buried oxide layer, the second silicon substrate comprises a second buried oxide layer and a second silicon layer arranged below the second buried oxide layer, the thickness of the first silicon layer is larger than that of the second silicon layer, the first silicon layer is bonded with the second buried oxide layer, a through opening is formed on the second silicon substrate corresponding to a pixel unit array region, a plurality of light sensing parts and control transistors of a pixel unit array are arranged on the back surface of the first silicon layer corresponding to the opening, and peripheral circuit transistors are arranged on the back surface of the second silicon layer around the opening. The invention can realize the manufacture of the pixel unit of the back-illuminated image sensor while using the low-power SOI device in the peripheral circuit, and can avoid the problems of impurity self-doping and poor thickness uniformity after thinning caused by the conventional back-illuminated process.

Description

CMOS image sensor structure and manufacturing method

Technical Field

The invention relates to the technical field of semiconductor processing, in particular to a CMOS image sensor structure and a manufacturing method thereof.

Background

For half a century, the semiconductor industry has been in keeping with moore's law with shrinking transistor sizes, increasing transistor density, and increasing performance. However, as the size of bulk silicon transistor devices in planar structures is getting closer to the physical limit, moore's law is getting closer to its termination; therefore, new structures of semiconductor devices called "non-classical CMOS" have been proposed. These techniques include finfets, carbon nanotubes, Silicon On Insulator (SOI), silicon germanium on insulator (SiGe on insulator), germanium on insulator (GeOI), and the like.

With these new structures, the performance of the semiconductor device can be further improved. Among them, a semiconductor device manufactured on a silicon-on-insulator Substrate (SOI) material has attracted much attention because of its simple process and superior performance.

Semiconductor-on-insulator is a technique in which devices are fabricated in a silicon layer over an insulating layer rather than on a conventional silicon substrate, thereby achieving all-dielectric isolation between different transistors. Compared with the traditional planar bulk silicon process, the SOI technology has the advantages of high speed, low power consumption and high integration level. Compared with a bulk silicon device, the unique insulating buried oxide layer separates the device from the substrate, realizes the full-medium isolation of a single transistor, eliminates the influence (namely the bulk effect) of the substrate on the device, fundamentally eliminates the Latch-Up (Latch-Up) of the bulk silicon CMOS device, inhibits the parasitic effect of the bulk silicon device to a great extent, fully exerts the potential of the silicon integration technology, greatly improves the performance of a circuit, and has the working performance close to an ideal device.

Semiconductor on insulator has shown to be the dominant technology for future SOCs, whether in the size reduction of devices or in radio frequency or low voltage, low power applications. By using the semiconductor-on-insulator technology, a logic circuit, an analog circuit and an RF circuit can be integrated on one chip under the condition of small mutual interference, and the semiconductor-on-insulator technology has a very wide development prospect, so that the semiconductor-on-insulator technology becomes an important technology for researching and developing a large-scale integrated circuit with high speed, low power consumption, high integration degree and high reliability.

Meanwhile, the CMOS image sensor is an important application direction of the CMOS process. The image sensor refers to a device that converts an optical signal into an electrical signal, and a large-scale commercial image sensor chip includes two major types of Charge Coupled Device (CCD) and Complementary Metal Oxide Semiconductor (CMOS) image sensor chips. Compared with the traditional CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, compatibility with the CMOS process and the like, so that the CMOS image sensor is more and more widely applied. At present, CMOS image sensors are widely used in consumer electronics fields such as digital micro cameras (DSCs), cell phone cameras, video cameras, Digital Single Lens Reflex (DSLR), and in automotive electronics, surveillance, biotechnology, and medicine.

In order to achieve efficient photoelectric conversion, the silicon layer for sensitization of the CMOS image sensor is typically several micrometers to several tens of micrometers thick. SOI is used to fabricate devices with silicon layers typically between a few nanometers and hundreds of nanometers thick, well below the thickness required for CMOS image sensor sensing.

Referring to fig. 1, fig. 1 is a schematic diagram of a CMOS transistor fabricated in a conventional silicon-on-insulator substrate. As shown in fig. 1, a silicon-on-insulator (SOI) substrate includes a silicon base 10 at a bottom layer, a device silicon substrate 12 at an upper layer, and a buried oxide layer 11 for isolation between the silicon base 10 and the device silicon substrate 12. A transistor 13 is formed in the device silicon substrate 12 above the buried oxide layer 11. The buried oxide layer 11 between the silicon substrate 12 and the silicon substrate 10 for the device is usually a silicon dioxide layer, the thickness of the silicon substrate 12 for the device is usually between several nanometers and several hundred nanometers, which is much lower than the thickness required for the light sensing of the CMOS image sensor, and the doping concentration and type requirements of the substrate used for the SOI device are different from those of the CMOS image sensor. Since the thickness of the silicon substrate 12 for the device is too thin, a pixel cell structure of a CMOS image sensor cannot be fabricated therein. Therefore, SOI silicon wafers are not suitable for fabricating CMOS image sensors.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a conventional back-illuminated CMOS image sensor before thinning. As shown in fig. 2, a highly doped substrate 15 is bonded to the back side of the device silicon layer 14, and the thinning process requires that the highly doped substrate 15 be removed by grinding, wet etching, chemical mechanical polishing, and the like, and finally stop on the device silicon layer 14. Because the doping concentrations of the highly doped substrate 15 and the device silicon layer 14 are different, the corresponding etching rates are also different, so that the etching process is stopped mainly by the difference of the etching rates between the highly doped substrate and the device silicon layer, but the etching rate difference caused by the difference of the doping concentrations is smaller, so that the end point of the etching stop is not easy to control, and the over-etching phenomenon is often caused; meanwhile, the highly doped substrate 15 has a high impurity concentration and is easily separated out in a high-temperature process, so that the characteristics of the device are affected.

Therefore, there is a need to develop a new technology of a CMOS image sensor that can meet different manufacturing requirements of a pixel unit and a peripheral circuit; meanwhile, it is desirable to provide a CMOS image sensor manufacturing technique that does not require the use of a highly doped substrate to achieve backside illuminated process thinning.

Disclosure of Invention

The present invention aims to overcome the above-mentioned defects of the prior art, and provides a CMOS image sensor structure and a method for manufacturing the same, which realizes the manufacture of a pixel unit of a back-illuminated image sensor while using a low-power SOI device as a peripheral circuit of the image sensor, so as to achieve the purpose that the SOI device and the CMOS image sensor are manufactured by using different substrates; meanwhile, the problems of self doping and narrow process window formed when a highly doped substrate is used for manufacturing the back-illuminated CMOS image sensor are solved.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a CMOS image sensor structure is arranged on a first silicon substrate and a second silicon substrate which are stacked up and down, wherein the first silicon substrate and the second silicon substrate are provided with a pixel unit array area and a peripheral circuit area located around the pixel unit array area;

the first silicon substrate includes: the first buried oxide layer is arranged on the front surface of the first silicon substrate, and the first silicon layer is arranged below the first buried oxide layer;

the second silicon substrate includes: the second buried oxide layer is arranged on the front surface of the second silicon substrate, and the second silicon layer is arranged below the second buried oxide layer; wherein the thickness of the first silicon layer is greater than the thickness of the second silicon layer;

the first silicon substrate and the second silicon substrate are connected through bonding of the first silicon layer and the second buried oxide layer;

a through opening is formed on the second silicon substrate corresponding to the pixel unit array area, a plurality of light sensing parts and control transistors of the pixel unit array are arranged on the back surface of the first silicon layer corresponding to the opening, and peripheral circuit transistors are arranged in the peripheral circuit area on the back surface of the second silicon layer around the opening.

Furthermore, a first shallow trench isolation for isolating the pixel unit is arranged on the back surface of the first silicon layer corresponding to the opening.

Further, a second shallow trench isolation for isolating the pixel unit array region from the peripheral circuit region is arranged on the back surface of the second silicon layer around the opening, and the second shallow trench isolation extends into the back surface of the first silicon layer.

Further, the first silicon substrate is bonded with the first carrier through the first buried oxide layer.

Furthermore, the first slide glass is made of silicon.

Furthermore, a back-end dielectric layer is arranged on the back surface of the second silicon layer and is connected with the back surface of the first silicon layer through the opening.

Furthermore, a metal interconnection layer is arranged in the back-end dielectric layer.

Further, the second silicon substrate is bonded with a second slide glass through the back dielectric layer.

Further, the light sensing portion is a photodiode.

A CMOS image sensor structure fabrication method, comprising:

providing a first silicon substrate, and forming a first buried oxide layer on the front surface of the first silicon substrate;

forming a first hydrogen ion layer in the first silicon substrate below the first buried oxide layer by hydrogen ion implantation, thereby forming a first silicon layer in the first silicon substrate between the first buried oxide layer and the first hydrogen ion layer;

inverting the first silicon substrate to bond the first buried oxide layer with a first carrier;

cleaving the first silicon substrate along the first hydrogen ion layer by annealing to form the first silicon substrate structure having the first buried oxide layer and the first silicon layer;

providing a second silicon substrate, and forming a second buried oxide layer on the front surface of the second silicon substrate;

forming a second hydrogen ion layer in the second silicon substrate below the second buried oxide layer by hydrogen ion implantation, thereby forming a second silicon layer in the second silicon substrate between the second buried oxide layer and the second hydrogen ion layer; wherein the thickness of the first silicon layer is greater than the thickness of the second silicon layer;

inverting the second silicon substrate to bond the second buried oxide layer with the first silicon layer;

through annealing, splitting the second silicon substrate along the second hydrogen ion layer to form a second silicon substrate structure which is connected with the first silicon substrate and is provided with the second buried oxide layer and the second silicon layer;

removing the second silicon layer and the second buried oxide layer material of the pixel unit array region, simultaneously reserving the second silicon layer and the second buried oxide layer material of the peripheral circuit region, and forming an opening on the second silicon substrate to expose the first silicon layer below;

forming a plurality of photodiodes and a first shallow trench isolation of a pixel unit array on the back surface of the first silicon layer below the opening, and forming a second shallow trench isolation on the back surface of the second silicon layer around the opening, and enabling the bottom of the second shallow trench isolation to enter the back surface of the first silicon layer;

forming a peripheral circuit transistor on the back surface of the second silicon layer around the opening, and forming a plurality of control transistors of a pixel cell array on the back surface of the first silicon layer corresponding to the position of the opening;

forming a back dielectric layer on the back of the second silicon substrate in a whole wafer manner, covering the opening, and forming a metal interconnection layer in the back dielectric layer;

inverting the second silicon substrate to bond the subsequent dielectric layer with a second slide glass;

thinning the first slide glass to stop thinning on the first buried oxide layer;

and continuously thinning the first buried oxide layer to stop thinning on the first silicon layer and expose the photodiode.

According to the technical scheme, the mutual stacking of the silicon layers with different thicknesses, namely the thick silicon layer (the first silicon layer) and the thin silicon layer (the second silicon layer), and the different oxygen burying layers (the first oxygen burying layer and the second oxygen burying layer) is realized through the two hydrogen ion implantation, silicon wafer bonding and silicon wafer stripping (splitting) technologies. The present invention can form a pixel unit transistor, a photodiode and other photosensitive devices in a thick silicon layer having a thickness of several to several tens of micrometers, and simultaneously form an SOI transistor in a thin silicon layer having a thickness of several to several hundreds of nanometers, by using two different types of silicon substrates. And according to different requirements of the SOI device and the pixel unit device on the doping type and the doping concentration of the silicon substrate, different doping types and doping concentrations can be used for the thick silicon layer and the thin silicon layer, for example, the thin silicon layer can be doped by using a P type, the thick silicon layer can be doped by using an N type, or the thin silicon layer and the thick silicon layer can be doped by using a P type, but the doping concentrations of the thin silicon layer and the thick silicon layer are different, so that the respective optimization of the SOI device on the thin silicon layer and the pixel unit device on the thick silicon layer can be realized. Therefore, the present invention achieves the object of forming a high-performance pixel cell array while using a high-speed, low-power consumption, and high-integration SOI device in a peripheral circuit of a CMOS image sensor.

Drawings

Fig. 1 is a schematic diagram of a CMOS transistor structure fabricated in a conventional silicon-on-insulator substrate.

Fig. 2 is a schematic structural diagram of a conventional back-illuminated CMOS image sensor before thinning.

Fig. 3 is a layout diagram of a CMOS image sensor chip.

Fig. 4 is a cross-sectional view of a CMOS image sensor at a location a-B in fig. 3 according to a preferred embodiment of the present invention.

Fig. 5-23 are schematic process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the invention.

Detailed Description

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.

In the following embodiments of the present invention, please refer to fig. 3-4, fig. 3 is a layout diagram of a CMOS image sensor chip, and fig. 4 is a cross-sectional structure diagram of a CMOS image sensor along a-B position in fig. 3 according to a preferred embodiment of the present invention. As shown in fig. 3, a typical CMOS image sensor chip includes a pixel cell area at the center of the chip and a peripheral circuit area surrounding the pixel cell area. The pixel unit area is provided with a pixel unit array formed by a plurality of densely arranged pixel units, and the pixel unit array is responsible for converting optical signals into electric signals; the peripheral circuit area is provided with various peripheral control and readout circuits including peripheral circuits such as a column-level readout circuit and a row selection control circuit.

Please refer to fig. 4, which shows a cross-sectional structure along the direction "a-B" in fig. 3. The device structure in fig. 4 is inverted compared to fig. 1. As shown in FIG. 4, a CMOS image sensor structure of the present invention is built on a first silicon substrate I and a second silicon substrate II stacked one on top of the other. The first silicon substrate i and the second silicon substrate ii are, for example, silicon wafers. A pixel cell array region and a peripheral circuit region located around the pixel cell array region are defined in a vertical direction on a first silicon substrate I and a second silicon substrate II.

Please refer to fig. 4. The first silicon substrate i located above includes: a first buried oxide layer 27 provided on the front side of the first silicon substrate i and a first silicon layer 26 connected below the first buried oxide layer 27. The first silicon layer 26 is used for manufacturing pixel unit devices, including devices for sensing light such as the control transistor 29 and the photodiode 28 of the pixel unit located in the pixel unit array region, and thus has the thickness of a conventional silicon substrate, i.e., the first silicon layer 26 is a thick silicon layer 26, and the thickness thereof is generally several micrometers to several tens of micrometers.

The second silicon substrate II located below the first silicon substrate I comprises: a second buried oxide layer 24 provided on the front surface of the second silicon substrate ii and a second silicon layer 23 connected below the second buried oxide layer 24. The second silicon layer 23 is a thin silicon layer 23, and the thickness of the second silicon layer is typically several nanometers to several hundred nanometers, so that the second silicon substrate ii is equivalent to an SOI substrate, and can be used to manufacture SOI devices including the peripheral circuit transistor 22 in the peripheral circuit region.

The first silicon substrate I and the second silicon substrate II are connected through bonding of the first silicon layer 26 and the second buried oxide layer 24.

Please refer to fig. 4. A through opening 33 is formed on the second silicon substrate ii corresponding to the pixel unit array region (see fig. 15); that is, the size of the opening 33 corresponds to the pixel cell array region, and the region other than the opening 33 is the peripheral circuit region.

On the back surface of the first silicon layer 26 at the position corresponding to the opening 33, a plurality of photodiodes 28 and control transistors 29 of the pixel cell array, and a first shallow trench isolation 30 for isolating the pixel cells are provided.

On the back surface of the second silicon layer 23 around the opening 33, a peripheral circuit transistor 22 and a second shallow trench isolation 25 for isolating the pixel cell array region from the peripheral circuit region are provided. Wherein the bottom of the second shallow trench isolation 25 extends into the backside of the first silicon layer 26.

Please refer to fig. 4. The first silicon substrate i may be bonded to the first carrier wafer by a first buried oxide layer 27. The first buried oxide layer 27 can be used as a stop layer when the back side of the first silicon substrate i is thinned. The material of the first carrier sheet can be silicon, for example.

A back medium layer 20 is arranged on the back of the second silicon layer 23; the subsequent dielectric layer 20 is connected to the back side of the first silicon layer 26 through an opening 33. A metal interconnection layer 21 is provided in the subsequent dielectric layer 20.

The second silicon substrate II can be bonded with a second slide glass through a subsequent dielectric layer 20.

A method for fabricating a CMOS image sensor structure according to the present invention is described in detail with reference to the accompanying drawings.

Referring to fig. 5-23, fig. 5-23 are schematic process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the invention. As shown in fig. 5-23, a method for fabricating a CMOS image sensor chip structure according to the present invention can be used to fabricate the above-mentioned CMOS image sensor chip structure such as that shown in fig. 4. The invention relates to a manufacturing method of an image sensor structure, which comprises the following steps:

first, as shown in fig. 5, a conventional silicon wafer substrate is used as the first silicon substrate i. The thickness of the first silicon substrate i is typically about 700 μm, and the doping type can be N-type or P-type, and the doping concentration can be adjusted according to the optimization requirement of the CMOS image sensor pixel unit.

Next, as shown in fig. 6, a layer of silicon dioxide may be grown on the entire front surface of the first silicon substrate i by thermal oxidation, thereby forming a first buried oxide layer 27 on the front surface of the first silicon substrate i.

Subsequently, as shown in fig. 7, a hydrogen ion implanted layer is formed as a first hydrogen ion layer 31 in the first silicon substrate i below the first buried oxide layer 27 by hydrogen ion implantation. The implantation depth of the first hydrogen ion layer 31 can be several microns to several tens of microns, and the first silicon substrate I material positioned between the first buried oxide layer 27 and the first hydrogen ion layer 31 is used as the first silicon layer 26; the first silicon layer 26, i.e., the thick silicon layer 26, is subsequently used to fabricate CMOS image sensor pixel cells.

Next, as shown in fig. 8, the first silicon substrate i is inverted, and the first buried oxide layer 27 is bonded to the first carrier.

And then, through high-temperature annealing, splitting the first silicon substrate I along the first hydrogen ion layer 31, and removing the first silicon substrate I material above the thick silicon layer 26 by utilizing the bubbles formed in the first silicon substrate I by the hydrogen ion injection layer 31 to expand under heat. Then, by further interfacial processing, a three-layer new structure of the first silicon substrate i having the first buried oxide layer 27 and the first silicon layer 26 and the first carrier sheet is formed, as shown in fig. 9.

Meanwhile, as shown in fig. 10, another conventional silicon wafer substrate is used as the second silicon substrate ii. The thickness of the second silicon substrate II is usually about 700 microns, the doping type can be N type or P type, and the doping concentration can be adjusted according to the optimization requirement of the performance of the SOI device.

Next, as shown in fig. 11, a layer of silicon dioxide may be grown on the entire front surface of the second silicon substrate ii by thermal oxidation, thereby forming a second buried oxide layer 24 on the front surface of the second silicon substrate ii.

Subsequently, as shown in fig. 12, a hydrogen ion implanted layer is formed as a second hydrogen ion layer 32 in the second silicon substrate ii under the second buried oxide layer 24 by hydrogen ion implantation. The implantation depth of the second hydrogen ion layer 32 can be from several nanometers to several hundred nanometers, and a second silicon substrate II material positioned between the second buried oxide layer 24 and the second hydrogen ion layer 32 is used as a second silicon layer 23; the second silicon layer 23, i.e., the thin silicon layer 23, is subsequently used to fabricate SOI devices.

Next, as shown in fig. 13, the second silicon substrate ii is inverted, and the second buried oxide layer 24 and the first silicon layer 26 are bonded to form the illustrated stacked structure. Wherein the first silicon layer 26 and the second silicon layer 23 are isolated from each other by the second buried oxide layer 24.

And then, through high-temperature annealing, splitting the second silicon substrate II along the second hydrogen ion layer 32, and removing the second silicon substrate II material above the thin silicon layer 23 by utilizing the thermal expansion of bubbles formed in the second silicon substrate II by the hydrogen ion injection layer 32. Then, by further interface processing, a five-layer new structure having a thin silicon layer 23, a second buried oxide layer 24, a thick silicon layer 26, a first buried oxide layer 27, and a first carrier sheet in this order is formed, as shown in fig. 14.

Then, as shown in fig. 15, the second silicon layer 23 and the second buried oxide layer 24 in the pixel cell array region can be removed by photolithography and etching to expose the underlying first silicon layer 26; while the second silicon layer 23 and the second buried oxide layer 24 material of the peripheral circuit region are retained, an opening 33 is formed in the second silicon substrate ii.

Next, as shown in fig. 16, a plurality of photodiodes 28 of the pixel cell array and first shallow trench isolations 30 may be formed on the back surface of the first silicon layer 26 below the opening 33 using photolithography, etching, ion implantation, and the like, and the depth of the photodiodes 28 may be equal to the thickness of the thick silicon layer 26. And forming a second shallow trench isolation 25 on the back of the second silicon layer 23 around the opening 33 and letting the bottom of the second shallow trench isolation 25 enter into the back of the first silicon layer 26, i.e. so that the depth of the second shallow trench isolation 25 is larger than the sum of the thicknesses of the thin silicon layer 23 and the second buried oxide layer 24.

Next, as shown in fig. 17, by using a semiconductor manufacturing process, the peripheral circuit transistor 22 is formed on the back surface of the second silicon layer 23 around the opening 33, and the plurality of control transistors 29 of the pixel cell array are formed on the back surface of the first silicon layer 26 at positions corresponding to the openings 33.

Then, as shown in fig. 18, the opening 33 is filled by deposition of a dielectric layer material 34 and a planarization process, and a step existing between the peripheral circuit and the pixel cell area is filled.

Next, as shown in fig. 19, a back-end dielectric layer 20 is formed entirely on the back surface of the second silicon substrate ii by deposition, and a metal interconnection layer 21 is formed in the back-end dielectric layer 20 using processes such as metal lithography, etching, and chemical mechanical polishing.

Then, as shown in fig. 20, the second silicon substrate ii is inverted, and the subsequent dielectric layer 20 is bonded to the second carrier.

Next, as shown in fig. 21, the first carrier is thinned by grinding, wet etching, chemical mechanical polishing, and the like, and due to the difference in the removal rate between the silicon material of the first carrier and the silicon dioxide material of the first buried oxide layer 27, thinning can be automatically stopped on the first buried oxide layer 27. Therefore, the high selection ratio characteristic of the process between the silicon substrate and the oxygen burying layer can be utilized, and the first oxygen burying layer 27 is used as a stop layer for the bonding of the first slide glass, so that the stability and the uniformity of the thinning process are improved, and the window of the thinning process is effectively expanded.

Subsequently, as shown in fig. 22, the first buried oxide layer 27 is thinned and removed continuously by wet etching or chemical mechanical polishing, and due to the difference in the removal rate between the silicon dioxide material of the first buried oxide layer 27 and the material of the first silicon layer 26, the thinning process is automatically stopped on the first silicon layer 26 and the photosensitive region of the photodiode 28 is exposed.

Finally, as shown in fig. 23, an antireflection layer 35 and a metal light blocking layer 36 may also be formed over the pixel cell using a conventional backside illumination process.

The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.

Claims

1. A CMOS image sensor structure is characterized in that the CMOS image sensor structure is arranged on a first silicon substrate and a second silicon substrate which are stacked up and down, and the first silicon substrate and the second silicon substrate are provided with a pixel unit array area and a peripheral circuit area located around the pixel unit array area;

2. The CMOS image sensor structure of claim 1, wherein a first shallow trench isolation for isolating pixel cells is provided on the backside of the first silicon layer corresponding to the opening.

3. The CMOS image sensor structure of claim 1, wherein a second shallow trench isolation is provided on the back surface of the second silicon layer around the opening to isolate the pixel cell array region from peripheral circuit regions, the second shallow trench isolation extending into the back surface of the first silicon layer.

4. The CMOS image sensor structure of claim 1, wherein the first silicon substrate is bonded to a first carrier via the first buried oxide layer.

5. The CMOS image sensor structure of claim 4, wherein said first carrier is silicon.

6. The CMOS image sensor structure of claim 1, wherein a back dielectric layer is disposed on the back surface of the second silicon layer, and the back dielectric layer is connected to the back surface of the first silicon layer through the opening.

7. The CMOS image sensor structure of claim 6, wherein said back dielectric layer has a metal interconnect layer disposed therein.

8. The CMOS image sensor structure of claim 6, wherein the second silicon substrate is bonded to a second carrier through the back dielectric layer.

9. The CMOS image sensor structure of claim 1, wherein the light sensing portions are photodiodes.

10. A CMOS image sensor structure manufacturing method is characterized by comprising the following steps: