CN102509730A - Preparation method of image sensor - Google Patents
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- CN102509730A CN102509730A CN2011104552040A CN201110455204A CN102509730A CN 102509730 A CN102509730 A CN 102509730A CN 2011104552040 A CN2011104552040 A CN 2011104552040A CN 201110455204 A CN201110455204 A CN 201110455204A CN 102509730 A CN102509730 A CN 102509730A
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Abstract
The invention provides a preparation method of an image sensor. The preparation method comprises the following steps of: providing a first semiconductor substrate and a second semiconductor substrate; forming a second isolation burying layer on the first semiconductor substrate surface or the second semiconductor substrate surface; bonding a first semiconductor substrate and a second semiconductor substrate, and making the second insulation layer be positioned between the first top layer semiconductor layer and the second semiconductor substrate; thinning the second semiconductor substrate for forming a second top layer semiconductor layer with different thickness from the first top layer semiconductor layer; defining a first region and a second region on the second top layer semiconductor layer surface, and opening a window on the first region until the first top layer semiconductor layer surface is exposed; and respectively completing the sensor and pixel reading circuit preparation on the first region and the second region, and forming isolation between adjacent devices for completing the preparation of the image sensor. The image sensor prepared by the method has good anti-radiation performance and good semiconductor performance, and in addition, a light sensing region has higher light absorption efficiency.
Description
Technical field
The invention belongs to technical field of semiconductors, refer in particular to and relate to a kind of imageing sensor preparation method.
Background technology
SOI (Silicon-On-Insulator, silicon on the dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and the backing to bury oxide layer.Through on insulator, forming semiconductive thin film, the SOI material had traditional body silicon materials incomparable advantage: can realize the dielectric isolation of components and parts in the integrated circuit, thoroughly eliminate the parasitic latch-up in the body silicon CMOS circuit; The integrated circuit that adopts this material to process has also that parasitic capacitance is little, integration density is high, speed is fast, technology is simple, short-channel effect is little and be specially adapted to advantages such as low-voltage and low-power dissipation circuit.
Cmos image sensor is a kind ofly to convert optical imagery the semiconductor device of the signal of telecommunication into, generally is made up of optics sensor devices and cmos signal treatment circuit (comprising pixel readout circuit).Common cmos image sensor is an active pixel type imageing sensor (APS) at present; Wherein be divided into three pipe pixel readout circuit (3T again; Comprise reset transistor, amplifier transistor and row selecting transistor) and four pipe pixel readout circuits (4T comprises transfering transistor, reset transistor, amplifier transistor and row selecting transistor), two big classes.
Existing cmos image sensor based on SOI technology roughly has following two types:
The first kind is that light sensitive diode is made in the cmos image sensor on the substrate silicon, and is as shown in Figure 5.What the pixel readout circuit among Fig. 5 adopted is the 4T type; Its principle and 3T type are similar basically; Therefore introduce with 4T type shown in Figure 5 below; Comprise: top layer silicon 503, the N type doped well region 507 in the substrate silicon that the P type doped substrate silicon 501 of SOI, insulating barrier (being generally silicon dioxide) 502, P type mix, be arranged in the above substrate silicon of said N type doped well region surperficial P type doped region 508, transfering transistor 505, floating diffusion region 506, be positioned at the above and silicon dioxide layer 509 below the transfering transistor of substrate silicon and be positioned at the pixel readout circuit 504 (Fig. 5 does not draw particular circuit configurations only with a transistor diagram pixel readout circuit) on the top layer silicon; Wherein, the part of the part of whole, the surperficial P type doped region 508 of N type doped well region 507 and substrate silicon 501 has been formed effective photosensitive area 510.
Its operation principle is that elder generation all sucks power supply with the reset transistor in the pixel readout circuit 504 with the electronics in the floating diffusion region 506, and its current potential is uprised; After the exposure beginning, photon irradiation is to effective photosensitive area 510, and in it, generate electronics and the hole right; Behind the end exposure; Add high level on the transfering transistor 505; Light induced electron in effective photosensitive area 510 is transferred to floating diffusion region 506; Its current potential is reduced, through amplifier transistor in the pixel readout circuit 504 and row selecting transistor (particular circuit configurations of not drawing among Fig. 5 is only with a transistor diagram pixel readout circuit) the photovoltage signal is exported at last.
There is following shortcoming in the said first kind at least based on the cmos image sensor of SOI technology: because photosensitive region is arranged in substrate silicon and directly is in contact with it; When described imageing sensor is in the radiation environment; High energy particle will be squeezed in the substrate silicon 501; Produce a large amount of electron hole pairs; High energy electron is wherein crossed the PN junction potential barrier that substrate silicon 501 and N type doped well region 507 constituted easily and is got into N type doped well region 507, forms the interference to picture signal, has reduced the signal to noise ratio and the dynamic range of gained image.
Second type is that light sensitive diode is made in the cmos image sensor structure on the top layer silicon; As shown in Figure 6, comprise SOI substrate silicon 601, intermediate insulating layer 602, P type doped top layer silicon 603, be arranged in top layer silicon near the N type doped region 604 on surface be positioned at top silicon layer pixel readout circuit 606.Wherein the part that exhausts near N type doped region 604 that exhausts part and top layer silicon 603 near top layer silicon 603 of N type doped region 604 constitutes effective photosensitive area 605 jointly, and said effective photosensitive area all is positioned at the top silicon layer inside of SOI.More than high 3 one magnitude of doping content of the doping content of N type doped region 604 than top layer silicon 603, make most of depletion region be positioned at top layer silicon 603.
Cmos image sensor based on SOI technology shown in Figure 6 is collected photo-generated carrier through the effective photosensitive area 605 that is positioned at top layer silicon, and remaining operation principle is identical with imageing sensor among Fig. 1.
There is following shortcoming at least in said second kind of cmos image sensor based on SOI technology: because its photosensitive area is arranged in top layer silicon, and in order to use complete depletion type SOI device, the thickness of top layer silicon 603 is generally less than 200nm; Big limitations the degree of depth of effective photosensitive area 605; Make the efficiency of light absorption of this imageing sensor descend, especially for the redness of wavelength greater than 600nm, orange and sodium yellow; Absorption efficiency is extremely low, and image quality is very undesirable.
Summary of the invention
The shortcoming of prior art in view of the above; The object of the present invention is to provide a kind of imageing sensor preparation method; The radiation resistance difference that is used for solving the prior art imageing sensor has reduced the signal to noise ratio of gained image and the problem of dynamic range, and the effective problem of the limited reduction absorptivity of the photosensitive area degree of depth.
For realizing above-mentioned purpose and other relevant purposes, the present invention provides a kind of imageing sensor preparation method, and this method may further comprise the steps at least:
1) first Semiconductor substrate and second Semiconductor substrate are provided; Wherein, first Semiconductor substrate comprises: first support substrates, be positioned at lip-deep first insulating buried layer of said first support substrates and be positioned at lip-deep first top-layer semiconductor of said first insulating buried layer;
2) form second insulating buried layer at said first semiconductor substrate surface or said second semiconductor substrate surface;
3) said first Semiconductor substrate of bonding and second Semiconductor substrate, and make said second insulating buried layer between said first top-layer semiconductor and second Semiconductor substrate;
4) with the said second Semiconductor substrate attenuate, form second top-layer semiconductor different with the first top-layer semiconductor thickness, wherein, what thickness was thicker in said first top-layer semiconductor and second top-layer semiconductor is thick film layers, otherwise, be thin layer;
5) define I zone and II zone on the said second top-layer semiconductor surface, and windowing is surperficial until exposing said first top-layer semiconductor in said I zone;
6) in the preparation of said I zone and II zone completion optical sensor device and pixel readout circuit, wherein, said optical sensor device is prepared in the said thick film layers, and forms the isolation between adjacent devices, to accomplish the preparation of imageing sensor.
Alternatively, said first top-layer semiconductor is a thin layer, and thickness range is 0.1 μ m～0.3 μ m, and said second top-layer semiconductor is a thick film layers, and thickness range is 0.3 μ m～10 μ m.
Alternatively, said first top-layer semiconductor is a thick film layers, and thickness range is 0.3 μ m～10 μ m, and said second top-layer semiconductor is a thin layer, and thickness range is 0.1 μ m～0.3 μ m.
Alternatively, the material of said first top-layer semiconductor and second top-layer semiconductor is respectively the semi-conducting material that is used to prepare semiconductor device, comprises in silicon, strained silicon, germanium and the SiGe any one at least; Said first support substrates is an ordinary semiconductor substrates, comprises silicon substrate or Sapphire Substrate at least.
Alternatively, in the said step 6), said optical sensor device comprises a kind of in light sensitive diode and the photogate at least; Said pixel readout circuit is three pipe pixel readout circuits or four pipe pixel readout circuits; Wherein, Said three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and said four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor.
Alternatively, the reset transistor of said pixel readout circuit, amplifier transistor and row selecting transistor are prepared in the said thin layer; When said pixel readout circuit was four pipe pixel readout circuits, the transfering transistor of said pixel readout circuit was prepared in the thick film layers.
Alternatively, said second Semiconductor substrate is the Semiconductor substrate with insulating buried layer, comprises silicon-on-insulator or germanium on insulator at least; Thinning process in the said step 4) comprises in regular turn etching or corrodes the support substrates and the insulating buried layer of said second Semiconductor substrate.
Alternatively, the thinning process in the said step 4) also comprises etching or corrosion process planarization process afterwards.
Alternatively, said first top-layer semiconductor is a thin layer, and when said second top-layer semiconductor was thick film layers, said second Semiconductor substrate was an ordinary semiconductor substrates, comprises silicon substrate at least; Thinning process in the said step 4) comprises the etching of preorder or the planarization process of corrosion process and postorder.
Alternatively, said second Semiconductor substrate is an ordinary semiconductor substrates, comprises silicon substrate at least; Said step 1) also comprises, carries out the H ion at said second semiconductor substrate surface and injects, and the degree of depth that ion injects is the thickness of second top-layer semiconductor of said step 4); At this moment, the attenuate in the said step 4) adopts high annealing, makes H ion injected media layer place form continuous airport, and then at said H ion injected media layer place said second Semiconductor substrate is realized peeling off, to form said second top-layer semiconductor.
As stated, a kind of imageing sensor preparation method of the present invention has following beneficial effect:
1) optical sensor device is prepared in the top-layer semiconductor as thick film layers, makes it can realize darker PN junction depletion region, thereby has higher efficiency of light absorption.
2) pixel readout circuit is prepared in the top-layer semiconductor as thin layer, and its MOS transistor is exhausted entirely, and circuit has the premium properties of high speed, low-power consumption, anti-breech lock.
3) optical sensor device of imageing sensor and pixel readout circuit through first insulating buried layer and second insulating buried layer and first support substrates and second support substrates realization electric isolation, have improved the ability of its anti-high energy particle radiation respectively.
Description of drawings
Fig. 1 a to Fig. 1 f is shown as the sketch map of imageing sensor preparation method of the present invention in embodiment one.
Fig. 2 a to Fig. 2 f is shown as the sketch map of imageing sensor preparation method of the present invention in embodiment two.
Fig. 3 a to Fig. 3 e is shown as the sketch map of imageing sensor preparation method of the present invention in embodiment three.
Fig. 4 a to Fig. 4 f is shown as the sketch map of imageing sensor preparation method of the present invention in embodiment four.
Fig. 5 is shown as the sketch map of first kind cmos image sensor in the prior art.
Fig. 6 is shown as the sketch map of second type of cmos image sensor in the prior art.
The element numbers explanation
11 first support substrates
12 first insulating buried layers
13 first top-layer semiconductor
1 first Semiconductor substrate
The support substrates of 21 second Semiconductor substrate
The insulating buried layer of 22 second Semiconductor substrate
The top-layer semiconductor of 23 second Semiconductor substrate
2 second Semiconductor substrate
3 second insulating buried layers
4 second top-layer semiconductor
5 optical sensor devices
6,504,606 pixel readout circuits
7 isolate
8,505 transfering transistors
9,506 floating diffusion regions
A-A, B-B, A '-A ', B '-B ' face
The C-C ion injects depth location
501,601 substrate silicon
502,602 insulating barriers
503, the top layer silicon of 603 P types doping
N type doped well region in 507 substrate silicon
508 surperficial P type doped regions
509 silicon dioxide layers
510,605 effective photosensitive areas
The N type doped region of 604 top layer silicon
Embodiment
Below through specific instantiation execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention can also implement or use through other different embodiment, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
The present invention provides a kind of imageing sensor preparation method; At first; First Semiconductor substrate and second Semiconductor substrate are provided; Wherein, first Semiconductor substrate comprises: first support substrates, be positioned at lip-deep first insulating buried layer of said first support substrates and be positioned at lip-deep first top-layer semiconductor of said first insulating buried layer; Secondly; Form second insulating buried layer at said first semiconductor substrate surface or said second semiconductor substrate surface; Said first Semiconductor substrate of bonding and second Semiconductor substrate, and make said second insulating buried layer between said first top-layer semiconductor and second Semiconductor substrate; Once more, with the said second Semiconductor substrate attenuate, form second top-layer semiconductor different with the first top-layer semiconductor thickness, wherein, what thickness was thicker in said first top-layer semiconductor and second top-layer semiconductor is thick film layers, otherwise, be thin layer; Then, define I zone and II zone on the said second top-layer semiconductor surface, and windowing is surperficial until exposing said first top-layer semiconductor in said I zone; At last, in the preparation of said I zone and II zone completion optical sensor device and pixel readout circuit, wherein, said optical sensor device is prepared in the said thick film layers, and forms the isolation between adjacent devices, to accomplish the preparation of imageing sensor.
See also Fig. 1 a to Fig. 6.Need to prove; The diagram that is provided in the following specific embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality; Kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.
Embodiment one
Shown in Fig. 1 a to Fig. 1 f, the present invention provides a kind of imageing sensor preparation method, and this method may further comprise the steps at least:
Shown in Fig. 1 a; At first execution in step 1) first Semiconductor substrate 1 and second Semiconductor substrate 2 be provided; Wherein, first Semiconductor substrate 1 comprises: first support substrates 11, be positioned at said first support substrates, 11 lip-deep first insulating buried layers 12 and be positioned at said first insulating buried layer, 12 lip-deep first top-layer semiconductor 13.
Wherein, the material of said first top-layer semiconductor 13 is the semi-conducting material that is used to prepare semiconductor device, comprises in silicon, strained silicon, germanium and the SiGe any one at least; Said first insulating buried layer 12 is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride; Said first support substrates 11 is ordinary semiconductor substrates (comprising silicon substrate or Sapphire Substrate at least); Said second Semiconductor substrate 2 is for ordinary semiconductor substrates (comprising silicon substrate at least) or have the Semiconductor substrate (comprise silicon-on-insulator or germanium on insulator at least, its backing material comprises silicon or sapphire) of insulating buried layer.Particularly; In present embodiment one; Said first top-layer semiconductor 13 is a monocrystalline silicon layer, and said first insulating buried layer 12 is the silica single layer structure, and said first support substrates 11 is the silicon materials support substrates; Said second Semiconductor substrate 2 is a silicon substrate, and the surface of said second Semiconductor substrate 2 uses B '-B ' face to represent (shown in Fig. 1 a).
Need to prove; Said first top-layer semiconductor 13 is thin layer or thick film layers, and wherein, said thin layer thickness range is 0.1 μ m～0.3 μ m; Said thick film layers thickness range is 0.3 μ m～10 μ m; In present embodiment one, said first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, and (shown in Fig. 1 a) represented with the A-A face in the surface of first top-layer semiconductor 13 of said first Semiconductor substrate 1.Follow execution in step 2).
Shown in Fig. 1 b; In step 2) in; Form second insulating buried layers 3 (the B-B face among Fig. 1 b represent shown in the surface of second insulating buried layer 3) on said second Semiconductor substrate 2 surface; The method that forms 3 employings of second insulating buried layer comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at said second Semiconductor substrate, 2 surface depositions, the second insulating buried layer material, to form second insulating buried layer 3; Or said second Semiconductor substrate 2 of thermal oxidation, oxide layer that its surface is formed is as second insulating buried layer 3.In present embodiment one, adopt thermal oxidation process, the oxide layers that said second Semiconductor substrate 2 surfaces are formed are as second insulating buried layer 3.
Need to prove; In another embodiment; Aforesaid step 2), forms second insulating buried layer 3 (A ' among Fig. 1 f-A ' face represent shown in the surface of second insulating buried layer 3) on said first Semiconductor substrate 1 surface, form the method that second insulating buried layer 3 adopts this moment and comprise: adopt chemical gaseous phase depositing process or physical gas-phase deposite method; At said first Semiconductor substrate, 1 surface deposition, the second insulating buried layer material, to form second insulating buried layer 3; Or said first Semiconductor substrate 1 of thermal oxidation, oxide layer that its surface is formed is as second insulating buried layer 3.
What need specify is; Said second insulating buried layer 3 is single layer structure or laminated construction; Said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride; In present embodiment one, said second insulating buried layer 3 is the silica of single layer structure.Follow execution in step 3).
Shown in Fig. 1 c; In step 3); Conventional bonding techniques is adopted after going up and forming second insulating buried layer 3 in said second Semiconductor substrate 2 surfaces, and said second insulating buried layer 3 is aimed at bonding with first top-layer semiconductor 13 of said first Semiconductor substrate 1; Promptly in Fig. 1 c, present embodiment one adopts conventional bonding techniques (Si-SiO
2Bonding); First top-layer semiconductor, the 13 surperficial A-A faces (also shown in Fig. 1 a) of said first Semiconductor substrate 1 of expression are aimed at bonding with the B-B faces (also shown in Fig. 1 b) on said second insulating buried layer of expression 3 surfaces; At this moment, said second insulating buried layer 3 is between said first top-layer semiconductor 13 and second Semiconductor substrate 2.Need to prove; In another embodiment; Conventional bonding techniques is adopted after going up and forming second insulating buried layer 3 in said first Semiconductor substrate of aforesaid step 3) 1 surface, and said second insulating buried layer 3 is aimed at bonding with said second Semiconductor substrate 2 surfaces; Promptly adopt conventional bonding techniques; B '-B ' the face (shown in Fig. 1 a) on said second Semiconductor substrate of expression 2 surfaces is aimed at bonding with the A '-A ' face (shown in Fig. 1 f) on said second insulating buried layer of expression 3 surfaces, and at this moment, said second insulating buried layer 3 is between said first top-layer semiconductor 13 and second Semiconductor substrate 2.Follow execution in step 4).
Shown in Fig. 1 d, in step 4),, form second top-layer semiconductor 4 with said second Semiconductor substrate, 2 attenuates.Said second top-layer semiconductor 4 is thin layer or thick film layers; Wherein, said thin layer thickness range is 0.1 μ m～0.3 μ m, and said thick film layers thickness range is 0.3 μ m～10 μ m; Particularly; In present embodiment one, because selected said first top-layer semiconductor 13 is the thin layer of thickness between 0.1 μ m～0.3 μ m, at this moment; 4 of required second top-layer semiconductor are the thick film layers of thickness between 0.3 μ m～10 μ m, and wherein 2 μ m～3 μ m are the preferred thickness of second top-layer semiconductor 4.Need to prove that in another embodiment, when selected said first top-layer semiconductor 13 was the thick film layers of thickness between 0.3 μ m～10 μ m, then required second top-layer semiconductor 4 was the thin layer of thickness between 0.1 μ m～0.3 μ m.
In present embodiment one, shown in Fig. 1 d, said first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m; Said second Semiconductor substrate 2 is a silicon substrate; And required second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m; Thinning process in the then said step 4) comprises the etching of preorder or the planarization process of corrosion process and postorder; Be about to carry out planarization again after said second Semiconductor substrate 2 (silicon substrate) etching or the corrosion, particularly, adopt cmp method to realize said planarization; Forming second top-layer semiconductor 4, wherein said second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m.Follow execution in step 5).
Shown in Fig. 1 e; In step 5), define I zone and II zone on said second top-layer semiconductor 4 surfaces, and at the regional windowing of said I until exposing said first top-layer semiconductor 13 surfaces; Wherein, The technology that said I zone windowing is adopted is conventional photoetching, etching (comprising inductively coupled plasma etching or reactive ion etching at least) and corrosion, in present embodiment one, adopts conventional photoetching, reactive ion etching and corrosion; On said second top-layer semiconductor 4 surfaces to the said I zone windowing that has defined, until exposing said first top-layer semiconductor 13 surfaces.Follow execution in step 6).
Shown in Fig. 1 e; In step 6); In the preparation of said I zone and II zone completion optical sensor device 5 and pixel readout circuit 6, wherein, said optical sensor device 5 is prepared in the said thick film layers; And adopt shallow trench isolation or dielectric to isolate the isolation 7 that forms between adjacent devices, to accomplish the preparation of imageing sensor.
Need to prove that said optical sensor device 5 comprises at least and is prepared in a kind of in light sensitive diode (comprise at least PN junction light sensitive diode or PIN knot light sensitive diode) and the photogate in the said thick film layers; Said pixel readout circuit 6 is three pipe pixel readout circuits, four pipe pixel readout circuit or other pixel readout circuits of being made up of MOS transistor: said three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, are prepared in the said thin layer; Said four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor; Wherein, The transfering transistor of said four pipe pixel readout circuits is prepared in the thick film layers, and reset transistor, amplifier transistor and the row selecting transistor of said four pipe pixel readout circuits are prepared in the said thin layer.Particularly, in present embodiment one, shown in Fig. 1 e, said optical sensor device 5 is the PN junction light sensitive diode, and said pixel readout circuit 6 is three pipe pixel readout circuits (only with transistor diagram pixel readout circuits).
In present embodiment one; Said first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m; Said second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m; Said I zone windowing is until exposing said first top-layer semiconductor 13 surfaces; Said II zone is in said second top-layer semiconductor 4, and shown in Fig. 1 e, said optical sensor device 5 is the PN junction light sensitive diode; Be prepared in the II zone as said second top-layer semiconductor 4 of thick film layers, said pixel readout circuit 6 is that three pipe pixel readout circuits (only with a transistor diagram pixel readout circuit) are prepared in the I zone as said first top-layer semiconductor 13 of thin layer; Isolation 7 between adjacent devices adopts dielectric to isolate, to accomplish the preparation of imageing sensor.
The imageing sensor of the present invention's preparation has good radiation resistance; And the imageing sensor photosensitive region has higher efficiency of light absorption; The circuit of imageing sensor has the premium properties of high speed, low-power consumption, anti-breech lock simultaneously, and promptly imageing sensor has good semiconducting behavior.
Embodiment two
Shown in Fig. 2 a to Fig. 2 f, the present invention provides a kind of imageing sensor preparation method, and this method may further comprise the steps at least:
Shown in Fig. 2 a; At first execution in step 1) first Semiconductor substrate 1 and second Semiconductor substrate 2 be provided; Wherein, first Semiconductor substrate 1 comprises: first support substrates 11, be positioned at said first support substrates, 11 lip-deep first insulating buried layers 12 and be positioned at said first insulating buried layer, 12 lip-deep first top-layer semiconductor 13.
Wherein, the material of said first top-layer semiconductor 13 is the semi-conducting material that is used to prepare semiconductor device, comprises in silicon, strained silicon, germanium and the SiGe any one at least; Said first insulating buried layer 12 is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride; Said first support substrates 11 is ordinary semiconductor substrates (comprising silicon substrate or Sapphire Substrate at least); Said second Semiconductor substrate 2 is for ordinary semiconductor substrates (comprising silicon substrate at least) or have the Semiconductor substrate (comprise silicon-on-insulator or germanium on insulator at least, its backing material can be silicon or sapphire) of insulating buried layer.Particularly; In present embodiment two, said first top-layer semiconductor 13 is a monocrystalline silicon layer, and said first insulating buried layer 12 is the silicon nitride single layer structure; Said first support substrates 11 is the sapphire material support substrates; Said second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, and preferred silicon-on-insulator (SOI) comprising: the support substrates 21 of second Semiconductor substrate 2, the top-layer semiconductor 23 that is positioned at the insulating buried layer 22 of said support substrates 21 lip-deep second Semiconductor substrate 2 and is positioned at said insulating buried layer 22 lip-deep second Semiconductor substrate 2, wherein; Said support substrates 21 is a Sapphire Substrate; Said insulating buried layer 22 is a silica, and said top-layer semiconductor 23 is a silicon, and (shown in Fig. 2 a) represented with the B-B face in top-layer semiconductor 23 surfaces of said second Semiconductor substrate 2.
Need to prove; Said first top-layer semiconductor 13 is thin layer or thick film layers, and wherein, said thin layer thickness range is 0.1 μ m～0.3 μ m; Said thick film layers thickness range is 0.3 μ m～10 μ m; In present embodiment two, said first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, wherein; 0.15 μ m～0.2 μ m is said first top-layer semiconductor, 13 preferred thickness, the surface of first top-layer semiconductor 13 of said first Semiconductor substrate 1 uses A '-A ' face to represent (shown in Fig. 2 a).
What need further specify is; Said second Semiconductor substrate 2 is to have the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI), and the top-layer semiconductor 23 of said second Semiconductor substrate 2 is thin layer or thick film layers; Wherein, Said thin layer thickness range is 0.1 μ m～0.3 μ m, and said thick film layers thickness range is 0.3 μ m～10 μ m, in present embodiment two; Because said first top-layer semiconductor 13 is thickness thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m; The top-layer semiconductor 23 of then said second Semiconductor substrate 2 is the thick film layers of thickness between 0.3 μ m～10 μ m, and wherein, 3 μ m～5 μ m are the preferred thickness of the top-layer semiconductor 23 of said second Semiconductor substrate 2.In another embodiment, when selected said first top-layer semiconductor 13 was the thick film layers of thickness between 0.3 μ m～10 μ m, the top-layer semiconductor 23 of then said second Semiconductor substrate 2 was elected the thin layer of thickness between 0.1 μ m～0.3 μ m as.Follow execution in step 2).
Shown in Fig. 2 b; In step 2) in; Form second insulating buried layer 3 (the A-A face among Fig. 2 b represent shown in the surface of second insulating buried layer 3) on said first Semiconductor substrate 1 surface; The method that forms 3 employings of second insulating buried layer this moment comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at said first Semiconductor substrate, 1 surface deposition, the second insulating buried layer material, to form second insulating buried layer 3; Or said first Semiconductor substrate 1 of thermal oxidation, oxide layer that its surface is formed is as second insulating buried layer 3.In present embodiment two, adopt chemical gaseous phase depositing process, at said first Semiconductor substrate, 1 surface deposition, the second insulating buried layer material, to form second insulating buried layer 3.
Need to prove; In another embodiment; Aforesaid step 2), forms second insulating buried layers 3 (B ' among Fig. 2 f-B ' face represent shown in the surface of second insulating buried layer 3) on said second Semiconductor substrate 2 surface, form the method that second insulating buried layer 3 adopts and comprise: adopt chemical gaseous phase depositing process or physical gas-phase deposite method; At said second Semiconductor substrate, 2 surface depositions, the second insulating buried layer material, to form second insulating buried layer 3; Or said second Semiconductor substrate 2 of thermal oxidation, oxide layer that its surface is formed is as second insulating buried layer 3.
What need specify is; Said second insulating buried layer 3 is single layer structure or laminated construction; Said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride; In present embodiment two, said second insulating buried layer 3 is the silicon oxynitride of single layer structure.Follow execution in step 3).
Shown in Fig. 2 c; In step 3), conventional bonding techniques is adopted after going up and forming second insulating buried layer 3 in said first Semiconductor substrate 1 surface; Said second insulating buried layer 3 is aimed at bonding with said second Semiconductor substrate 2 surfaces; Promptly in Fig. 2 c, adopt conventional bonding techniques, the B-B face (also shown in Fig. 2 a) on said second Semiconductor substrate of expression 2 surfaces is aimed at bonding with the A-A face (also shown in Fig. 2 b) on said second insulating buried layer of expression 3 surfaces; At this moment, said second insulating buried layer 3 is between said first top-layer semiconductor 13 and second Semiconductor substrate 2.Need to prove; In another embodiment; Conventional bonding techniques is adopted after going up and forming second insulating buried layer 3 in said second Semiconductor substrate of aforesaid step 3) 2 surfaces, and said second insulating buried layer 3 is aimed at bonding with first top-layer semiconductor 13 of said first Semiconductor substrate 1; Promptly adopt conventional bonding techniques; First top-layer semiconductor, the 13 surperficial A '-A ' faces (shown in Fig. 2 a) of said first Semiconductor substrate 1 of expression are aimed at bonding with the B '-B ' faces (shown in Fig. 2 f) on said second insulating buried layer of expression 3 surfaces, and at this moment, said second insulating buried layer 3 is between said first top-layer semiconductor 13 and second Semiconductor substrate 2.Follow execution in step 4).
Shown in Fig. 2 d, in step 4),, form second top-layer semiconductor 4 with said second Semiconductor substrate, 2 attenuates.Said second top-layer semiconductor 4 is thin layer or thick film layers; Wherein, said thin layer thickness range is 0.1 μ m～0.3 μ m, and said thick film layers thickness range is 0.3 μ m～10 μ m; In present embodiment two; Because selected said first top-layer semiconductor 13 is thickness thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m, at this moment, 4 of required second top-layer semiconductor are the thick film layers of thickness between 0.3 μ m～10 μ m.Need to prove that in another embodiment, when selected said first top-layer semiconductor 13 was the thick film layers of thickness between 0.3 μ m～10 μ m, then required second top-layer semiconductor 4 was the thin layer of thickness between 0.1 μ m～0.3 μ m.
In present embodiment two, shown in Fig. 2 d, said first top-layer semiconductor 13 is thickness thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m; Said second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer; Preferred silicon-on-insulator (SOI; Its backing material is a sapphire); And the top-layer semiconductor of said second Semiconductor substrate 2 23 is thickness thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m, and required second top-layer semiconductor 4 is the thick film layers of thickness between 0.3 μ m～10 μ m.Thereby; Thinning process in the said step 4) comprises: first etching or corrode the support substrates 21 of said second Semiconductor substrate 2; Etching or corrode the insulating buried layer 22 of said second Semiconductor substrate 2 again; The top-layer semiconductor 23 that only keeps said second Semiconductor substrate 2 is to form second top-layer semiconductor 4, wherein; The top-layer semiconductor 23 of said second Semiconductor substrate 2 is aforementioned second top-layer semiconductor 4, is thickness silicon materials thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m.Further; In another embodiment, after the etching or the support substrates 21 of corroding said second Semiconductor substrate 2 and the insulating buried layer 22, the top-layer semiconductor 23 of said second Semiconductor substrate 2 is carried out planarization again; Particularly; Said planarization adopts cmp method to realize, forming said second top-layer semiconductor 4, wherein said second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m.Follow execution in step 5).
Shown in Fig. 2 e; In step 5), define I zone and II zone on said second top-layer semiconductor 4 surfaces, and at the regional windowing of said I until exposing said first top-layer semiconductor 13 surfaces; Wherein, The technology that said I zone windowing is adopted is conventional photoetching, etching (comprising inductively coupled plasma etching or reactive ion etching at least) and corrosion, in present embodiment two, adopts conventional photoetching, reactive ion etching and corrosion; On said second top-layer semiconductor 4 surfaces to the said I zone windowing that has defined, until exposing said first top-layer semiconductor 13 surfaces.Follow execution in step 6).
Shown in Fig. 2 e; In step 6); In the preparation of said I zone and II zone completion optical sensor device 5 and pixel readout circuit 6, wherein, said optical sensor device 5 is prepared in the said thick film layers; And adopt shallow trench isolation or dielectric to isolate the isolation 7 that forms between adjacent devices, to accomplish the preparation of imageing sensor.
Need to prove that said optical sensor device 5 comprises at least and is prepared in a kind of in light sensitive diode (comprise at least PN junction light sensitive diode or PIN knot light sensitive diode) and the photogate in the said thick film layers; Said pixel readout circuit 6 is three pipe pixel readout circuits, four pipe pixel readout circuit or other pixel readout circuits of being made up of MOS transistor: said three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, are prepared in the said thin layer; Said four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor; Wherein, The transfering transistor of said four pipe pixel readout circuits is prepared in the thick film layers, and reset transistor, amplifier transistor and the row selecting transistor of said four pipe pixel readout circuits are prepared in the said thin layer.Particularly; In present embodiment two; Shown in Fig. 2 e; Said optical sensor device 5 is the PN junction light sensitive diode, and said pixel readout circuit 6 is four pipe pixel readout circuits, wherein; Reset transistor, amplifier transistor and the row selecting transistor of said four pipe pixel readout circuits be only with transistor signal (seeing Fig. 2 e), and the prepared zone of reset transistor, amplifier transistor and the row selecting transistor of pixel readout circuits is managed respectively in two different zones in the transfering transistor 8 of said four pipe pixel readout circuits, floating diffusion region 9 prepared zones and said four.
In present embodiment two; Said first top-layer semiconductor 13 is thickness silicon materials thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m; Said second Semiconductor substrate 2 is silicon-on-insulator (SOI; Its backing material is a sapphire); Said second top-layer semiconductor 4 (being the top-layer semiconductor 23 of said second Semiconductor substrate 2) is thickness silicon materials thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m, and said I zone windowing is until exposing said first top-layer semiconductor 13 surfaces, and said II zone is in said second top-layer semiconductor 4; Shown in Fig. 2 e; Said optical sensor device 5 is the PN junction light sensitive diode, is prepared in the II zone as said second top-layer semiconductor 4 of thick film layers, and said pixel readout circuit 6 is four pipe pixel readout circuits; Wherein, Reset transistor, amplifier transistor and the row selecting transistor of said four pipe pixel readout circuits all is prepared in the I zone as said first top-layer semiconductor 13 of thin layer only with a transistor signal, and the transfering transistor 8 of said four pipe pixel readout circuits and floating diffusion region 9 all are prepared in the II zone as said second top-layer semiconductor 4 of thick film layers; Isolation 7 between adjacent devices adopts dielectric to isolate, to accomplish the preparation of imageing sensor.
The imageing sensor of the present invention's preparation has good radiation resistance; And the imageing sensor photosensitive region has higher efficiency of light absorption; The circuit of imageing sensor has the premium properties of high speed, low-power consumption, anti-breech lock simultaneously, and promptly imageing sensor has good semiconducting behavior.
Embodiment three
Embodiment three and embodiment one adopt essentially identical technical scheme; Main difference is: among the embodiment one; First top-layer semiconductor 13 of said first Semiconductor substrate 1 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, and said second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m; In embodiment three; First top-layer semiconductor 13 of said first Semiconductor substrate 1 is thickness strained silicon materials thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m; Said second Semiconductor substrate 2 is silicon-on-insulator (SOI), and the top-layer semiconductor 23 of said second top-layer semiconductor 4 and said second Semiconductor substrate 2 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.
Shown in Fig. 3 a to Fig. 3 e, the present invention provides a kind of imageing sensor preparation method, and this method may further comprise the steps at least:
Shown in Fig. 3 a, essentially identical step 1) among execution and the embodiment one, difference is:
In present embodiment three, said first top-layer semiconductor 13 is thickness strained silicon materials thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m; Said second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer; Preferred silicon-on-insulator (SOI) comprising: the support substrates 21 of second Semiconductor substrate 2, the top-layer semiconductor 23 that is positioned at the insulating buried layer 22 of said support substrates 21 lip-deep second Semiconductor substrate 2 and is positioned at said insulating buried layer 22 lip-deep second Semiconductor substrate 2; Wherein, Said support substrates 21 is a silicon substrate, and said insulating buried layer 22 is a silica, and said top-layer semiconductor 23 is a silicon; Particularly, the top-layer semiconductor 23 of said second Semiconductor substrate 2 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.
Follow execution in step 2); Shown in Fig. 3 b, promptly in present embodiment three, adopt physical gas-phase deposite method; At said second Semiconductor substrate, 2 surface depositions, the second insulating buried layer material; Forming second insulating buried layer 3, and said second insulating buried layer 3 is double-deck laminated construction, and wherein the material of each layer is respectively silicon nitride and silicon oxynitride.
Then carry out the identical step 3) of embodiment one, shown in Fig. 3 c, promptly in present embodiment three, adopt conventional bonding techniques, said second insulating buried layer 3 is aimed at bonding with first top-layer semiconductor 13 of said first Semiconductor substrate 1.Follow execution in step 4).
Shown in Fig. 3 d; Essentially identical step 4) among execution and the embodiment one; Difference is: in present embodiment three; Said first top-layer semiconductor 13 is thickness thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m, and said second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI); And the top-layer semiconductor 23 of said second Semiconductor substrate 2 is the thin layer of thickness between 0.1 μ m～0.3 μ m, and then required second top-layer semiconductor 4 is the thin layer of thickness between 0.1 μ m～0.3 μ m.
Need to prove; In the step 4), embodiment three and embodiment one adopts identical thinning process, promptly first etching or corrode the support substrates 21 of said second Semiconductor substrate 2; Etching or corrode the insulating buried layer 22 of said second Semiconductor substrate 2 again; The top-layer semiconductor 23 that only keeps said second Semiconductor substrate 2 is to form second top-layer semiconductor 4, wherein; The top-layer semiconductor 23 of said second Semiconductor substrate 2 is aforementioned second top-layer semiconductor 4, is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.Further; In another embodiment, after the etching or the support substrates 21 of corroding said second Semiconductor substrate 2 and the insulating buried layer 22, the top-layer semiconductor 23 of said second Semiconductor substrate 2 is carried out planarization again; Particularly; Adopt cmp method to realize said planarization, to form second top-layer semiconductor 4, wherein said second top-layer semiconductor 4 is the thin layer of thickness between 0.1 μ m～0.3 μ m.Follow execution in step 5).
Follow execution in step 5); Shown in Fig. 3 e, promptly in present embodiment three, adopt conventional photoetching, inductively coupled plasma etching and corrosion; On said second top-layer semiconductor 4 surfaces to the said I zone windowing that has defined, until exposing said first top-layer semiconductor 13 surfaces.Follow execution in step 6).
Shown in Fig. 3 e, essentially identical step 6) among execution and the embodiment one, difference is:
In present embodiment three; Said first top-layer semiconductor 13 is thickness strained silicon materials thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m; Said second Semiconductor substrate 2 is silicon-on-insulator (SOI); Said second top-layer semiconductor 4 (being the top-layer semiconductor 23 of said second Semiconductor substrate 2) is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m; Said I zone windowing is until exposing said first top-layer semiconductor 13 surfaces; Said II zone is in said second top-layer semiconductor 4, and shown in Fig. 3 e, said optical sensor device 5 is the PN junction light sensitive diode; Be prepared in the I zone as said first top-layer semiconductor 13 of thick film layers, said pixel readout circuit 6 is that three pipe pixel readout circuits (only with a transistor diagram pixel readout circuit) are prepared in the II zone as said second top-layer semiconductor 4 of thin layer.
Need to prove that in the step 6), embodiment three is with embodiment one something in common:
I) said optical sensor device 5 is identical with said pixel readout circuit 6; Shown in Fig. 3 e; Promptly in present embodiment three, said optical sensor device 5 is the PN junction light sensitive diode, and said pixel readout circuit 6 is three pipe pixel readout circuits (only with transistor diagram pixel readout circuit zones).
Ii) partition method is identical, and shown in Fig. 3 e, promptly in present embodiment three, the isolation 7 between adjacent devices adopts dielectric to isolate, to accomplish the preparation of imageing sensor.
The imageing sensor of the present invention's preparation has good radiation resistance; And the imageing sensor photosensitive region has higher efficiency of light absorption; The circuit of imageing sensor has the premium properties of high speed, low-power consumption, anti-breech lock simultaneously, and promptly imageing sensor has good semiconducting behavior.
Embodiment four
Shown in Fig. 4 a to Fig. 4 f, the present invention provides a kind of imageing sensor preparation method, and this method may further comprise the steps at least:
Shown in Fig. 4 a; At first execution in step 1) first Semiconductor substrate 1 and second Semiconductor substrate 2 be provided; Wherein, first Semiconductor substrate 1 comprises: first support substrates 11, be positioned at said first support substrates, 11 lip-deep first insulating buried layers 12 and be positioned at said first insulating buried layer, 12 lip-deep first top-layer semiconductor 13.
Wherein, the material of said first top-layer semiconductor 13 is the semi-conducting material that is used to prepare semiconductor device, comprises in silicon, strained silicon, germanium and the SiGe any one at least; Said first insulating buried layer 12 is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride; Said first support substrates 11 is ordinary semiconductor substrates (comprising silicon substrate or Sapphire Substrate at least); Said second Semiconductor substrate 2 is for ordinary semiconductor substrates (comprising silicon substrate at least) or have the Semiconductor substrate (comprise silicon-on-insulator or germanium on insulator at least, its backing material comprises silicon or sapphire) of insulating buried layer.Particularly; In present embodiment four; Said first top-layer semiconductor 13 is a germanium-silicon layer, and said first insulating buried layer 12 is the silicon oxynitride single layer structure, and said first support substrates 11 is the sapphire material support substrates; Said second Semiconductor substrate 2 is a silicon substrate, and (shown in Fig. 4 a) represented with the B-B face in the surface of said second Semiconductor substrate 2.
Need to prove; Said first top-layer semiconductor 13 is thin layer or thick film layers; Wherein, Said thin layer thickness range is 0.1 μ m～0.3 μ m, and said thick film layers thickness range is 0.3 μ m～10 μ m, in present embodiment four; Said first top-layer semiconductor 13 is thickness silicon germanium material thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m, and the surface of first top-layer semiconductor 13 of said first Semiconductor substrate 1 uses A '-A ' face to represent (shown in Fig. 4 a).Follow execution in step 2).
Shown in Fig. 4 b; In step 2) in; Form second insulating buried layer 3 (the A-A face among Fig. 4 b represent shown in the surface of second insulating buried layer 3) on said first Semiconductor substrate 1 surface; The method that forms 3 employings of second insulating buried layer this moment comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at said first Semiconductor substrate, 1 surface deposition, the second insulating buried layer material, to form second insulating buried layer 3; Or said first Semiconductor substrate 1 of thermal oxidation, oxide layer that its surface is formed is as second insulating buried layer 3.In present embodiment four, adopt chemical gaseous phase depositing process, at said first Semiconductor substrate, 1 surface deposition, the second insulating buried layer material, to form second insulating buried layer 3.
Need to prove; In another embodiment; Aforesaid step 2), forms second insulating buried layers 3 (B ' among Fig. 4 f-B ' face represent shown in the surface of second insulating buried layer 3) on said second Semiconductor substrate 2 surface, form the method that second insulating buried layer 3 adopts and comprise: adopt chemical gaseous phase depositing process or physical gas-phase deposite method; At said second Semiconductor substrate, 2 surface depositions, the second insulating buried layer material, to form second insulating buried layer 3; Or said second Semiconductor substrate 2 of thermal oxidation, oxide layer that its surface is formed is as second insulating buried layer 3.
What need specify is; Said second insulating buried layer 3 is single layer structure or laminated construction; Said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride; In present embodiment four, said second insulating buried layer 3 is the silicon nitride of single layer structure.Follow execution in step 3).
Shown in Fig. 4 c; In step 3); Conventional bonding techniques is adopted after going up and forming second insulating buried layer 3 in said first Semiconductor substrate 1 surface, and said second insulating buried layer 3 is aimed at bonding with said second Semiconductor substrate 2 surfaces; Promptly adopt conventional bonding techniques; The B-B face (also shown in Fig. 4 a) on said second Semiconductor substrate of expression 2 surfaces is aimed at bonding with the A-A face (also shown in Fig. 4 b) on said second insulating buried layer of expression 3 surfaces, and at this moment, said second insulating buried layer 3 is between said first top-layer semiconductor 13 and second Semiconductor substrate 2.Need to prove; In another embodiment; After said second Semiconductor substrate of aforesaid step 3) 2 surfaces are gone up and are formed second insulating buried layer 3; Adopt conventional bonding techniques, said second insulating buried layer 3 is aimed at bonding with first top-layer semiconductor 13 of said first Semiconductor substrate 1, promptly in Fig. 4 c; Adopt conventional bonding techniques; First top-layer semiconductor, the 13 surperficial A '-A ' faces (also shown in Fig. 4 a) of said first Semiconductor substrate 1 of expression are aimed at bonding with the B '-B ' faces (also shown in Fig. 4 f) on said second insulating buried layer of expression 3 surfaces, and at this moment, said second insulating buried layer 3 is between said first top-layer semiconductor 13 and second Semiconductor substrate 2.Follow execution in step 4).
Shown in Fig. 4 d, in step 4),, form second top-layer semiconductor 4 with said second Semiconductor substrate, 2 attenuates.Said second top-layer semiconductor 4 is thin layer or thick film layers; Wherein, said thin layer thickness range is 0.1 μ m～0.3 μ m, and said thick film layers thickness range is 0.3 μ m～10 μ m; In present embodiment four; Because selected said first top-layer semiconductor 13 is thickness thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m, at this moment, 4 of required second top-layer semiconductor are the thin layer of thickness between 0.1 μ m～0.3 μ m.Need to prove that in another embodiment, when selected said first top-layer semiconductor 13 was the thin layer of thickness between 0.1 μ m～0.3 μ m, then required second top-layer semiconductor 4 was the thick film layers of thickness between 0.3 μ m～10 μ m.
In present embodiment four, shown in Fig. 4 d, said first top-layer semiconductor 13 is thickness silicon germanium material thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m; Said second Semiconductor substrate 2 is a silicon substrate; And required second top-layer semiconductor 4 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m; What need further specify is that said step 1) also comprises, carries out the H ion on said second Semiconductor substrate 2 surfaces and injects; Depth distance second Semiconductor substrate, 2 surperficial 0.1 μ m～0.3 μ m (position shown in Fig. 4 a C-C face) that ion injects, this ion injects the thickness that the degree of depth is required second top-layer semiconductor 4; At this moment; Attenuate in the said step 4) adopts high annealing; Make H ion injected media layer position (position shown in C-C face among Fig. 4 c) form continuous airport; And then in said H ion injected media layer position (position shown in C-C face among Fig. 4 c) said second Semiconductor substrate 2 is realized peeling off, to form second top-layer semiconductor 4, wherein said second top-layer semiconductor 4 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.
What need specified otherwise is that in another embodiment, said first top-layer semiconductor 13 is the thin layer of thickness between 0.1 μ m～0.3 μ m; Required second top-layer semiconductor 4 is the thick film layers of thickness between 0.3 μ m～10 μ m; What need further specify is that said step 1) also comprises, carries out the H ion on said second Semiconductor substrate 2 surfaces and injects; Depth distance second Semiconductor substrate 2 surperficial 0.3 μ m～10 μ m that ion injects; This ion injects the thickness that the degree of depth is required second top-layer semiconductor 4, and at this moment, the attenuate in the said step 4) adopts high annealing; Make H ion injected media layer position form continuous airport; And then in said H ion injected media layer position said second Semiconductor substrate 2 is realized peeling off, to form second top-layer semiconductor 4, wherein said second top-layer semiconductor 4 is the thick film layers of thickness between 0.3 μ m～10 μ m.Follow execution in step 5).
Shown in Fig. 4 e; In step 5), define I zone and II zone on said second top-layer semiconductor 4 surfaces, and at the regional windowing of said I until exposing said first top-layer semiconductor 13 surfaces; Wherein, The technology that said I zone windowing is adopted is conventional photoetching, etching (comprising inductively coupled plasma etching or reactive ion etching at least) and corrosion, in present embodiment four, adopts conventional photoetching, reactive ion etching and corrosion; On said second top-layer semiconductor 4 surfaces to the said I zone windowing that has defined, until exposing said first top-layer semiconductor 13 surfaces.Follow execution in step 6).
Shown in Fig. 4 e; In step 6); In the preparation of said I zone and II zone completion optical sensor device 5 and pixel readout circuit 6, wherein, said optical sensor device 5 is prepared in the said thick film layers; And adopt shallow trench isolation or dielectric to isolate the isolation 7 that forms between adjacent devices, to accomplish the preparation of imageing sensor.
Need to prove that said optical sensor device 5 comprises at least and is prepared in a kind of in light sensitive diode (comprise at least PN junction light sensitive diode or PIN knot light sensitive diode) and the photogate in the said thick film layers; Said pixel readout circuit 6 is three pipe pixel readout circuits or four pipe pixel readout circuit or other pixel readout circuits of being made up of MOS transistor: said three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, are prepared in the said thin layer; Said four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor; Wherein, The transfering transistor of said four pipe pixel readout circuits is prepared in the thick film layers, and reset transistor, amplifier transistor and the row selecting transistor of said four pipe pixel readout circuits are prepared in the said thin layer.Particularly; In present embodiment four; Shown in Fig. 4 e; Said optical sensor device 5 is the PN junction light sensitive diode, and said pixel readout circuit 6 is four pipe pixel readout circuits, wherein; Reset transistor, amplifier transistor and the row selecting transistor of said four pipe pixel readout circuits be only with transistor signal (seeing Fig. 4 e), and the prepared zone of reset transistor, amplifier transistor and the row selecting transistor of pixel readout circuits is managed respectively in two different zones in the transfering transistor 8 of said four pipe pixel readout circuits, floating diffusion region 9 prepared zones and said four.
In present embodiment four; Said first top-layer semiconductor 13 is thickness silicon germanium material thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m; Said second top-layer semiconductor 4 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m; Said I zone windowing is until exposing said first top-layer semiconductor 13 surfaces; Said II zone is in said second top-layer semiconductor 4; Shown in Fig. 4 e, said optical sensor device 5 is the PN junction light sensitive diode, is prepared in the I zone as said first top-layer semiconductor 13 of thick film layers; Said pixel readout circuit 6 is four pipe pixel readout circuits; Reset transistor, amplifier transistor and the row selecting transistor of wherein said four pipe pixel readout circuits all is prepared in the II zone as said second top-layer semiconductor 4 of thin layer only with a transistor signal, and the transfering transistor 8 of said four pipe pixel readout circuits and floating diffusion region 9 all are prepared in the I zone as said first top-layer semiconductor 13 of thick film layers; Isolation 7 between adjacent devices adopts dielectric to isolate, to accomplish the preparation of imageing sensor.
In sum, imageing sensor preparation method of the present invention has following beneficial effect:
1) optical sensor device is prepared in the top-layer semiconductor as thick film layers, makes it can realize darker PN junction depletion region, thereby has higher efficiency of light absorption.
2) pixel readout circuit is prepared in the top-layer semiconductor as thin layer, and its MOS transistor is exhausted entirely, and circuit has the premium properties of high speed, low-power consumption, anti-breech lock.
3) optical sensor device of imageing sensor and pixel readout circuit through first insulating buried layer and second insulating buried layer and first support substrates and second support substrates realization electric isolation, have improved the ability of its anti-high energy particle radiation respectively.
So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.
Claims (10)
1. an imageing sensor preparation method is characterized in that, this method may further comprise the steps at least:
1) first Semiconductor substrate and second Semiconductor substrate are provided; Wherein, first Semiconductor substrate comprises: first support substrates, be positioned at lip-deep first insulating buried layer of said first support substrates and be positioned at lip-deep first top-layer semiconductor of said first insulating buried layer;
2) form second insulating buried layer at said first semiconductor substrate surface or said second semiconductor substrate surface;
3) said first Semiconductor substrate of bonding and second Semiconductor substrate, and make said second insulating buried layer between said first top-layer semiconductor and second Semiconductor substrate;
4) with the said second Semiconductor substrate attenuate, form second top-layer semiconductor different with the first top-layer semiconductor thickness, wherein, what thickness was thicker in said first top-layer semiconductor and second top-layer semiconductor is thick film layers, otherwise, be thin layer;
5) define I zone and II zone on the said second top-layer semiconductor surface, and windowing is surperficial until exposing said first top-layer semiconductor in said I zone;
6) in the preparation of said I zone and II zone completion optical sensor device and pixel readout circuit, wherein, said optical sensor device is prepared in the said thick film layers, and forms the isolation between adjacent devices, to accomplish the preparation of imageing sensor.
2. imageing sensor preparation method according to claim 1; It is characterized in that: said first top-layer semiconductor is a thin layer; Thickness range is 0.1 μ m～0.3 μ m, and said second top-layer semiconductor is a thick film layers, and thickness range is 0.3 μ m～10 μ m.
3. imageing sensor preparation method according to claim 1; It is characterized in that: said first top-layer semiconductor is a thick film layers; Thickness range is 0.3 μ m～10 μ m, and said second top-layer semiconductor is a thin layer, and thickness range is 0.1 μ m～0.3 μ m.
4. imageing sensor preparation method according to claim 1; It is characterized in that: the material of said first top-layer semiconductor and second top-layer semiconductor is respectively the semi-conducting material that is used to prepare semiconductor device, comprises in silicon, strained silicon, germanium and the SiGe any one at least; Said first support substrates is an ordinary semiconductor substrates, comprises silicon substrate or Sapphire Substrate at least.
5. imageing sensor preparation method according to claim 1 is characterized in that: in the said step 6), said optical sensor device comprises a kind of in light sensitive diode and the photogate at least; Said pixel readout circuit is three pipe pixel readout circuits or four pipe pixel readout circuits; Wherein, Said three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and said four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor.
6. imageing sensor preparation method according to claim 5 is characterized in that: the reset transistor of said pixel readout circuit, amplifier transistor and row selecting transistor are prepared in the said thin layer; When said pixel readout circuit was four pipe pixel readout circuits, the transfering transistor of said pixel readout circuit was prepared in the thick film layers.
7. imageing sensor preparation method according to claim 1 is characterized in that: said second Semiconductor substrate is the Semiconductor substrate with insulating buried layer, comprises silicon-on-insulator or germanium on insulator at least; Thinning process in the said step 4) comprises in regular turn etching or corrodes the support substrates and the insulating buried layer of said second Semiconductor substrate.
8. imageing sensor preparation method according to claim 7 is characterized in that: the thinning process in the said step 4) also comprises the planarization process after etching or the corrosion process.
9. imageing sensor preparation method according to claim 2 is characterized in that: said second Semiconductor substrate is an ordinary semiconductor substrates, comprises silicon substrate at least; Thinning process in the said step 4) comprises the etching of preorder or the planarization process of corrosion process and postorder.
10. imageing sensor preparation method according to claim 1 is characterized in that: said second Semiconductor substrate is an ordinary semiconductor substrates, comprises silicon substrate at least; Said step 1) also comprises, carries out the H ion at said second semiconductor substrate surface and injects, and the degree of depth that ion injects is the thickness of second top-layer semiconductor of said step 4); At this moment, the attenuate in the said step 4) adopts high annealing, makes H ion injected media layer place form continuous airport, and then at said H ion injected media layer place said second Semiconductor substrate is realized peeling off, to form said second top-layer semiconductor.
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