CN102509730B

CN102509730B - Preparation method of image sensor

Info

Publication number: CN102509730B
Application number: CN2011104552040A
Authority: CN
Inventors: 方娜; 陈杰; 汪辉; 田犁; 任韬
Original assignee: Shanghai Advanced Research Institute of CAS
Current assignee: Chongqing Toutuo Technology Co.,Ltd.
Priority date: 2011-12-30
Filing date: 2011-12-30
Publication date: 2013-11-20
Anticipated expiration: 2031-12-30
Also published as: CN102509730A

Abstract

The invention provides a preparation method of an image sensor. The preparation method comprises the following steps of: providing a first semiconductor substrate and a second semiconductor substrate; forming a second isolation burying layer on the first semiconductor substrate surface or the second semiconductor substrate surface; bonding a first semiconductor substrate and a second semiconductor substrate, and making the second insulation layer be positioned between the first top layer semiconductor layer and the second semiconductor substrate; thinning the second semiconductor substrate for forming a second top layer semiconductor layer with different thickness from the first top layer semiconductor layer; defining a first region and a second region on the second top layer semiconductor layer surface, and opening a window on the first region until the first top layer semiconductor layer surface is exposed; and respectively completing the sensor and pixel reading circuit preparation on the first region and the second region, and forming isolation between adjacent devices for completing the preparation of the image sensor. The image sensor prepared by the method has good anti-radiation performance and good semiconductor performance, and in addition, a light sensing region has higher light absorption efficiency.

Description

The imageing sensor preparation method

Technical field

The invention belongs to technical field of semiconductors, refer in particular to and relate to a kind of imageing sensor preparation method.

Background technology

SOI (Silicon-On-Insulator, silicon on dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and backing to bury oxide layer.By on insulator, forming semiconductive thin film, the SOI material had advantages of traditional body silicon materials incomparable: can realize the medium isolation of components and parts in integrated circuit, thoroughly eliminate the parasitic latch-up in the Bulk CMOS circuit; Adopt integrated circuit that this material is made also to have that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantages such as low voltage and low power circuits.

Cmos image sensor is a kind of semiconductor device that optical imagery is converted to the signal of telecommunication, generally optics sensor devices and cmos signal treatment circuit (comprising pixel readout circuit), consists of.Common cmos image sensor is active pixel type imageing sensor (APS) at present, wherein be divided into again three pipe pixel readout circuit (3T, comprise reset transistor, amplifier transistor and row selecting transistor) and four pipe pixel readout circuit (4T comprises transfering transistor, reset transistor, amplifier transistor and row selecting transistor) two large classes.

Existing cmos image sensor based on SOI technique roughly has following two classes:

The first kind is that light sensitive diode is made in to the cmos image sensor on substrate silicon, as shown in Figure 5.what the pixel readout circuit in Fig. 5 adopted is the 4T type, its principle and 3T type are substantially similar, therefore below, with 4T type shown in Figure 5, be described, comprise: the P type doped substrate silicon 501 of SOI, insulating barrier (being generally silicon dioxide) 502, the top layer silicon 503 of P type doping, N-type doped well region 507 in substrate silicon, be positioned at the surperficial P type doped region 508 of the above substrate silicon of described N-type doped well region, transfering transistor 505, floating diffusion region 506, be positioned at the silicon dioxide layer 509 that substrate silicon is above and transfering transistor is following, and be arranged in pixel readout circuit 504 on top layer silicon (Fig. 5 does not draw particular circuit configurations only with a transistor diagram pixel readout circuit), wherein, N-type doped well region 507 whole, the part of surface P type doped region 508 and the part of substrate silicon 501 have formed effective photosensitive area 510.

Its operation principle is, first with the reset transistor in pixel readout circuit 504, the electronics in floating diffusion region 506 all sucked to power supply, and its current potential is uprised; After exposure started, photon irradiation arrived effective photosensitive area 510, and generates in the inner electronics and hole pair; After end exposure, on transfering transistor 505, add high level, light induced electron in effective photosensitive area 510 is transferred to floating diffusion region 506, its current potential is reduced, finally by the amplifier transistor in pixel readout circuit 504 and row selecting transistor (not drawing particular circuit configurations in Fig. 5 only with a transistor diagram pixel readout circuit), the photovoltage signal is exported.

There is following shortcoming in the described first kind at least based on the cmos image sensor of SOI technique: because photosensitive region is arranged in substrate silicon and directly is in contact with it, when described imageing sensor is in radiation environment, high energy particle will be squeezed in substrate silicon 501, produce a large amount of electron hole pairs, high energy electron is wherein easily crossed the PN junction potential barrier that substrate silicon 501 and N-type doped well region 507 form and is entered N-type doped well region 507, the interference of formation to picture signal, reduced signal to noise ratio and the dynamic range of gained image.

Equations of The Second Kind is that light sensitive diode is made in to the cmos image sensor structure on top layer silicon, as shown in Figure 6, comprise SOI substrate silicon 601, intermediate insulating layer 602, P type doped top layer silicon 603, be arranged in top layer silicon near the surface N-type doped region 604 and be positioned at top silicon layer pixel readout circuit 606.Wherein the part that exhausts that exhausts part and the close N-type doped region 604 of top layer silicon 603 of the close top layer silicon 603 of N-type doped region 604, jointly form effective photosensitive area 605, and described effective photosensitive area all is positioned at the top silicon layer inside of SOI.The doping content of N-type doped region 604 is higher 3 more than the order of magnitude than the doping content of top layer silicon 603, makes most of depletion region be positioned at top layer silicon 603.

Cmos image sensor based on SOI technique shown in Figure 6 is collected photo-generated carrier by the effective photosensitive area 605 that is positioned at top layer silicon, and remaining operation principle is identical with the imageing sensor in Fig. 1.

There is following shortcoming in described the second at least based on the cmos image sensor of SOI technique: because its photosensitive area is arranged in top layer silicon, and in order to use complete depletion type SOI device, the thickness of top layer silicon 603 is generally less than 200nm, greatly limited the degree of depth of effective photosensitive area 605, make the efficiency of light absorption of this imageing sensor descend, especially for the redness of wavelength greater than 600nm, orange and sodium yellow, absorption efficiency is extremely low, and image quality is very undesirable.

Summary of the invention

The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of imageing sensor preparation method, for solving the poor signal to noise ratio of gained image and the problem of dynamic range of having reduced of radiation resistance of prior art imageing sensor, and the problem of effective limited reduction absorptivity of the photosensitive area degree of depth.

Reach for achieving the above object other relevant purposes, the invention provides a kind of imageing sensor preparation method, the method comprises the following steps at least:

1) provide the first Semiconductor substrate and the second Semiconductor substrate, wherein, the first Semiconductor substrate comprises: the first support substrates, be positioned at lip-deep the first insulating buried layer of described the first support substrates and be positioned at lip-deep the first top-layer semiconductor of described the first insulating buried layer;

2) at described the first semiconductor substrate surface or described the second semiconductor substrate surface, form the second insulating buried layer;

3) described the first Semiconductor substrate of bonding and the second Semiconductor substrate, and make described the second insulating buried layer between described the first top-layer semiconductor and the second Semiconductor substrate;

4) by described the second Semiconductor substrate attenuate, form second top-layer semiconductor different from the first top-layer semiconductor thickness, wherein, what in described the first top-layer semiconductor and the second top-layer semiconductor, thickness was thicker is thick film layers, otherwise, be thin layer;

5) on described the second top-layer semiconductor surface, define I zone and II zone, and at the regional windowing of described I until expose described the first top-layer semiconductor surface;

6) and II zone regional at described I completes the preparation of optical sensor device and pixel readout circuit, and wherein, described optical sensor device preparation is in described thick film layers, and the isolation between the formation adjacent devices, to complete the preparation of imageing sensor.

Alternatively, described the first top-layer semiconductor is thin layer, and thickness range is 0.1 μ m～0.3 μ m, and described the second top-layer semiconductor is thick film layers, and thickness range is 0.3 μ m～10 μ m.

Alternatively, described the first top-layer semiconductor is thick film layers, and thickness range is 0.3 μ m～10 μ m, and described the second top-layer semiconductor is thin layer, and thickness range is 0.1 μ m～0.3 μ m.

Alternatively, the material of described the first top-layer semiconductor and the second top-layer semiconductor is respectively the semi-conducting material for the preparation of semiconductor device, comprises at least any one in silicon, strained silicon, germanium and SiGe; Described the first support substrates is ordinary semiconductor substrates, comprises at least silicon substrate or Sapphire Substrate.

Alternatively, described step 6) in, described optical sensor device comprises a kind of in light sensitive diode and photoelectricity door at least; Described pixel readout circuit is three pipe pixel readout circuits or four pipe pixel readout circuits, wherein, described three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and described four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor.

Alternatively, the reset transistor of described pixel readout circuit, amplifier transistor and row selecting transistor preparation are in described thin layer; When described pixel readout circuit was four pipe pixel readout circuits, the transfering transistor preparation of described pixel readout circuit was in thick film layers.

Alternatively, described the second Semiconductor substrate is the Semiconductor substrate with insulating buried layer, comprises at least silicon-on-insulator or germanium on insulator; Described step 4) thinning process in comprises sequentially etching or corrodes support substrates and the insulating buried layer of described the second Semiconductor substrate.

Alternatively, the thinning process described step 4) also comprises the planarization process after etching or corrosion process.

Alternatively, described the first top-layer semiconductor is thin layer, and when described the second top-layer semiconductor was thick film layers, described the second Semiconductor substrate was ordinary semiconductor substrates, comprises at least silicon substrate; Described step 4) thinning process in comprises the etching of preorder or the planarization process of corrosion process and postorder.

Alternatively, described the second Semiconductor substrate is ordinary semiconductor substrates, comprises at least silicon substrate; Described step 1) also comprise, at described the second semiconductor substrate surface, carry out the H Implantation, the degree of depth of Implantation is described step 4) in the thickness of the second top-layer semiconductor; At this moment, described step 4) attenuate in adopts high annealing, makes H Implantation dielectric layer place form continuous airport, and then at described H Implantation dielectric layer place, described the second Semiconductor substrate is realized peeling off, to form described the second top-layer semiconductor.

As mentioned above, a kind of imageing sensor preparation method of the present invention has following beneficial effect:

1) the optical sensor device preparation, in the top-layer semiconductor as thick film layers, can realize darker PN junction depletion region, thereby have higher efficiency of light absorption.

2) the pixel readout circuit preparation, in the top-layer semiconductor as thin layer, exhausts its MOS transistor entirely, and circuit has the premium properties of high speed, low-power consumption, anti-breech lock.

3) optical sensor device of imageing sensor and pixel readout circuit are realized electric isolation by the first insulating buried layer and the second insulating buried layer and the first support substrates and the second support substrates respectively, have improved the ability of its anti-High energy particles Radiation.

The accompanying drawing explanation

Fig. 1 a to Fig. 1 f is shown as the schematic diagram of imageing sensor preparation method of the present invention in embodiment mono-.

Fig. 2 a to Fig. 2 f is shown as the schematic diagram of imageing sensor preparation method of the present invention in embodiment bis-.

Fig. 3 a to Fig. 3 e is shown as the schematic diagram of imageing sensor preparation method of the present invention in embodiment tri-.

Fig. 4 a to Fig. 4 f is shown as the schematic diagram of imageing sensor preparation method of the present invention in embodiment tetra-.

Fig. 5 is shown as the schematic diagram of first kind cmos image sensor in prior art.

Fig. 6 is shown as the schematic diagram of Equations of The Second Kind cmos image sensor in prior art.

The element numbers explanation

11 first support substrates

12 first insulating buried layers

13 first top-layer semiconductor

1 first Semiconductor substrate

The support substrates of 21 second Semiconductor substrate

The insulating buried layer of 22 second Semiconductor substrate

The top-layer semiconductor of 23 second Semiconductor substrate

2 second Semiconductor substrate

3 second insulating buried layers

4 second top-layer semiconductor

5 optical sensor devices

6,504,606 pixel readout circuits

7 isolation

8,505 transfering transistors

9,506 floating diffusion regions

A-A, B-B, A '-A ', B '-B ' face

C-C Implantation depth location

501,601 substrate silicon

502,602 insulating barriers

503, the top layer silicon of 603 P type doping

N-type doped well region in 507 substrate silicon

508 surperficial P type doped regions

509 silicon dioxide layers

510,605 effective photosensitive areas

The N-type doped region of 604 top layer silicon

Embodiment

Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.

The invention provides a kind of imageing sensor preparation method, at first, the first Semiconductor substrate and the second Semiconductor substrate are provided, wherein, the first Semiconductor substrate comprises: the first support substrates, be positioned at lip-deep the first insulating buried layer of described the first support substrates and be positioned at lip-deep the first top-layer semiconductor of described the first insulating buried layer; Secondly, at described the first semiconductor substrate surface or described the second semiconductor substrate surface, form the second insulating buried layer, described the first Semiconductor substrate of bonding and the second Semiconductor substrate, and make described the second insulating buried layer between described the first top-layer semiconductor and the second Semiconductor substrate; Again, by described the second Semiconductor substrate attenuate, form second top-layer semiconductor different from the first top-layer semiconductor thickness, wherein, what in described the first top-layer semiconductor and the second top-layer semiconductor, thickness was thicker is thick film layers, otherwise, be thin layer; Then, on described the second top-layer semiconductor surface, define I zone and II zone, and at the regional windowing of described I until expose described the first top-layer semiconductor surface; Finally, in described I zone and II zone, complete the preparation of optical sensor device and pixel readout circuit, wherein, described optical sensor device preparation is in described thick film layers, and the isolation between the formation adjacent devices, to complete the preparation of imageing sensor.

Refer to Fig. 1 a to Fig. 6.It should be noted that, the diagram that provides in following specific embodiment only illustrates basic conception of the present invention in a schematic way, satisfy in graphic only show with the present invention in relevant assembly but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.

Embodiment mono-

As shown in Fig. 1 a to Fig. 1 f, the invention provides a kind of imageing sensor preparation method, the method comprises the following steps at least:

As shown in Figure 1a, at first perform step 1) the first Semiconductor substrate 1 and the second Semiconductor substrate 2 be provided, wherein, the first Semiconductor substrate 1 comprises: the first support substrates 11, be positioned at lip-deep the first insulating buried layer 12 of described the first support substrates 11 and be positioned at lip-deep the first top-layer semiconductor 13 of described the first insulating buried layer 12.

Wherein, the material of described the first top-layer semiconductor 13 is the semi-conducting material for the preparation of semiconductor device, comprises at least any one in silicon, strained silicon, germanium and SiGe; Described the first insulating buried layer 12 is single layer structure or laminated construction, and described single layer structure wherein or the material of the every one deck in described laminated construction are any one in silica, silicon nitride and silicon oxynitride; Described the first support substrates 11 is ordinary semiconductor substrates (comprising at least silicon substrate or Sapphire Substrate); Described the second Semiconductor substrate 2 is for ordinary semiconductor substrates (comprising at least silicon substrate) or have the Semiconductor substrate (comprise at least silicon-on-insulator or germanium on insulator, its backing material comprises silicon or sapphire) of insulating buried layer.Particularly, in the present embodiment one, described the first top-layer semiconductor 13 is monocrystalline silicon layer, described the first insulating buried layer 12 is the silica single layer structure, described the first support substrates 11 is the silicon materials support substrates, described the second Semiconductor substrate 2 is silicon substrate, and the surface B ' of described the second Semiconductor substrate 2-B ' face represents (as shown in Figure 1a).

It should be noted that, described the first top-layer semiconductor 13 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, in the present embodiment one, described the first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, and the surface of the first top-layer semiconductor 13 of described the first Semiconductor substrate 1 represents (as shown in Figure 1a) with the A-A face.Then perform step 2).

As shown in Figure 1 b, in step 2) in, on described the second Semiconductor substrate 2 surface, form the second insulating buried layers 3 (the B-B face in Fig. 1 b represent shown in the surface of the second insulating buried layer 3), the method that forms the second insulating buried layer 3 employings comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at described second Semiconductor substrate 2 surface deposition the second insulating buried layer materials, to form the second insulating buried layer 3; Or described the second Semiconductor substrate 2 of thermal oxidation, the oxide layer that its surface is formed is as the second insulating buried layer 3.In the present embodiment one, adopt thermal oxidation process, the oxide layer that described the second Semiconductor substrate 2 surfaces are formed is as the second insulating buried layer 3.

It should be noted that, in another embodiment, aforesaid step 2), on described the first Semiconductor substrate 1 surface, form the second insulating buried layer 3 (A ' in Fig. 1 f-A ' face represent shown in the surface of the second insulating buried layer 3), the method that forms the second insulating buried layer 3 employings this moment comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at described first Semiconductor substrate 1 surface deposition the second insulating buried layer material, to form the second insulating buried layer 3; Or described the first Semiconductor substrate 1 of thermal oxidation, the oxide layer that its surface is formed is as the second insulating buried layer 3.

What need to illustrate is, described the second insulating buried layer 3 is single layer structure or laminated construction, described single layer structure wherein or the material of the every one deck in described laminated construction are any one in silica, silicon nitride and silicon oxynitride, in the present embodiment one, described the second insulating buried layer 3 is the silica of single layer structure.Then perform step 3).

As shown in Fig. 1 c, in step 3) in, after the described second Semiconductor substrate 2 upper formation in surface the second insulating buried layers 3, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with the first top-layer semiconductor 13 of described the first Semiconductor substrate 1, namely in Fig. 1 c, the present embodiment one adopts conventional bonding techniques (Si-SiO ₂Bonding), the A-A face (also as shown in Figure 1a) on the first top-layer semiconductor 13 surfaces of described the first Semiconductor substrate 1 of expression is aimed to bonding with the B-B face (also as shown in Figure 1 b) on described the second insulating buried layer 3 surfaces of expression, at this moment, described the second insulating buried layer 3 is between described the first top-layer semiconductor 13 and the second Semiconductor substrate 2.it should be noted that, in another embodiment, aforesaid step 3) after the surperficial above formation of described the first Semiconductor substrate 1 the second insulating buried layer 3, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with described the second Semiconductor substrate 2 surfaces, namely adopt conventional bonding techniques, the B ' on described the second Semiconductor substrate 2 surfaces of expression-B ' face (as shown in Figure 1a) is aimed to bonding with the A ' that represents described the second insulating buried layer 3 surfaces-A ' face (as shown in Figure 1 f), at this moment, described the second insulating buried layer 3 is between described the first top-layer semiconductor 13 and the second Semiconductor substrate 2.Then perform step 4).

As shown in Fig. 1 d, in step 4) in, by described the second Semiconductor substrate 2 attenuates, form the second top-layer semiconductor 4.Described the second top-layer semiconductor 4 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, particularly, in the present embodiment one, because selected described the first top-layer semiconductor 13 is the thin layer of thickness between 0.1 μ m～0.3 μ m, at this moment, 4 of required the second top-layer semiconductor are the thick film layers of thickness between 0.3 μ m～10 μ m, and wherein 2 μ m～3 μ m are the preferred thickness of the second top-layer semiconductor 4.It should be noted that, in another embodiment, when selected described the first top-layer semiconductor 13 was the thick film layers of thickness between 0.3 μ m～10 μ m, required the second top-layer semiconductor 4 was the thin layer of thickness between 0.1 μ m～0.3 μ m.

in the present embodiment one, as shown in Fig. 1 d, described the first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, described the second Semiconductor substrate 2 is silicon substrate, and required the second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m, described step 4) thinning process in comprises the etching of preorder or the planarization process of corrosion process and postorder, be about to carry out again planarization after described the second Semiconductor substrate 2 (silicon substrate) etching or corrosion, particularly, adopt cmp method to realize described planarization, to form the second top-layer semiconductor 4, wherein said the second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m.Then perform step 5).

as shown in Fig. 1 e, in step 5) in, on described the second top-layer semiconductor 4 surfaces, define I zone and II zone, and at described I zone windowing until expose described the first top-layer semiconductor 13 surfaces, wherein, the technique that described I zone windowing is adopted is conventional photoetching, etching (comprising at least inductively coupled plasma etching or reactive ion etching) and corrosion, in the present embodiment one, adopt conventional photoetching, reactive ion etching and corrosion, on described the second top-layer semiconductor 4 surfaces to defined described I zone windowing, until expose described the first top-layer semiconductor 13 surfaces.Then perform step 6).

As shown in Fig. 1 e, in step 6) in, in described I zone and II zone, complete the preparation of optical sensor device 5 and pixel readout circuit 6, wherein, described optical sensor device 5 preparations are in described thick film layers, and adopt shallow trench isolation or dielectric isolation to form the isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

It should be noted that, described optical sensor device 5 comprises a kind of in light sensitive diode (comprising at least PN junction light sensitive diode or PIN knot light sensitive diode) and photoelectricity door at least, and preparation is in described thick film layers; Described pixel readout circuit 6 is three pipe pixel readout circuits, four pipe pixel readout circuit or other pixel readout circuits that are comprised of MOS transistor: described three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and preparation is in described thin layer; Described four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor, wherein, the transfering transistor preparation of described four pipe pixel readout circuits is in thick film layers, and the reset transistor of described four pipe pixel readout circuits, amplifier transistor and row selecting transistor preparation are in described thin layer.Particularly, in the present embodiment one, as shown in Fig. 1 e, described optical sensor device 5 is the PN junction light sensitive diode, and described pixel readout circuit 6 is three pipe pixel readout circuits (only with transistor diagram pixel readout circuits).

in the present embodiment one, described the first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, described the second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m, described I zone windowing is until expose described the first top-layer semiconductor 13 surfaces, described II zone is in described the second top-layer semiconductor 4, as shown in Fig. 1 e, described optical sensor device 5 is the PN junction light sensitive diode, preparation is in the II zone of described the second top-layer semiconductor 4 as thick film layers, described pixel readout circuit 6 is the I zone of three pipe pixel readout circuits (transistor of only usining illustrates pixel readout circuit) preparation in described the first top-layer semiconductor 13 as thin layer, the dielectric isolation is adopted in isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

Imageing sensor prepared by the present invention has good radiation resistance, and the imageing sensor photosensitive region has higher efficiency of light absorption, the circuit of imageing sensor has the premium properties of high speed, low-power consumption, anti-breech lock simultaneously, and namely imageing sensor has good semiconducting behavior.

Embodiment bis-

As shown in Fig. 2 a to Fig. 2 f, the invention provides a kind of imageing sensor preparation method, the method comprises the following steps at least:

As shown in Figure 2 a, at first perform step 1) the first Semiconductor substrate 1 and the second Semiconductor substrate 2 be provided, wherein, the first Semiconductor substrate 1 comprises: the first support substrates 11, be positioned at lip-deep the first insulating buried layer 12 of described the first support substrates 11 and be positioned at lip-deep the first top-layer semiconductor 13 of described the first insulating buried layer 12.

Wherein, the material of described the first top-layer semiconductor 13 is the semi-conducting material for the preparation of semiconductor device, comprises at least any one in silicon, strained silicon, germanium and SiGe; Described the first insulating buried layer 12 is single layer structure or laminated construction, and described single layer structure wherein or the material of the every one deck in described laminated construction are any one in silica, silicon nitride and silicon oxynitride; Described the first support substrates 11 is ordinary semiconductor substrates (comprising at least silicon substrate or Sapphire Substrate); Described the second Semiconductor substrate 2 is for ordinary semiconductor substrates (comprising at least silicon substrate) or have the Semiconductor substrate (comprise at least silicon-on-insulator or germanium on insulator, its backing material can be silicon or sapphire) of insulating buried layer.particularly, in the present embodiment two, described the first top-layer semiconductor 13 is monocrystalline silicon layer, described the first insulating buried layer 12 is the silicon nitride single layer structure, described the first support substrates 11 is the sapphire material support substrates, described the second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI) comprising: the support substrates 21 of the second Semiconductor substrate 2, be positioned at the insulating buried layer 22 of lip-deep the second Semiconductor substrate 2 of described support substrates 21, and the top-layer semiconductor 23 that is positioned at lip-deep the second Semiconductor substrate 2 of described insulating buried layer 22, wherein, described support substrates 21 is Sapphire Substrate, described insulating buried layer 22 is silica, described top-layer semiconductor 23 is silicon, top-layer semiconductor 23 surfaces of described the second Semiconductor substrate 2 represent (as shown in Figure 2 a) with the B-B face.

It should be noted that, described the first top-layer semiconductor 13 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, in the present embodiment two, described the first top-layer semiconductor 13 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, wherein, 0.15 μ m～0.2 μ m is described the first top-layer semiconductor 13 preferred thickness, the surface A ' of the first top-layer semiconductor 13 of described the first Semiconductor substrate 1-A ' face represents (as shown in Figure 2 a).

what need to further illustrate is, described the second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI), the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, in the present embodiment two, because described the first top-layer semiconductor 13 is thickness thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m, the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is the thick film layers of thickness between 0.3 μ m～10 μ m, wherein, 3 μ m～5 μ m are the preferred thickness of the top-layer semiconductor 23 of described the second Semiconductor substrate 2.In another embodiment, when selected described the first top-layer semiconductor 13 was the thick film layers of thickness between 0.3 μ m～10 μ m, the top-layer semiconductor 23 of described the second Semiconductor substrate 2 was elected the thin layer of thickness between 0.1 μ m～0.3 μ m as.Then perform step 2).

As shown in Figure 2 b, in step 2) in, on described the first Semiconductor substrate 1 surface, form the second insulating buried layer 3 (the A-A face in Fig. 2 b represent shown in the surface of the second insulating buried layer 3), the method that forms the second insulating buried layer 3 employings this moment comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at described first Semiconductor substrate 1 surface deposition the second insulating buried layer material, to form the second insulating buried layer 3; Or described the first Semiconductor substrate 1 of thermal oxidation, the oxide layer that its surface is formed is as the second insulating buried layer 3.In the present embodiment two, adopt chemical gaseous phase depositing process, at described first Semiconductor substrate 1 surface deposition the second insulating buried layer material, to form the second insulating buried layer 3.

It should be noted that, in another embodiment, aforesaid step 2), on described the second Semiconductor substrate 2 surface, form the second insulating buried layers 3 (B ' in Fig. 2 f-B ' face represent shown in the surface of the second insulating buried layer 3), the method that forms the second insulating buried layer 3 employings comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at described second Semiconductor substrate 2 surface deposition the second insulating buried layer materials, to form the second insulating buried layer 3; Or described the second Semiconductor substrate 2 of thermal oxidation, the oxide layer that its surface is formed is as the second insulating buried layer 3.

What need to illustrate is, described the second insulating buried layer 3 is single layer structure or laminated construction, described single layer structure wherein or the material of the every one deck in described laminated construction are any one in silica, silicon nitride and silicon oxynitride, in the present embodiment two, described the second insulating buried layer 3 is the silicon oxynitride of single layer structure.Then perform step 3).

as shown in Figure 2 c, in step 3) in, after the described first Semiconductor substrate 1 upper formation in surface the second insulating buried layer 3, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with described the second Semiconductor substrate 2 surfaces, namely in Fig. 2 c, adopt conventional bonding techniques, the B-B face (also as shown in Figure 2 a) on described the second Semiconductor substrate 2 surfaces of expression is aimed to bonding with the A-A face (also as shown in Figure 2 b) on described the second insulating buried layer 3 surfaces of expression, at this moment, described the second insulating buried layer 3 is between described the first top-layer semiconductor 13 and the second Semiconductor substrate 2.it should be noted that, in another embodiment, aforesaid step 3) after the surperficial above formation of described the second Semiconductor substrate 2 the second insulating buried layers 3, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with the first top-layer semiconductor 13 of described the first Semiconductor substrate 1, namely adopt conventional bonding techniques, the A ' on the first top-layer semiconductor 13 surfaces of described the first Semiconductor substrate 1 of expression-A ' face (as shown in Figure 2 a) is aimed to bonding with the B ' that represents described the second insulating buried layer 3 surfaces-B ' face (as shown in Fig. 2 f), at this moment, described the second insulating buried layer 3 is between described the first top-layer semiconductor 13 and the second Semiconductor substrate 2.Then perform step 4).

As shown in Figure 2 d, in step 4) in, by described the second Semiconductor substrate 2 attenuates, form the second top-layer semiconductor 4.Described the second top-layer semiconductor 4 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, in the present embodiment two, because selected described the first top-layer semiconductor 13 is thickness thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m, at this moment, 4 of required the second top-layer semiconductor are the thick film layers of thickness between 0.3 μ m～10 μ m.It should be noted that, in another embodiment, when selected described the first top-layer semiconductor 13 was the thick film layers of thickness between 0.3 μ m～10 μ m, required the second top-layer semiconductor 4 was the thin layer of thickness between 0.1 μ m～0.3 μ m.

In the present embodiment two, as shown in Figure 2 d, described the first top-layer semiconductor 13 is thickness thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m; Described the second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI, its backing material is sapphire), and the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is thickness thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m, and required the second top-layer semiconductor 4 is the thick film layers of thickness between 0.3 μ m～10 μ m.Thereby, described step 4) thinning process in comprises: first etching or corrode the support substrates 21 of described the second Semiconductor substrate 2, etching or corrode the insulating buried layer 22 of described the second Semiconductor substrate 2 again, the top-layer semiconductor 23 that only keeps described the second Semiconductor substrate 2, to form the second top-layer semiconductor 4, wherein, the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is aforementioned the second top-layer semiconductor 4, for thickness between 0.3 μ m～10 μ m the silicon materials thick film layers of (preferred thickness is 3 μ m～5 μ m).Further, in another embodiment, etching or corrode the support substrates 21 and insulating buried layer 22 of described the second Semiconductor substrate 2 after, top-layer semiconductor 23 to described the second Semiconductor substrate 2 is carried out planarization again, particularly, described planarization adopts cmp method to realize, to form described the second top-layer semiconductor 4, wherein said the second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m.Then perform step 5).

as shown in Figure 2 e, in step 5) in, on described the second top-layer semiconductor 4 surfaces, define I zone and II zone, and at described I zone windowing until expose described the first top-layer semiconductor 13 surfaces, wherein, the technique that described I zone windowing is adopted is conventional photoetching, etching (comprising at least inductively coupled plasma etching or reactive ion etching) and corrosion, in the present embodiment two, adopt conventional photoetching, reactive ion etching and corrosion, on described the second top-layer semiconductor 4 surfaces to defined described I zone windowing, until expose described the first top-layer semiconductor 13 surfaces.Then perform step 6).

As shown in Figure 2 e, in step 6) in, in described I zone and II zone, complete the preparation of optical sensor device 5 and pixel readout circuit 6, wherein, described optical sensor device 5 preparations are in described thick film layers, and adopt shallow trench isolation or dielectric isolation to form the isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

It should be noted that, described optical sensor device 5 comprises a kind of in light sensitive diode (comprising at least PN junction light sensitive diode or PIN knot light sensitive diode) and photoelectricity door at least, and preparation is in described thick film layers; Described pixel readout circuit 6 is three pipe pixel readout circuits, four pipe pixel readout circuit or other pixel readout circuits that are comprised of MOS transistor: described three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and preparation is in described thin layer; Described four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor, wherein, the transfering transistor preparation of described four pipe pixel readout circuits is in thick film layers, and the reset transistor of described four pipe pixel readout circuits, amplifier transistor and row selecting transistor preparation are in described thin layer.particularly, in the present embodiment two, as shown in Figure 2 e, described optical sensor device 5 is the PN junction light sensitive diode, described pixel readout circuit 6 is four pipe pixel readout circuits, wherein, the reset transistor of described four pipe pixel readout circuits, amplifier transistor and row selecting transistor are only with a transistor signal (seeing Fig. 2 e), the transfering transistor 8 of described four pipe pixel readout circuits, the reset transistor of the zone that floating diffusion region 9 is prepared and described four pipe pixel readout circuits, the prepared zone of amplifier transistor and row selecting transistor is respectively in two different zones.

in the present embodiment two, described the first top-layer semiconductor 13 is thickness silicon materials thin layer of (preferred thickness is 0.15 μ m～0.2 μ m) between 0.1 μ m～0.3 μ m, described the second Semiconductor substrate 2 is silicon-on-insulator (SOI, its backing material is sapphire), described the second top-layer semiconductor 4 (being the top-layer semiconductor 23 of described the second Semiconductor substrate 2) is thickness silicon materials thick film layers of (preferred thickness is 3 μ m～5 μ m) between 0.3 μ m～10 μ m, described I zone windowing is until expose described the first top-layer semiconductor 13 surfaces, described II zone is in described the second top-layer semiconductor 4, as shown in Figure 2 e, described optical sensor device 5 is the PN junction light sensitive diode, preparation is in the II zone of described the second top-layer semiconductor 4 as thick film layers, described pixel readout circuit 6 is four pipe pixel readout circuits, wherein, the reset transistor of described four pipe pixel readout circuits, amplifier transistor and row selecting transistor are only with a transistor signal, all prepare the I zone in described the first top-layer semiconductor 13 as thin layer, transfering transistor 8 and the floating diffusion region 9 of described four pipe pixel readout circuits all prepare the II zone in described the second top-layer semiconductor 4 as thick film layers, the dielectric isolation is adopted in isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

Embodiment tri-

Embodiment tri-and embodiment mono-adopt essentially identical technical scheme, main difference is: in embodiment mono-, the first top-layer semiconductor 13 of described the first Semiconductor substrate 1 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, and described the second top-layer semiconductor 4 is thickness silicon materials thick film layers of (preferred thickness is 2 μ m～3 μ m) between 0.3 μ m～10 μ m; In embodiment tri-, the first top-layer semiconductor 13 of described the first Semiconductor substrate 1 is thickness strained silicon materials thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m, described the second Semiconductor substrate 2 is silicon-on-insulator (SOI), and the top-layer semiconductor 23 of described the second top-layer semiconductor 4 and described the second Semiconductor substrate 2 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.

As shown in Fig. 3 a to Fig. 3 e, the invention provides a kind of imageing sensor preparation method, the method comprises the following steps at least:

As shown in Figure 3 a, essentially identical step 1 in execution and embodiment mono-), difference is:

in the present embodiment three, described the first top-layer semiconductor 13 is thickness strained silicon materials thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m, described the second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI) comprising: the support substrates 21 of the second Semiconductor substrate 2, be positioned at the insulating buried layer 22 of lip-deep the second Semiconductor substrate 2 of described support substrates 21, and the top-layer semiconductor 23 that is positioned at lip-deep the second Semiconductor substrate 2 of described insulating buried layer 22, wherein, described support substrates 21 is silicon substrate, described insulating buried layer 22 is silica, described top-layer semiconductor 23 is silicon, particularly, the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.

Then perform step 2), as shown in Fig. 3 b, namely in the present embodiment three, adopt physical gas-phase deposite method, at described second Semiconductor substrate 2 surface deposition the second insulating buried layer materials, to form the second insulating buried layer 3, and described the second insulating buried layer 3 is double-deck laminated construction, and wherein the material of every one deck is respectively silicon nitride and silicon oxynitride.

Then carry out the step 3 that embodiment mono-is identical), as shown in Figure 3 c, namely, in the present embodiment three, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with the first top-layer semiconductor 13 of described the first Semiconductor substrate 1.Then perform step 4).

as shown in Figure 3 d, essentially identical step 4 in execution and embodiment mono-), difference is: in the present embodiment three, described the first top-layer semiconductor 13 is thickness thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m, described the second Semiconductor substrate 2 is for having the Semiconductor substrate of insulating buried layer, preferred silicon-on-insulator (SOI), and the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is the thin layer of thickness between 0.1 μ m～0.3 μ m, required the second top-layer semiconductor 4 is the thin layer of thickness between 0.1 μ m～0.3 μ m.

It should be noted that, step 4) in, embodiment tri-adopts identical thinning process with embodiment mono-, be first etching or the support substrates 21 of corroding described the second Semiconductor substrate 2, etching or corrode the insulating buried layer 22 of described the second Semiconductor substrate 2 again, the top-layer semiconductor 23 that only keeps described the second Semiconductor substrate 2, to form the second top-layer semiconductor 4, wherein, the top-layer semiconductor 23 of described the second Semiconductor substrate 2 is aforementioned the second top-layer semiconductor 4, is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.Further, in another embodiment, etching or corrode the support substrates 21 and insulating buried layer 22 of described the second Semiconductor substrate 2 after, top-layer semiconductor 23 to described the second Semiconductor substrate 2 is carried out planarization again, particularly, adopt cmp method to realize described planarization, to form the second top-layer semiconductor 4, wherein said the second top-layer semiconductor 4 is the thin layer of thickness between 0.1 μ m～0.3 μ m.Then perform step 5).

Then perform step 5), as shown in Figure 3 e, namely, in the present embodiment three, adopt conventional photoetching, inductively coupled plasma etching and corrosion, on described the second top-layer semiconductor 4 surfaces to defined described I zone windowing, until expose described the first top-layer semiconductor 13 surfaces.Then perform step 6).

As shown in Figure 3 e, essentially identical step 6 in execution and embodiment mono-), difference is:

in the present embodiment three, described the first top-layer semiconductor 13 is thickness strained silicon materials thick film layers of (preferred thickness is 6 μ m～8 μ m) between 0.3 μ m～10 μ m, described the second Semiconductor substrate 2 is silicon-on-insulator (SOI), described the second top-layer semiconductor 4 (being the top-layer semiconductor 23 of described the second Semiconductor substrate 2) is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, described I zone windowing is until expose described the first top-layer semiconductor 13 surfaces, described II zone is in described the second top-layer semiconductor 4, as shown in Figure 3 e, described optical sensor device 5 is the PN junction light sensitive diode, preparation is in the I zone of described the first top-layer semiconductor 13 as thick film layers, described pixel readout circuit 6 is the II zone of three pipe pixel readout circuits (transistor of only usining illustrates pixel readout circuit) preparation in described the second top-layer semiconductor 4 as thin layer.

It should be noted that step 6) in, embodiment tri-is with embodiment mono-something in common:

I) described optical sensor device 5 is identical with described pixel readout circuit 6, as shown in Figure 3 e, namely in the present embodiment three, described optical sensor device 5 is the PN junction light sensitive diode, and described pixel readout circuit 6 is three pipe pixel readout circuits (only with transistor diagram pixel readout circuit zones).

Ii) partition method is identical, and as shown in Figure 3 e, namely in the present embodiment three, the dielectric isolation is adopted in the isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

Embodiment tetra-

As shown in Fig. 4 a to Fig. 4 f, the invention provides a kind of imageing sensor preparation method, the method comprises the following steps at least:

As shown in Fig. 4 a, at first perform step 1) the first Semiconductor substrate 1 and the second Semiconductor substrate 2 be provided, wherein, the first Semiconductor substrate 1 comprises: the first support substrates 11, be positioned at lip-deep the first insulating buried layer 12 of described the first support substrates 11 and be positioned at lip-deep the first top-layer semiconductor 13 of described the first insulating buried layer 12.

Wherein, the material of described the first top-layer semiconductor 13 is the semi-conducting material for the preparation of semiconductor device, comprises at least any one in silicon, strained silicon, germanium and SiGe; Described the first insulating buried layer 12 is single layer structure or laminated construction, and described single layer structure wherein or the material of the every one deck in described laminated construction are any one in silica, silicon nitride and silicon oxynitride; Described the first support substrates 11 is ordinary semiconductor substrates (comprising at least silicon substrate or Sapphire Substrate); Described the second Semiconductor substrate 2 is for ordinary semiconductor substrates (comprising at least silicon substrate) or have the Semiconductor substrate (comprise at least silicon-on-insulator or germanium on insulator, its backing material comprises silicon or sapphire) of insulating buried layer.Particularly, in the present embodiment four, described the first top-layer semiconductor 13 is germanium-silicon layer, described the first insulating buried layer 12 is the silicon oxynitride single layer structure, described the first support substrates 11 is the sapphire material support substrates, described the second Semiconductor substrate 2 is silicon substrate, and the surface of described the second Semiconductor substrate 2 represents (as shown in Fig. 4 a) with the B-B face.

It should be noted that, described the first top-layer semiconductor 13 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, in the present embodiment four, described the first top-layer semiconductor 13 is thickness silicon germanium material thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m, and the surface A ' of the first top-layer semiconductor 13 of described the first Semiconductor substrate 1-A ' face represents (as shown in Fig. 4 a).Then perform step 2).

As shown in Figure 4 b, in step 2) in, on described the first Semiconductor substrate 1 surface, form the second insulating buried layer 3 (the A-A face in Fig. 4 b represent shown in the surface of the second insulating buried layer 3), the method that forms the second insulating buried layer 3 employings this moment comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at described first Semiconductor substrate 1 surface deposition the second insulating buried layer material, to form the second insulating buried layer 3; Or described the first Semiconductor substrate 1 of thermal oxidation, the oxide layer that its surface is formed is as the second insulating buried layer 3.In the present embodiment four, adopt chemical gaseous phase depositing process, at described first Semiconductor substrate 1 surface deposition the second insulating buried layer material, to form the second insulating buried layer 3.

It should be noted that, in another embodiment, aforesaid step 2), on described the second Semiconductor substrate 2 surface, form the second insulating buried layers 3 (B ' in Fig. 4 f-B ' face represent shown in the surface of the second insulating buried layer 3), the method that forms the second insulating buried layer 3 employings comprises: adopt chemical gaseous phase depositing process or physical gas-phase deposite method, at described second Semiconductor substrate 2 surface deposition the second insulating buried layer materials, to form the second insulating buried layer 3; Or described the second Semiconductor substrate 2 of thermal oxidation, the oxide layer that its surface is formed is as the second insulating buried layer 3.

What need to illustrate is, described the second insulating buried layer 3 is single layer structure or laminated construction, described single layer structure wherein or the material of the every one deck in described laminated construction are any one in silica, silicon nitride and silicon oxynitride, in the present embodiment four, described the second insulating buried layer 3 is the silicon nitride of single layer structure.Then perform step 3).

As shown in Fig. 4 c, in step 3) in, after the described first Semiconductor substrate 1 upper formation in surface the second insulating buried layer 3, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with described the second Semiconductor substrate 2 surfaces, namely adopt conventional bonding techniques, the B-B face (also as shown in Fig. 4 a) on described the second Semiconductor substrate 2 surfaces of expression is aimed to bonding with the A-A face (also as shown in Figure 4 b) on the second insulating buried layer 3 surfaces as described in expression, at this moment, described the second insulating buried layer 3 is between described the first top-layer semiconductor 13 and the second Semiconductor substrate 2.it should be noted that, in another embodiment, aforesaid step 3) after the surperficial above formation of described the second Semiconductor substrate 2 the second insulating buried layers 3, adopt conventional bonding techniques, described the second insulating buried layer 3 is aimed to bonding with the first top-layer semiconductor 13 of described the first Semiconductor substrate 1, namely in Fig. 4 c, adopt conventional bonding techniques, by the A '-A ' face (also as shown in Fig. 4 a) on the first top-layer semiconductor 13 surfaces of described the first Semiconductor substrate 1 of expression with represent as described in the B '-B ' face (also as shown in Fig. 4 f) on the second insulating buried layer 3 surfaces aim at bonding, at this moment, described the second insulating buried layer 3 is between described the first top-layer semiconductor 13 and the second Semiconductor substrate 2.Then perform step 4).

As shown in Fig. 4 d, in step 4) in, by described the second Semiconductor substrate 2 attenuates, form the second top-layer semiconductor 4.Described the second top-layer semiconductor 4 is thin layer or thick film layers, wherein, described thin layer thickness range is 0.1 μ m～0.3 μ m, described thick film layers thickness range is 0.3 μ m～10 μ m, in the present embodiment four, because selected described the first top-layer semiconductor 13 is thickness thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m, at this moment, 4 of required the second top-layer semiconductor are the thin layer of thickness between 0.1 μ m～0.3 μ m.It should be noted that, in another embodiment, when selected described the first top-layer semiconductor 13 was the thin layer of thickness between 0.1 μ m～0.3 μ m, required the second top-layer semiconductor 4 was the thick film layers of thickness between 0.3 μ m～10 μ m.

In the present embodiment four, as shown in Fig. 4 d, described the first top-layer semiconductor 13 is thickness silicon germanium material thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m; Described the second Semiconductor substrate 2 is silicon substrate, and required the second top-layer semiconductor 4 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, what need to further illustrate is, described step 1) also comprise, on described the second Semiconductor substrate 2 surfaces, carry out the H Implantation, the surperficial 0.1 μ m of depth distance the second Semiconductor substrate 2 of Implantation～0.3 μ m (position as shown in C-C face in Fig. 4 a), this Implantation degree of depth is the thickness of required the second top-layer semiconductor 4; At this moment, described step 4) attenuate in adopts high annealing, make H Implantation dielectric layer position (position as shown in C-C face in Fig. 4 c) form continuous airport, and then described H Implantation dielectric layer position (position as shown in C-C face in Fig. 4 c) to as described in the second Semiconductor substrate 2 realize peeling off, to form the second top-layer semiconductor 4, wherein said the second top-layer semiconductor 4 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m.

what need specified otherwise is, in another embodiment, described the first top-layer semiconductor 13 is the thin layer of thickness between 0.1 μ m～0.3 μ m, required the second top-layer semiconductor 4 is the thick film layers of thickness between 0.3 μ m～10 μ m, what need to further illustrate is, described step 1) also comprise, on described the second Semiconductor substrate 2 surfaces, carry out the H Implantation, the surperficial 0.3 μ m of depth distance the second Semiconductor substrate 2 of Implantation～10 μ m, this Implantation degree of depth is the thickness of required the second top-layer semiconductor 4, at this moment, described step 4) attenuate in adopts high annealing, make H Implantation dielectric layer position form continuous airport, and then in described H Implantation dielectric layer position, described the second Semiconductor substrate 2 is realized peeling off, to form the second top-layer semiconductor 4, wherein said the second top-layer semiconductor 4 is the thick film layers of thickness between 0.3 μ m～10 μ m.Then perform step 5).

as shown in Fig. 4 e, in step 5) in, on described the second top-layer semiconductor 4 surfaces, define I zone and II zone, and at described I zone windowing until expose described the first top-layer semiconductor 13 surfaces, wherein, the technique that described I zone windowing is adopted is conventional photoetching, etching (comprising at least inductively coupled plasma etching or reactive ion etching) and corrosion, in the present embodiment four, adopt conventional photoetching, reactive ion etching and corrosion, on described the second top-layer semiconductor 4 surfaces to defined described I zone windowing, until expose described the first top-layer semiconductor 13 surfaces.Then perform step 6).

As shown in Fig. 4 e, in step 6) in, in described I zone and II zone, complete the preparation of optical sensor device 5 and pixel readout circuit 6, wherein, described optical sensor device 5 preparations are in described thick film layers, and adopt shallow trench isolation or dielectric isolation to form the isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

It should be noted that, described optical sensor device 5 comprises a kind of in light sensitive diode (comprising at least PN junction light sensitive diode or PIN knot light sensitive diode) and photoelectricity door at least, and preparation is in described thick film layers; Described pixel readout circuit 6 is three pipe pixel readout circuits or four pipe pixel readout circuit or other pixel readout circuits that are comprised of MOS transistor: described three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and preparation is in described thin layer; Described four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor, wherein, the transfering transistor preparation of described four pipe pixel readout circuits is in thick film layers, and the reset transistor of described four pipe pixel readout circuits, amplifier transistor and row selecting transistor preparation are in described thin layer.particularly, in the present embodiment four, as shown in Fig. 4 e, described optical sensor device 5 is the PN junction light sensitive diode, described pixel readout circuit 6 is four pipe pixel readout circuits, wherein, the reset transistor of described four pipe pixel readout circuits, amplifier transistor and row selecting transistor are only with a transistor signal (seeing Fig. 4 e), the transfering transistor 8 of described four pipe pixel readout circuits, the reset transistor of the zone that floating diffusion region 9 is prepared and described four pipe pixel readout circuits, the prepared zone of amplifier transistor and row selecting transistor is respectively in two different zones.

in the present embodiment four, described the first top-layer semiconductor 13 is thickness silicon germanium material thick film layers of (preferred thickness is 5 μ m～6 μ m) between 0.3 μ m～10 μ m, described the second top-layer semiconductor 4 is the silicon materials thin layer of thickness between 0.1 μ m～0.3 μ m, described I zone windowing is until expose described the first top-layer semiconductor 13 surfaces, described II zone is in described the second top-layer semiconductor 4, as shown in Fig. 4 e, described optical sensor device 5 is the PN junction light sensitive diode, preparation is in the I zone of described the first top-layer semiconductor 13 as thick film layers, described pixel readout circuit 6 is four pipe pixel readout circuits, the reset transistor of wherein said four pipe pixel readout circuits, amplifier transistor and row selecting transistor are only with a transistor signal, all prepare the II zone in described the second top-layer semiconductor 4 as thin layer, transfering transistor 8 and the floating diffusion region 9 of described four pipe pixel readout circuits all prepare the I zone in described the first top-layer semiconductor 13 as thick film layers, the dielectric isolation is adopted in isolation 7 between adjacent devices, to complete the preparation of imageing sensor.

In sum, imageing sensor preparation method of the present invention has following beneficial effect:

So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not be used to limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and know that usually the knowledgeable, not breaking away from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.

Claims

1. an imageing sensor preparation method, is characterized in that, the method comprises the following steps at least:

6) in described I zone and II zone, prepare optical sensor device and pixel readout circuit, and form the isolation between adjacent devices, to complete the preparation of imageing sensor, wherein, described optical sensor device preparation is in described thick film layers.

2. imageing sensor preparation method according to claim 1, it is characterized in that: described the first top-layer semiconductor is thin layer, thickness range is 0.1 μ m～0.3 μ m, and described the second top-layer semiconductor is thick film layers, and thickness range is 0.3 μ m～10 μ m.

3. imageing sensor preparation method according to claim 1, it is characterized in that: described the first top-layer semiconductor is thick film layers, thickness range is 0.3 μ m～10 μ m, and described the second top-layer semiconductor is thin layer, and thickness range is 0.1 μ m～0.3 μ m.

4. imageing sensor preparation method according to claim 1, it is characterized in that: the material of described the first top-layer semiconductor and the second top-layer semiconductor is respectively the semi-conducting material for the preparation of semiconductor device, comprises at least any one in silicon, strained silicon, germanium and SiGe; Described the first support substrates is ordinary semiconductor substrates, comprises at least silicon substrate or Sapphire Substrate.

5. imageing sensor preparation method according to claim 1 is characterized in that: in described step 6), described optical sensor device comprises a kind of in light sensitive diode and photoelectricity door at least; Described pixel readout circuit is three pipe pixel readout circuits or four pipe pixel readout circuits, wherein, described three pipe pixel readout circuits comprise reset transistor, amplifier transistor and row selecting transistor, and described four pipe pixel readout circuits comprise transfering transistor, reset transistor, amplifier transistor and row selecting transistor.

6. imageing sensor preparation method according to claim 5 is characterized in that: the reset transistor of described pixel readout circuit, amplifier transistor and row selecting transistor preparation are in described thin layer; When described pixel readout circuit was four pipe pixel readout circuits, the transfering transistor preparation of described pixel readout circuit was in thick film layers.

7. imageing sensor preparation method according to claim 1, it is characterized in that: described the second Semiconductor substrate is the Semiconductor substrate with insulating buried layer, comprises at least silicon-on-insulator or germanium on insulator; Thinning process in described step 4) comprises sequentially etching or corrodes support substrates and the insulating buried layer of described the second Semiconductor substrate.

8. imageing sensor preparation method according to claim 7 is characterized in that: the thinning process in described step 4) also comprises the planarization process after etching or corrosion process.

9. imageing sensor preparation method according to claim 2, it is characterized in that: described the second Semiconductor substrate is ordinary semiconductor substrates, comprises at least silicon substrate; Thinning process in described step 4) comprises the etching of preorder or the planarization process of corrosion process and postorder.

10. imageing sensor preparation method according to claim 1, it is characterized in that: described the second Semiconductor substrate is ordinary semiconductor substrates, comprises at least silicon substrate; Described step 1) also comprises, at described the second semiconductor substrate surface, carries out the H Implantation, and the degree of depth of Implantation is the thickness of the second top-layer semiconductor in described step 4); At this moment, the attenuate in described step 4) adopts high annealing, makes H Implantation dielectric layer place form continuous airport, and then at described H Implantation dielectric layer place, described the second Semiconductor substrate is realized peeling off, to form described the second top-layer semiconductor.