CN111128691A

CN111128691A - Method for manufacturing semiconductor device and method for manufacturing contact plug thereof

Info

Publication number: CN111128691A
Application number: CN201911046113.4A
Authority: CN
Inventors: 黄玉莲
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-10-31
Filing date: 2019-10-30
Publication date: 2020-05-08
Anticipated expiration: 2039-10-30
Also published as: US11121026B2; TW202018763A; TWI728493B; US20200135547A1; CN111128691B

Abstract

Methods of patterning openings of conductive contacts in a target layer of a semiconductor device, and methods of forming conductive contacts. The opening patterning method can be used to form contact openings in an interlayer dielectric layer of a semiconductor structure to provide contacts to source/drain regions of a finfet device. A cut MD pattern of a photoresist layer over a first intermediate layer of a four-layer photoresist is pattern transferred by photolithography to pattern a hard mask layer to form a cut curtain layer. After the cut-off layer is formed, contact openings are formed in an interlayer dielectric layer to source/drain regions of the finfet device of the semiconductor structure. The conductive material may be filled in the contact openings to define conductive contacts (e.g., conductive plugs).

Description

Method for manufacturing semiconductor device and method for manufacturing contact plug thereof

Technical Field

Embodiments of the present disclosure relate to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device and a method for fabricating the same, in which a target layer is patterned by four photoresist layers.

Background

As the size of semiconductor devices continues to shrink, various processing techniques (e.g., photolithography) are adjusted accordingly to produce devices having ever smaller dimensions. For example, as gate density increases, the processes used to fabricate various features in the device (e.g., overlying interconnect features) are also adaptively adjusted so that these processes are generally compatible with shrinking device features. However, as the process window for semiconductor manufacturing continues to shrink, the fabrication of such devices has approached and even exceeded the theoretical limit of optical etching equipment. As semiconductor devices continue to shrink, the required spacing (i.e., pitch) between elements of the devices is smaller than the pitch that can be fabricated using conventional optical masks and optical etching equipment.

Disclosure of Invention

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes depositing a first mask layer over a target layer and forming a four-layer photoresist over the first mask layer. In some embodiments, the method of fabricating a semiconductor device also includes transferring a notch pattern of a first photoresist layer of the four photoresist layers into a first intermediate layer of the four photoresist layers, and forming and transferring the notch pattern into an underlying layer of the four photoresist layers. In some embodiments, the method further includes transferring the notch pattern and the cut pattern of the underlying layer into the first mask layer, and transferring the notch pattern and the cut pattern of the underlying layer into the first mask layer. In some embodiments, the method of manufacturing a semiconductor device further includes etching the target layer using the notch pattern and the cut pattern of the first mask layer to form a plurality of contact openings in the target layer.

Some embodiments of the present disclosure also provide a method of manufacturing a semiconductor device. The method includes forming a series of notches in a first intermediate layer of a compound photoresist layer disposed over a semiconductor structure. In some embodiments, the method further includes forming a patterned etch mask including a plurality of photoresist truncation islands in the second layer of photoresist disposed over the series of notches in the first intermediate layer of the compound layer of photoresist, the photoresist truncation islands spanning and filling a portion of the series of one or more notches in the first intermediate layer. In some embodiments, the method also includes transferring the series of notches and the patterned etch mask to an underlying layer of the compound photoresist layer to form a cut mask. In some embodiments, the method further includes forming a plurality of contact openings through an interlayer dielectric layer disposed over the semiconductor structure using the cut-off mask, the contact openings exposing portions of source and drain regions of the device in the semiconductor structure.

Some embodiments of the present disclosure also provide a method of fabricating a contact plug for a finfet device, comprising depositing a hard mask layer over a semiconductor structure; and forming a four-layer photoresist layer above the hard mask layer. In some embodiments, the method further comprises etching a series of notches in a first intermediate layer of the four photoresist layers; and forming a patterned photoresist mask over the remaining portion of the first intermediate layer. In some embodiments, the method also includes transferring the patterned photoresist mask and the series of notches into an underlying layer of the four photoresist layers. In some embodiments, the method further includes using the patterned photoresist mask in the underlayer and the series of notches to form a kerf curtain layer in the hard mask layer. In some embodiments, the method further includes etching contact openings through an interlayer dielectric layer to surfaces of source and drain regions of the finfet devices in the semiconductor structure. In some embodiments, the method further includes depositing a conductive material in the contact openings to form contact plugs for the finfet devices.

Drawings

The contents of the embodiments of the present disclosure can be more understood through the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-9B illustrate schematic diagrams depicting intermediate stages in the formation of contact openings and corresponding contact plugs in a target layer structure during the fabrication of finfet devices according to some embodiments of the present disclosure. The drawings in which reference is made to "a" represent perspective views of various intermediate structures from an intermediate stage of forming contact openings, according to some embodiments of the present disclosure. The drawings in which the designation "B" represents a top view of such intermediate structures, in some embodiments according to the present disclosure.

FIGS. 1A-1B illustrate a first photoresist layer of a four layer photoresist being patterned, according to some embodiments.

Fig. 2A-2B illustrate a first patterning of a first intermediate layer of a four layer photoresist, according to some embodiments.

Fig. 3A-3B are schematic diagrams illustrating deposition and patterning of a second layer of four layers of photoresist, according to some embodiments.

FIGS. 4A-4B are schematic diagrams illustrating a second patterning of a first intermediate layer of a four-layer photoresist, according to some embodiments.

Fig. 5A-5B illustrate deposition and patterning of a second layer of photoresist over a second intermediate layer of four layers of photoresist, according to some embodiments.

FIGS. 6A-6D illustrate the transfer of the pattern of the second layer of photoresist to a bottom layer of four layers of photoresist and the patterning of a second intermediate layer and bottom layer of four layers of photoresist, according to some embodiments.

Fig. 7A-7B are schematic diagrams illustrating the transfer of the underlying pattern to a hard mask layer of a four-layer photoresist and the patterning of the hard mask layer, according to some embodiments.

FIGS. 8A-8B are schematic diagrams illustrating transferring a pattern of a hard mask layer to a target layer and patterning the target layer, according to some embodiments.

Fig. 9A-9B illustrate schematic diagrams of forming conductive plugs over source/drain regions of a patterned target layer, according to some embodiments.

[ notation ] to show

100-a first intermediate structure;

101-a semiconductor structure;

103-a substrate;

104-semiconductor fins;

105-drain region;

107 to a source region;

109-gate region;

111-inner dielectric layer;

113-an etch stop layer;

115-target layer;

117 hard mask layers;

121 to the first four layers of light resistance;

123-bottom layer;

125 to the second intermediate layer;

127 to a first intermediate layer;

129 to the first photoresist layer;

131-a first notch;

200-a second intermediate structure;

150. 250, 350, 450, 550, 650a, 650b, 750, 850, 950-top view;

300 to a third intermediate structure;

321 to a second four-layer photoresist;

329 to a second photoresist layer;

331-a second notch;

400 to a fourth intermediate structure;

500 to a fifth intermediate structure;

521-a third four-layer photoresist;

529 to a third photoresist layer;

535. 635a, 635 b-cutting the MD photoresist part;

600a, 600b to a sixth intermediate structure;

631. 633a, 633b, 731 to first openings;

633. 631a, 631b, 733 — second opening;

700 to seventh intermediate structures;

735. 835-cutting the MD transfer pattern;

831-first contact opening;

833 to a second contact opening;

800 to eighth intermediate structures;

931 to a first contact;

933 to a second contact;

th100, Th101, Th103, Th111, Th113, Th115, Th117, Th121, Th123, Th125, Th127, Th129, Th329, Th 529-thickness;

W1₁₃₁、W1₃₃₁、W1₅₃₅-a first width;

W2₁₃₁、W2₃₃₁、W2₅₃₅-a second width;

L1₅₃₅-a first length;

L2₅₃₅-a second length;

D1₁₃₁-a first distance;

D2₃₃₁-a second distance;

D3₃₃₁-a third distance;

D4₃₃₁a fourth distance.

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the embodiments of the disclosure. For example, references in the specification to a first feature being formed on or over a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves represent a particular relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "below …," "below …," "below," "above …," "above," and the like, may be used herein to describe one element or component as illustrated in relation to another element or component. Such spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be rotated to other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly to the rotated orientations.

According to some embodiments, a semiconductor device and a method of manufacturing a semiconductor device are provided. In some embodiments, a patterning process is performed to pattern openings in a target layer of a semiconductor device for forming conductive features. For example, openings may be formed through a patterning process that may be connected to contacts of a transistor device, such as openings for source/drain contacts or gate contacts. In one embodiment, the target layer may be a low-k dielectric layer (low-k dielectric layer) or an oxide layer, and a hard mask layer is used to form the opening. According to some embodiments, a pattern may be transferred to the hard mask layer using photolithography and a patterned four-layer photoresist design. Subsequently, the openings of the target layer may be filled with a conductive material to define conductive features, and the conductive features have cutouts defined by the second dielectric layer. Some of the conductive features may have a fine pitch (fine), or some of the cuts may have a fine pitch.

Fig. 1A-1B illustrate a schematic view of a first intermediate structure 100 produced by an intermediate step of a process of forming contacts to a semiconductor structure 101, according to some embodiments of the present disclosure.

In one embodiment, the semiconductor structure 101 may include a substrate 103 having semiconductor fins 104, source and drain

regions

105 and 107 formed in the substrate 103, and an interlayer dielectric 111 having a gate region 109 therein. In an embodiment, the source region 105, the drain region 107, and the gate region 109 may form a plurality of fin field effect transistors (finfets) in the semiconductor structure 101. The Semiconductor structure 101 may be made of a Semiconductor material such as silicon, doped or undoped, or an active layer of a Semiconductor-On-Insulator (SOI) substrate. The semiconductor structure 101 may comprise other semiconductor materials, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination of the foregoing. Other substrates, such as multilayer substrates or graded substrates, may also be used. In one embodiment, the substrate 103 may have a thickness Th103 ranging from about 100nm to about 200nm, for example about 150nm, and the interlayer dielectric layer 111 may be deposited to a total thickness Th111 ranging from about 10nm to about 50 nm. However, the substrate 103 and the interlayer dielectric layer 111 may have any suitable thickness. Accordingly, the total thickness Th101 of the semiconductor structure 101 may be in a range of about 110nm to about 250nm, for example, about 170 nm.

Fig. 1A further illustrates an etch stop layer 113 selectively disposed over the semiconductor structure 101, wherein the etch stop layer 113 physically contacts the semiconductor structure 101. In an embodiment, an etch stop layer 113 may be formed over the fin, the source region 105, the drain region 107, and the gate region 109 of one or more finfet devices in the semiconductor structure 101. In some embodiments, the etch stop layer 113 may be made of silicon nitride, SiON, Si_CON,SiC,SiOC,SiC_xN_y,SiO_xOther dielectrics, combinations of the foregoing, or the like, and may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Physical Vapor Deposition (PVD), or the like. However, the etch stop layer 113 may be formed using any suitable materials and processes. In one embodiment, the etch stopsLayer 113 may be deposited to a total thickness Th113 ranging between about 2nm to about 10nm, for example about 5 nm. However, the etch stop layer 113 may be formed to have any suitable thickness.

According to one embodiment, FIG. 1A further illustrates a target layer 115 disposed directly above the top of the etch stop layer 113. The etch stop layer 113 may serve as a stop layer for the etch process during a subsequent etch process for the target layer 115. Accordingly, the materials and processes used to form the etch stop layer 113 may be selected based on and in coordination with the materials selected to form the target layer 115. In some embodiments, target layer 115 is a dielectric layer, such as an inter-layer dielectric (ILD0) layer, and may be formed from an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boro-Phospho-Silicate Glass (BPSG), Undoped Silicate Glass (USG), Tetraethoxysilane (TEOS) oxide, or the like. Examples of the formation method include Chemical Vapor Deposition (CVD), Flow Chemical Vapor Deposition (FCVD), spin-on coating, and the like. However, any other suitable materials and processes may be used to form the target layer 115. In one embodiment, the target layer 115 may be deposited to a total thickness Th115 ranging between about 50nm to about 150nm, for example about 80 nm. However, the target layer 115 may be formed to have any suitable thickness.

Although fig. 1A shows the target layer 115 in physical contact with the etch stop layer 113, any number of intervening layers (interlayers) may be disposed between the target layer 115 and the etch stop layer 113. The intermediate layers may include other interlayer dielectric layers, and the intermediate layers may have contact plugs (conductive plugs), conductive lines, and/or vias therein, or may include one or more conditioning layers (e.g., etch stop layers, adhesion layers, etc.), combinations thereof, and the like.

A hard mask layer 117 may be formed over the target layer 115. The hard mask layer 117 may be made of a material comprising a metal (e.g., titanium nitride, titanium, tantalum nitride, tantalum, a metal-doped carbide (e.g., tungsten carbide), or the like) and/or a class of metals (e.g., silicon nitride, boron nitride, silicon carbide, or the like). In some embodiments, the hard mask layer 117 may have a higher etch selectivity than other material layers, such as the target layer 115, or than subsequently formed material layers, to determine the material composition of the hard mask layer 117. The hard mask layer 117 may be formed by, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like. However, any other suitable material and process may be used to form the hard mask layer 117. In some embodiments, the hard mask layer 117 may have a thickness Th117 in a range of about 20nm to about 50nm, although in other embodiments, the hard mask layer 117 may have other suitable thicknesses.

Fig. 1A further illustrates a first four-layer photoresist (first tetra-layer photoresist)121 formed over the hard mask layer 117. In one embodiment, the first four-layer photoresist 121 includes a plurality of mask layers, which may be sequentially deposited in a blanket fashion using, for example, spin-on coating. In other embodiments, one or more mask layers may be deposited using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like. However, any other suitable process and any suitable combination of processes may be used to deposit the mask layer of the first four layers of photoresist 121. In one embodiment, the first four-layer photoresist 121 may be deposited to a total thickness Th121 in a range of about 120nm to about 500nm, for example, about 210 nm. However, the first four-layer photoresist 121 may be formed to have any suitable thickness.

Referring again to fig. 1A, according to one embodiment, the first four-layer photoresist 121 may include a bottom layer 123 formed over the hard mask layer 117. In some embodiments, the bottom layer 123 may be made of a polymer. In one embodiment, the bottom layer 123 may be a bottom anti-reflective coating (BARC) layer. According to one embodiment, the bottom layer 123 may comprise, for example, C_xH_yO_zAnd is prepared by a spin coating process. However, any other suitable material and any suitable process may be used to form underlayer 123. In one embodiment, underlayer 123 can be deposited to about 50nm to about 20nmA total thickness Th123 in the range of 0nm, for example about 150 nm. However, the bottom layer 123 may be formed to have any suitable thickness.

The first four-layer photoresist 121 further includes a second intermediate layer 125 formed over the bottom layer 123. The second intermediate layer 125 may comprise a material such as Si_xH_yC_zO_wSilicon or metal oxide, and is formed using one or more deposition processes such as spin-on coating, chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable materials and processes may be used to form the second interlayer 125. In some embodiments, the material composition of the second intermediate layer 125 may be determined such that the second intermediate layer 125 has a higher etch selectivity than other material layers, such as the underlayer 123 and/or the hard mask layer 117, or other material layers that may provide an etch stop capability when patterning the second intermediate layer 125. The second intermediate layer 125 may comprise more than one layer of material and may comprise more than one material. In some embodiments, the second intermediate layer 125 may have a total thickness Th125 ranging between about 20nm to about 50nm, for example about 30 nm. However, the second intermediate layer 125 may be formed to have any suitable thickness.

The first four-layer photoresist 121 further includes a first interlayer 127 formed over the second interlayer 125. The first intermediate layer 127 may be formed using one or more deposition processes, such as spin-on coating, chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable materials and processes may be used to form the first intermediate layer 127. In some embodiments, the material composition of the first intermediate layer 127 may be determined such that the first intermediate layer 127 has a higher etch selectivity than other material layers, such as the bottom layer 123, the second intermediate layer 125, or other material layers that may provide an etch stop capability when patterning the first intermediate layer 127. The first interlayer 127 may comprise an inorganic material, which may be a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), or the like. However, the first intermediate layer 127 may be formed using any other suitable material and any suitable process. Further, the first intermediate layer 127 may comprise more than one layer of material, and may comprise more than one material. In some embodiments, the first intermediate layer 127 has a total thickness Th127 in a range between about 20nm to about 50nm, for example about 30 nm. However, the first intermediate layer 127 may be formed to have any suitable thickness.

The first four-layer photoresist 121 further includes a first photoresist layer 129 formed over the first intermediate layer 127. The first photoresist layer 129 may be made of photoresist (e.g., a photosensitive material), which may include organic materials, and may be a positive photosensitive material (positive photosensitive material) or a negative photosensitive material (negative photosensitive material). The first photoresist layer 129 may be formed by one or more deposition processes, such as spin-on coating, chemical vapor deposition, atomic layer deposition, or the like. In some embodiments, the first photoresist layer 129 has a total thickness Th129 in a range of about 30nm to about 200nm, for example about 100 nm. However, the first photoresist layer 129 may be formed to have any suitable thickness. Thus, according to some embodiments, the first intermediate structure 100 may have a thickness Th100 in a range between about 312nm to about 1460nm, for example about 615 nm. However, the first intermediate structure 100 may be formed to have any suitable thickness.

Fig. 1A-1B further illustrate the patterned first photoresist layer 129 (e.g., using a photolithography mask and etch process). After deposition, the first photoresist layer 129 may be patterned to form a plurality of first slots (first trenches) 131 in the first photoresist layer 129. In one embodiment, the first trench 131 in the first photoresist layer 129 may have a first width W1 in a range of about 40nm to about 60nm₁₃₁For example about 45 nm. However, the first notch 131 may have any suitable width. In some embodiments, the first notches 131 in the first photoresist layer 129 may have different widths W1₁₃₁. In some embodiments, a single first notch 131 may have more than one width.

As shown in the top view 150 of the first intermediate structure 100 of fig. 1B, a series of first notches 131 expose a surface area of the first intermediate layer 127 through the patterned first photoresist layer 129. Therefore, the remaining portion of the first photoresist layer 129 can be used as a mask layer above the first intermediate layer 127.

FIGS. 2A-2B illustrate a first etch process for transferring the pattern of the first photoresist layer 129 to the first intermediate layer 127 as shown in FIG. 1A. The first intermediate layer 127 has a high etch selectivity compared to the first photoresist layer 129 and the second intermediate layer 125. In one embodiment, the first photoresist layer 129 acts as an etch mask for the first pattern of the first intermediate layer 127. The etching process may be anisotropic such that the first notch 131 in the first photoresist layer 129 may extend through the first intermediate layer 127. The etching method for patterning the first interlayer 127 may be selected from Reactive Ion Etching (RIE) which may be performed using Inductively Coupled Plasma (ICP), Capacitively Coupled Plasma (CCP), or the like. The process gases may include one or more etching gases and one or more polymer-forming gases. According to some embodiments, the etching gas may comprise a fluorine-containing gas, such as CF₄、NF₃Or a combination of the foregoing. The polymer-forming gas may comprise CHF₃,CH₂F₂,CH₃F,C₄F₆,C₄F₈Or a combination of the foregoing. The pressure of the process gas may be in the range of 5mTorr to 200 mTorr. The temperature of the wafer may range between about 0 ℃ and about 50 ℃. According to an embodiment, the first notch 131 in the first intermediate layer 127 may have a second width W2₁₃₁. In one embodiment, the first notch 131 in the first intermediate layer 127 may have substantially the same (or slightly smaller) size as the first notch in the first photoresist layer 129. In other embodiments, second width W2 in first intermediate layer 127 is reduced, for example, due to a reduction in critical dimension (critical dimension)₁₃₁May be different from the first width W1 in the first photoresist layer 129₁₃₁. According to one embodiment, the second width W2 of the first notch 131 in the first intermediate layer 127₁₃₁And may range between about 6nm and 12nm, such as about 9 nm. However, the first notch 131 may have any shapeAnd any suitable width. As shown in the top view 250 of the second intermediate structure 200 of fig. 2B, a series of first notches 131 expose a surface area of the second intermediate layer 125 through the portion of the first intermediate layer 127 that remains.

When the pattern of the first photoresist layer 129 is transferred to the first intermediate layer 127, the size and characteristics of the first notches 131 in the first photoresist layer 129 are also transferred to the size and characteristics of the first notches 131 in the first intermediate layer 127. Thus, in some embodiments, the second width W2 of the first notch 131 in the first intermediate layer 127 depends on the size and characteristics of the first notch 131 in the first photoresist layer 129₁₃₁May not be identical to each other. In some embodiments, a single first notch 131 in the first intermediate layer 127 may have more than one width. When the first recesses 131 have been formed in the first intermediate layer 127, any remaining portions of the first photoresist layer 129 may be removed to expose remaining portions of the first intermediate layer 127.

Fig. 3A-3B illustrate depositing a second photoresist layer 329 over the patterned first intermediate layer 127 and filling the first recesses 131, the second photoresist layer 329 being over portions of the second intermediate layer 125 exposed between the first recesses 131 in the first intermediate layer 127. Therefore, the bottom layer 123, the second intermediate layer 125, the first intermediate layer 127 and the second photoresist layer 329 are collectively referred to as a second four-layer photoresist 321. In some embodiments, the materials and processes used to deposit the second photoresist layer 329 may be the same as those used to deposit the first photoresist layer 129 and form the first notches 131 described above. For example, a spin-on process or the like may be used to deposit a photosensitive material as the second photoresist layer 329 over the patterned first intermediate layer 127. However, any other suitable material and any suitable process may be used to deposit the second photoresist layer 329.

In some embodiments, the second photoresist layer 329 may have the same thickness as the first photoresist layer 129. In other embodiments, the second photoresist layer 329 may have a different thickness than the first photoresist layer 129. In one embodiment, the second photoresist layer 329 has a total thickness Th329 in a range of about 50nm to about 200nm, for example about 100 nm. However, the second photoresist layer 329 may be formed to have any suitable thickness.

Fig. 3A-3B further illustrate the patterned second photoresist layer 329. In one embodiment, the patterned second photoresist layer 329 with second notches (second openings)331 is offset from and overlaps the patterned first photoresist layer 129. In some embodiments, the process used to form the second notches 331 in the second photoresist layer 329 may be the same as the process used to form the first notches 131 in the first photoresist layer 129, as described above. For example, a photolithography process may be used to form the second notches 331 in the second photoresist layer 329. However, any other suitable material and any suitable process may be used to form the second notches 331 in the second photoresist layer 329. Thus, the second notch 331 in the second photoresist layer 329 exposes the second surface of the first intermediate layer 127 through the patterned second photoresist layer 329. As shown in the top view 350 of the third intermediate structure 300, a series of second notches 331 expose the second surface of the first intermediate layer 127 through the patterned second photoresist layer 329.

In some embodiments, the second notches 331 of the second photoresist layer 329 may have the same width as the first notches 131 of the first photoresist layer 129. In other embodiments, the second notches 331 of the second photoresist layer 329 may have a different width than the first notches 131 of the first photoresist layer 129. In one embodiment, the second trench 331 of the second photoresist layer 329 has a first width W1 of about 40nm to about 60nm₃₃₁For example about 45 nm. However, the second notches 331 of the second photoresist layer 329 may have any suitable width.

FIGS. 4A-4B illustrate the second etch process transferring the pattern of the second layer of photoresist 329 to the remaining first intermediate layer 127. The first intermediate layer 127 has a high etch selectivity compared to the second photoresist layer 329 and the second intermediate layer 125. In one embodiment, the second photoresist layer 329 serves as an etch mask for the second pattern that remains part of the first intermediate layer 127. In some embodiments, the second etch process may be the same as the first etch process used to transfer the pattern of the first photoresist layer 129 to the first intermediate layer 127. In some embodiments, the second etching process may be an anisotropic etching process such thatThe second notch 331 in the second photoresist layer 329 may extend through the first intermediate layer 127. However, any suitable etching process may be used as the second etching process. According to an embodiment, the second notch 331 in the first intermediate layer 127 may have a second width W2₃₃₁Approximately equal to the second width W2 of the first notch 131 in the first intermediate layer 127₁₃₁The same size. In other embodiments, the second width W2 of the second notch 331 in the first intermediate layer 127₃₃₁And may be equal to the second width W2 of the first notch 131 in the first intermediate layer 127₁₃₁Are different in size.

When the pattern of the second photoresist layer 329 is transferred to the remaining portion of the first intermediate layer 127, the size and characteristics of the second notches 331 in the second photoresist layer 329 are also transferred to the size and characteristics of the second notches 331 in the first intermediate layer 127. Thus, in some embodiments, the second notches 331 in the first intermediate layer 127 may have the same second width W2 depending on the size and characteristics of the second notches 331 in the second photoresist layer 329₂₃₁. In other embodiments, the second width W2 of the second notch 331 in the first intermediate layer 127₂₃₁May not be identical to each other. According to some embodiments, a single second notch 331 in the first intermediate layer 127 may have more than one width.

In one embodiment, the second notch 331 may have substantially the same (or slightly smaller) size as the first notch of the remaining portion of the first intermediate layer 127, as the size of the second notch 331 formed in the second photoresist layer 329. In other embodiments, the second width W2 is reduced, for example, due to a reduction in critical dimension (critical dimension)₂₃₁May be different from the first width W1₁₃₁. In the remaining portion of the first intermediate layer 127, the second width W2 of the second notch 331 is according to an embodiment₂₃₁And may range between about 6nm and 12nm, such as about 9 nm. However, the second notch 331 may have any suitable width.

As shown in the top view 450 of the fourth intermediate structure 400 of fig. 4B, with the portion of the first intermediate layer 127 still remaining, a series of second notches 331 pass through the remaining portion of the first intermediate layer 127 to expose the second surface of the second intermediate layer 125, wherein the exposed second surface of the second intermediate layer 125 is juxtaposed with the exposed first surface of the second intermediate layer 125. In one embodiment, the patterned second photoresist layer 329 with the second notches 331 may be offset overlapped with the patterned first photoresist layer 129. Between the portions of the first intermediate layer 127 that remain, the exposed first surfaces of the second intermediate layers 125 are alternated with the exposed second surfaces of a series of second intermediate layers 125. The remaining portion of the first intermediate layer 127 may be patterned and used as a mask layer (e.g., a first notch pattern) to pattern the second intermediate layer 125.

Fig. 5A-5B illustrate the deposition of a third photoresist layer 529 over the patterned first intermediate layer 127 and filling the first and second exposed portions of the second intermediate layer 125 between the first and

second notches

131 and 331 in the first intermediate layer 127. Therefore, the bottom layer 123, the second intermediate layer 125, the first intermediate layer 127, and the third photoresist layer 529 are collectively referred to as a third four-layer photoresist (third four-layer photoresist) 521. In some embodiments, the materials and processes used to deposit the third photoresist layer 529 may be the same as those used to deposit the first photoresist layer 129 described above. For example, a spin-on process or the like may be used to deposit a photosensitive material as the third photoresist layer 529 over the patterned first intermediate layer 127. However, any other suitable material and any suitable process may be used to deposit the third photoresist layer 529.

In some embodiments, the third photoresist layer 529 may have the same thickness as the first photoresist layer 129. In other embodiments, the third photoresist layer 529 may have a different thickness than the first photoresist layer 129. In one embodiment, the third photoresist layer 529 has a total thickness Th529 in a range of about 30nm to about 100nm, for example, about 50 nm. However, third photoresist layer 529 may be formed to have any suitable thickness.

Fig. 5A-5B further illustrate the patterned third photoresist layer 529, which forms a cut mask over the patterned first intermediate layer 127. The area marked with a dashed rectangle in fig. 5B is a representation of a portion corresponding to the top view 550 of the fifth intermediate structure 500 shown in fig. 5A. Any suitable photolithography process may be performed to pattern the third photoresist layer 529. For example, the patterning of the third photoresist layer 529 may be similar to the patterning of the first four photoresist layers 121 or the second four photoresist layers 321.

In some embodiments, between the portions left adjacent the first intermediate layer 127, a plurality of truncated metal-to-source/drain (MD) photoresist portions 535 (e.g., photoresist truncated islands) may extend across and fill a portion of one or more of the series of first notches 131 and the series of second notches 331. Accordingly, the truncated MD light blocking portion 535 fills the partial first notch 131 in the first intermediate layer 127 and the partial second notch 331 in the first intermediate layer 127. Although only two truncated MD resist portions 535 are shown in fig. 5A, a plurality of truncated MD resist portions 535 (i.e., a truncated pattern) may be disposed in a plurality of regions along the surface of the remaining portion of the first intermediate layer 127, as shown in the top view 550 of the fifth intermediate structure 500 in fig. 5B.

In some embodiments, the truncated MD photo-resist portions 535 may have the same length and the same width. In other embodiments, the truncated MD resist portions 535 may have different lengths and different widths. In some embodiments, the first set of truncated MD light blocking portions 535 may have a first length L1₅₃₅And a first width W1₅₃₅And the second set of truncated MD photoresist portions 535 may have a second length L2₅₃₅And a second width W2₅₃₅. In one embodiment, the first length L1₅₃₅May be between about 40nm and about 70nm, such as about 50nm, and a first width W1₅₃₅And may be between about 25nm and about 40nm, such as about 30 nm. In one embodiment, the second length L2₅₃₅May be between about 120nm and about 200nm, such as about 150nm, and a second width W2₅₃₅And may be between about 30nm and about 50nm, for example about 40 nm. However, the formed truncated MD photoresist portions 535 may have any suitable length and width.

Furthermore, although the truncated MD light blocking portions 535 shown in fig. 5A cover only an area of a portion of one of the first notches 131, each of the truncated MD light blocking portions 535 may cover an area beyond a portion of the first notch 131, a portion of the second notch 331, or a combination thereof, as shown in the top view 550 of the fifth intermediate structure 500 in fig. 5B. However, the plurality of truncated MD photoresist portions 535 (i.e., the truncated pattern) may cover any portion of the first notch 131 in the first intermediate layer 127 and any portion of the second notch 331 in the first intermediate layer 127, which is suitable for transferring the truncated pattern to the bottom layer 123, in compliance with process requirements.

In some embodiments, the first set of truncated MD light blocking portions 535 may be the same first distance D1 along the first slot 131₁₃₁Spaced apart from each other. In one embodiment, the same first distance D1 along the first notch 131₁₃₁And may be between about 80nm and about 120nm, such as about 90 nm. In some embodiments, the second set of truncated MD photo-resist portions 535 may be spaced apart from each other at different distances along the second slot 331. For example, the second set of truncated MD photoresist portions 535 may be a second distance D2 along the second notch 331₃₃₁A third distance D3₃₃₁And a fourth distance D4₃₃₁Spaced apart. In some embodiments, the second distance D2 between the truncated MD photoresist portions 535 along the second notch 331₃₃₁And may be between about 90nm and about 150nm, such as about 120 nm. Third distance D3 between truncated MD light blocking portions 535 along second notch 331₃₃₁And may be between about 60nm and about 100nm, for example about 70 nm. Fourth distance D4 between truncated MD light blocking portions 535 along second notch 331₃₃₁And may be between about 30nm and about 60nm, for example about 40 nm.

Fig. 6A-6B illustrate the pattern of the remaining portions of the first intermediate layer 127 and the portions of the plurality of truncated MD resist portions 535 transferred to the second intermediate layer 125 in a third etch process. In one embodiment of the third etching process, the second intermediate layer 125 has a high etching selectivity compared to the first intermediate layer 127, the cut mask made of the third photoresist layer 529, and the bottom layer 123. In one embodiment, the pattern of the first intermediate layer 127 and the cut mask made of the third photoresist layer 529 are used as an etching mask to pattern the second intermediate layer 125 in an initial etching step of the third etching process. After second intermediate layer 125 is patterned, the remaining portions of third photoresist layer 529 cut through mask 535 and the remaining portions of first intermediate layer 127, as shown in fig. 5A-5B, may be removed to form sixth intermediate structure 600a, as shown in fig. 6A.

Fig. 6A-6B further illustrate second intermediate layer 125 patterned to form a cut mask over underlayer 123. The area marked with a dashed rectangle in fig. 6B is a representation of a portion corresponding to the top view 650a of the sixth intermediate structure 600a shown in fig. 6A. The exposed portions of the bottom layer 123 are present within the first and

second openings

633a, 631a disposed between the portions left by the second intermediate layer 125, and are not covered by the plurality of truncated MD resist portions 635a at the second intermediate layer 125. The corresponding portions of the second intermediate layer 125 may be removed by one or more etching processes using any suitable optical etching process or processes.

According to some embodiments, the etch process used to pattern the second intermediate layer 125 may be an anisotropic etch process such that the first notch 131 and the second notch 331 between the remaining portions of the first intermediate layer 127 may extend through the second intermediate layer 125. As such, the first opening 633a and the second opening 631a are formed between the portions left by the second intermediate layer 125, and the portions left by the second intermediate layer 125 are integrated with the cut MD resist portions 635a located within the portions left by the second intermediate layer 125. Thus, the first and

second openings

633a, 631a of the second intermediate layer 125 may have substantially the same (or slightly smaller) dimensions as the first and second notches in the first intermediate layer 127. The resulting intermediate structure 600a is shown in fig. 6A, 6B, and the intermediate structure 600a with the truncated MD photoresist portion 635a shown in fig. 6A has a contrasting pattern to the portion of the second intermediate layer 125 left between the first opening 633a and the second opening 631 a. The contrasting pattern of the truncated MD light-blocking portion 635a is merely to aid in the visual perception of the pattern formed in the second intermediate layer 125.

In some embodiments, the etching process used to pattern the second intermediate layer 125 may include opposing the second intermediate layer 125 to the first intermediate layerA dry etching process with high etch selectivity can be performed on the middle layer 127, the truncated MD photoresist portions 535, and the bottom layer 123. For example, the etch process may comprise a plasma etch process. In some embodiments, the plasma etch process may comprise an Inductively Coupled Plasma (ICP) generated with a power between about 100Watts and about 800Watts, and may be performed at a pressure in a range between 10mTorr and 100 mTorr. In some embodiments, the plasma etch process may use Cl₂HBr, a fluorine-containing process gas such as CF₄,CH₂F₂,CHF₃Or other types of process gases. In some embodiments, the etching method may be selected from a Reactive Ion Etching (RIE) process (e.g., ICP or CCP), or the like. The process gases may include one or more etching gases and one or more polymer-forming gases. According to some embodiments, for example, when the second interlayer 125 comprises silicon oxide, the etching gas may comprise a fluorine-containing gas, such as CF₄、NF₃Or a combination of the foregoing. The polymer-forming gas may comprise CHF₃,CH₂F₂,CH₃F,C₄F₆,C₄F₈Or a combination of the foregoing. The pressure of the process gas may be in the range of 5mTorr to 200 mTorr. During the etching of the second interlayer 125, the temperature of the intermediate structure 500 may range between about 0 ℃ and about 50 ℃. However, other embodiments may use any other suitable process gas or etch process. In some instances, during etching of second interlayer 125, truncated MD photoresist portions 535 and first interlayer 127 may be consumed. When the pattern of first and

second notches

131 and 331 and the truncated MD light-blocking portions 535 have been transferred to the second intermediate layer 125, any remaining portions of the truncated MD light-blocking portions 535 and remaining portions of the first intermediate layer 127 may be removed to expose remaining portions of the second intermediate layer 125 and the truncated MD light-blocking portions 635 a. After the patterning is completed, the second intermediate layer 125 may be used as an etching mask (e.g., a cut-off mask) in an etching step of a subsequent third etching process to transfer the pattern of the second intermediate layer 125 to the bottom layer 123.

Fig. 6C-6D illustrate the transfer of the pattern formed in the second intermediate layer 125 to the corresponding portion of the bottom layer 123 in the etching step of the subsequent third etching process. In one embodiment of the subsequent step of the third etching process, the bottom layer 123 has a high etching selectivity compared to the second intermediate layer 125 and the hard mask layer 117. In one embodiment, the pattern of the second middle layer 125 is used as an etch mask for patterning the bottom layer 123 in the subsequent etching step of the third etching process. After the bottom layer 123 is patterned, the remaining portion of the second intermediate layer 125 shown in fig. 6A and 6B may be removed to form an intermediate structure 600B shown in fig. 6C.

Fig. 6C-6D further illustrate the patterning of the underlayer 123 to form a cut mask over the hard mask layer 117. The area marked with a dashed rectangle in fig. 6D is a representation of a portion corresponding to the top view 650b of the intermediate structure 600b shown in fig. 6C. The exposed portions of the bottom layer 123, which are located within the first and

second openings

633a, 631a between the remaining portions of the second intermediate layer 125 not covered by the truncated MD photoresist portion 635a, may be removed using one or more etching processes, wherein the truncated MD photoresist portion 635a is integral with the remaining portions of the second intermediate layer 125. The pattern of underlayer 123 may be formed by any suitable photolithography process.

According to some embodiments, the etching process for patterning the bottom layer 123 may be an anisotropic etching process, such that the first opening 633a and the second opening 631a between the remaining portions of the second intermediate layer 125 may extend through the bottom layer 123. In this manner, the first opening 633b and the second opening 63b are formed between the remaining portions of the bottom layer 123, and the remaining portions of the bottom layer 123 are integrated with the cut MD pattern transfers 635b formed in the bottom layer 123. Accordingly, the first and

second openings

633b, 631b in the bottom layer 123 may have substantially the same (or slightly smaller) dimensions as the first and second openings in the second intermediate layer 125. The resulting intermediate structure 600b is shown in fig. 6C, 6D, and the intermediate structure 600b with the truncated MD transfer pattern 635b shown in fig. 6C has a contrasting pattern to the portions of the bottom layer 123 left between the first opening 633b and the second opening 631 b. The contrasting pattern of this truncated MD transfer pattern 635b is merely to aid in the visual perception of the pattern formed in the bottom layer 123.

In some embodiments, the etching process used to pattern the bottom layer 123 may include a dry etching process that may have a high etch selectivity for the bottom layer 123 relative to the second intermediate layer 125 and the hard mask layer 117. For example, the etch process may comprise a plasma etch process. In some embodiments, the plasma etch process may comprise an Inductively Coupled Plasma (ICP) generated with a power between about 100Watts and about 800Watts, and may be performed at a pressure in a range between 10mTorr and 100 mTorr. In some embodiments, the plasma etch process may use Cl₂HBr, a fluorine-containing process gas such as CF₄,CH₂F₂,CHF₃Or other types of process gases. In some embodiments, the etching method may be selected from a Reactive Ion Etching (RIE) process (e.g., ICP or CCP), or the like. The process gases may include one or more etching gases and one or more polymer-forming gases. According to some embodiments, for example, when the bottom layer 123 comprises silicon oxide, the etching gas may comprise a fluorine-containing gas, such as CF₄、NF₃Or a combination of the foregoing. The polymer-forming gas may comprise CHF₃、CH₂F₂、CH₃F、C₄F₆、C₄F₈Or a combination of the foregoing. The pressure of the process gas may be in the range of 5mTorr to 200 mTorr. During the etching of the second interlayer 125, the temperature of the intermediate structure 600a may range between about 0 ℃ and about 50 ℃. However, other embodiments may use any other suitable process gas or etch process. In some examples, the second interlayer 125 may be consumed during the etching step of the third etching process. When the first opening 633b and the second opening 631b of the bottom layer 123 have been formed, the remaining portion of the second intermediate layer 125 may be removed, exposing the remaining portion of the bottom layer 123 and the truncated MD transfer pattern 635b of the bottom layer 123.

Although the embodiments discussed and illustrated herein relate to the third etching process for patterning the second intermediate layer 125 and the bottom layer 123 by performing the etching steps separately, these embodiments are not intended to be limiting. Other embodiments of the third etch process may include patterning the second intermediate layer 125 and the bottom layer 123 together in a single etch step. For example, in the third etching process, the second intermediate layer 125 and the bottom layer 123 have high etching selectivity compared to the first intermediate layer 127, the truncated MD resist portions 535, and the hard mask layer 117. As such, the hard mask layer 117 may act as a stop layer when etching the second intermediate layer 125 and the bottom layer 123 and transferring the pattern of the first intermediate layer 127 and the truncated MD photoresist portions 535 to the second intermediate layer 125 and the bottom layer 123 in a single etching step. In some embodiments, the first intermediate layer 127 and the truncated MD photoresist portions 535 may be consumed in a single etching step. After the bottom layer 123 is patterned, the patterned second intermediate layer 125 may be removed to expose the remaining portion of the patterned bottom layer 123. Thus, the patterned underlayer 123 can act as a mask for transferring the pattern of the underlayer 123 to the hard mask layer 117. All of these embodiments are within the scope of the present disclosure.

Fig. 7A-7B illustrate the transfer of the first opening 631, the second opening 633, and the truncated MD transfer pattern 635 in the bottom layer 123 to the hardmask layer 117 to form a first opening 731, a second opening 733, and a truncated MD transfer pattern 735 in the hardmask layer 117. Fig. 7A-7B further illustrate the patterning of the hard mask layer 117 to form a cut mask over the target layer 115. The area marked with a dashed rectangle in fig. 7B represents a portion corresponding to the top view 750 of the seventh intermediate structure 700 shown in fig. 7A.

As shown in fig. 7A, a fourth etch process may be performed to transfer the pattern of the bottom layer 123 into the hard mask layer 117, thereby extending the first and second openings 631 and 633 through the hard mask layer 117. The fourth etch process of the hard mask layer 117 may be anisotropic such that the first opening 631 and the second opening 633 in the bottom layer 123 extend through the hard mask layer 117. As such, first and

second openings

731, 733 are formed between the remaining portions of underlayer 123, and the remaining portions of underlayer 123 are integral with truncated MD transfer pattern 735 within hardmask layer 117. Accordingly, the first opening 731 and the second opening 733 of the hard mask layer 117 may have substantially the same (or slightly smaller) size as the first opening 631 and the second opening 633 in the bottom layer 123. The seventh intermediate structure 700 is formed as shown in fig. 7A, 7B, and the seventh intermediate structure 700 with the truncated MD transfer pattern 735 as shown in fig. 7A has a contrasting pattern to the pattern between the first opening 731 and the second opening 733 between the portions left by the hardmask layer 117. The contrasting pattern of this truncated MD transfer pattern 735 is merely to aid in the visual perception of the pattern formed in the hardmask layer 117.

During etching of the hard mask layer 117, the underlayer 123 may be consumed. In some embodiments, when the patterned bottom layer 123 is not completely consumed during the etching of the hard mask layer 117, an ashing process may be performed to remove residues left by the bottom layer 123. When the bottom layer 123 is removed, portions of the hard mask layer 117 previously covered by the bottom layer 123 may be exposed. The hard mask layer 117 may then be used as an etch mask for etching the target layer 115, such that the pattern of the hard mask layer 117 is transferred to the target layer 115.

As shown in fig. 7B, the regions of the target layer 115 exposed through the first opening 731 and the second opening 733 of the hard mask layer 117 may define regions where contacts are formed in the target layer 115. The exposed portions of the hard mask layer 117 may define the location of the cuts between contacts subsequently formed in the target layer 115. After patterning, the remaining portion of the hard mask layer 117 may serve as an etch mask for the underlying target layer 115 to the source region 105 and to the drain region 107 of the semiconductor structure 101 to form contact openings (contacts openings). In this manner, the first opening 731, the second opening 733, and the truncated MD transfer pattern 735 of the etch mask formed in the hard mask layer 117 may be transferred into the target layer 115 and into the semiconductor structure 101 to form contact openings.

Fig. 8A-8B illustrate a fifth etch process using the patterned hardmask layer 117 as an etch mask to transfer the first opening 731, the second opening 733, and the truncated MD transfer pattern 735 in the hardmask layer 117 into the target layer 115, the etch stop layer 113, and the ild layer 111, according to some embodiments. Fig. 8A-8B further illustrate the patterning of the target layer 115, the etch stop layer 113, and the interlayer dielectric layer 111 to form a first contact opening 831 and a second contact opening 833 over the source/drain regions of the semiconductor structure 101.

Although the embodiment discussed and illustrated herein is directed to a single etching step associated with the fifth etching process for patterning the target layer 115, the etch stop layer 113 and the ild layer 111, these embodiments are not intended to be limiting. Other embodiments of the fifth etch process may include patterning the target layer 115, the etch stop layer 113, and the ild layer 111 with separate etch steps. All such embodiments are intended to be within the scope of the embodiments of the present disclosure.

A fifth etch process may be used to form the first and

second contact openings

831 and 833. in some embodiments, the fifth etch process may be a dry etch process using a process including CF₄、SO₂HBr, Cl and O₂Or a mixture containing HBr and Cl₂、O₂And CF₂Mixtures of (a) and the like. In other embodiments, the fifth etching process for forming the first contact opening 831 and the second contact opening 833 may be a wet etching process using an etching solution such as potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), acetic acid (CH)₃COOH), ammonium hydroxide (NH)₄OH), hydrogen peroxide (H)₂O₂) Isopropyl alcohol (Isopropanol; IPA), or a solution containing hydrogen fluoride, nitric acid, and water. However, any suitable etching technique and any suitable etching solution, or a combination of the foregoing, may be used to form the first and

second contact openings

831 and 833.

When the first and

second contact openings

831 and 833 have been formed, the remaining portions of the hard mask layer 117 may be removed. The mask formed by the hard mask layer 117 may be removed isotropically or anisotropically, and may be removed by a wet etching process or a dry etching process. However, any suitable etch process may be used to remove the remaining portions of the hard mask layer 117.

As shown in fig. 8A, a fifth etching process is performed to transfer the pattern of the hard mask layer 117 into the target layer 115, the etch stop layer 113, and the ild layer 111, thereby extending the first opening 731 and the second opening 733 of the hard mask layer 117 through the target layer 115, the etch stop layer 113, and the ild layer 111. In this manner, the first contact opening 831 and the second contact opening 833 are formed between the target layer 115, the etch stop layer 113, and the portion of the interlayer dielectric layer 111 left, and the target layer 115, the etch stop layer 113, and the portion of the interlayer dielectric layer 111 left are integrated with the truncated MD transfer pattern 835 in the target layer 115, the etch stop layer 113, and the interlayer dielectric layer 111. The eighth intermediate structure 800 is formed as shown in fig. 8A, 8B, and the truncated MD transfer pattern 835 shown in fig. 8A is a contrast pattern having a contrast with the target layer 115, the etch stop layer 113, and the remaining portion of the interlayer dielectric layer 111 between the first opening 731 and the second opening 733. The contrasting pattern of this truncated MD transfer pattern 835 is merely to aid in the visual perception of the pattern formed in the target layer 115, etch stop layer 113, and interlevel dielectric layer 111.

As shown in fig. 8A, the first contact opening 831 and the second contact opening 833 are etched to the source region 105 and the drain region 107 to form source/drain contact openings of the semiconductor structure 101. The area marked with a dashed rectangle in fig. 8B is a representation of a portion corresponding to the top view 850 of the eighth intermediate structure 800 shown in fig. 8A. In one embodiment, the first contact opening 831 is formed above the drain region 107, and the second contact opening 833 is formed above the source region 105.

For example, the first and

second contact openings

831 and 833 in the target layer 115 may expose source/drain regions of the finfet device to form source/drain contacts of the finfet device and/or expose a gate of the finfet device to form gate contacts of the finfet device. The etching process for the target layer 115, the etch stop layer 113 and the interlayer dielectric 111 may include an anisotropic dry etching process and/or a wet etching process. The remaining portions of the target layer 115, etch stop layer 113, and interlevel dielectric layer 111 as shown in figures 8A, 8B may have substantially the same (or slightly smaller) pattern as the hard mask layer 117 as shown in figures 7A, 7B. Thus, the target layer 115, the etch stop layer 113, and the interlayer dielectric layer 111 may be patterned in a single patterning step. After the target layer 115, the etch stop layer 113, and the ild layer 111 are patterned to form the first and

second contact openings

831 and 833, a wet clean process may be performed to remove any remaining portions of the hardmask layer 117.

Referring to fig. 9A-9B, a first contact 931 is formed in the first contact opening 831 over the drain region 107 of the patterning target layer 115, and a second contact 933 is formed in the second contact opening 833 over the patterning target layer 115, the patterned etch stop layer 113, and the source region 105 of the patterned interlayer dielectric layer 111. In one embodiment, one or more liners may be formed along the sidewalls and bottom surfaces of the first contact opening 831 and the second contact opening 833 of the target layer 115, and a conductive material may be formed over the target layer 115. In some embodiments, prior to forming the liner, metal silicide regions 833 may be formed in the source/drain regions exposed by the first and

second contact openings

831 and 833. The conductive material may be deposited over the liner layer first and may overflow the first and

second contact openings

831 and 833 of the target layer 115. The liner may comprise TiO, TiN, TaO, TaN, or the like, and may provide a diffusion barrier layer, adhesion layer, and/or seed layer for the contact. The liner may be deposited by any suitable process, such as physical vapor deposition chemical vapor deposition, atomic layer deposition, or the like. The conductive material may be any suitable conductive material, such as copper, tungsten, or other conductive material, and may be deposited, for example, by physical vapor deposition, electroplating, or the like.

In one embodiment, the slot MD patterning (slot MD patterning) and cut MD patterning (cut MD patterning) performed on the first intermediate layer 127, the second intermediate layer 125, and the bottom layer 123 transferred to the first four-layer photoresist 121, as shown in fig. 1A-6B, may be a "cut last" patterning process performed on the first four-layer photoresist 121. As such, the first and

second notches

131 and 127 in the first intermediate layer 127 of the first four-layer photoresist 121 may have a low degree of Line Width Roughness (LWR) and may have a notch profile with little or no twisting (e.g., MD groove twisting), as shown in the reference figures of fig. 2A-4B above. Due to the low degree of line width roughness and the little or no distorted notch profile, the notch MD pattern and the truncated MD pattern with well-defined profiles are transferred into the bottom layer 123 of the first four-layer photoresist 121, the hard mask layer 117, and the final target layer 105, as shown in the above reference figures of fig. 5A-8B, which reduces the risk of forming metal-to-source/drain and metal gate (MD-to-MG) bridges between contacts.

In some embodiments, the patterning methods described herein may be used to form first and

second contact openings

831 and 833 that provide conductive features, such as first and second contacts 931 and 933 (e.g., contact plugs) formed in the target layer 105. As described herein, one mask may be used to define the areas where contacts are formed, and then another mask may be used to define the areas where contacts are formed. Since the patterning of the scribe area is performed after the patterning of the contact area, the patterning method described herein can be considered as a "kerf post process". This is in contrast to a "cut first" process, in which the patterning of the cut regions is performed prior to the patterning of the contact regions. In some examples, a plurality of contacts having one or more cutouts with the same or substantially the same size may be formed, which may allow for better control of the electrical resistance of the contacts.

In some examples, etching the target layer 115 using the first four-layer photoresist 121 may enhance the definition of a pattern having a fine pitch in the target layer 115. In some embodiments, the second notch pattern of the second photoresist layer 329 in the first four-layer photoresist 121 may be used to transfer the second notch pattern to the first intermediate layer 127 in the first four-layer photoresist 121 in a "post-notching" process. Thus, the second notches 331 in the first intermediate layer 127 formed in the first four-layer photoresist 121 may have a low degree of line width roughness and may have a notch profile with little or no distortion (e.g., MD groove distortion), as shown in fig. 5A-8B. This reduces the risk of forming MD-to-MG bridges between contacts due to the low degree of line width roughness and little or no distortion of the notch profile. Furthermore, the "post-cut" and four-layer photoresist designs may be used with other cut designs, such as oxide cuts (cut OD), polysilicon cuts (cut POLY), and metal cuts.

In one embodiment, a method of fabricating a semiconductor device includes depositing a first mask layer over a target layer; forming a four-layer photoresist on the first mask layer; transferring a notch pattern of a first photoresist layer of the four photoresist layers to a first intermediate layer of the four photoresist layers; forming and transferring the notch pattern to a bottom layer of the four layers of photoresistors; transferring the notch pattern and the cut pattern of the bottom layer into the first mask layer; transferring the notch pattern and the cut pattern of the bottom layer into the first mask layer; and etching the target layer using the notch pattern and the cut pattern of the first mask layer to form a plurality of contact openings in the target layer. In one embodiment, the method further includes depositing a second photoresist layer over the first intermediate layer after transferring the notch pattern of the first photoresist layer to the first intermediate layer; and transferring a second notch pattern of the second photoresist layer to the first intermediate layer of the four photoresist layers, wherein the second notch pattern and the notch pattern are overlapped in an offset manner. In one embodiment, transferring the notch pattern of the first layer of four layers of photoresist to the first intermediate layer of four layers of photoresist further comprises exposing a first surface of a second intermediate layer of four layers of photoresist. In one embodiment, the first intermediate layer of the four-layer photoresist comprises a silicon oxynitride material. In one embodiment, the second intermediate layer of the four-layer photoresist comprises a metal oxide material. In one embodiment, a process gas used to etch the first intermediate layer comprises: a fluorine-containing gasThe body is selected from CF₄、NF₃And combinations of the foregoing; and a polymeric gas selected from CHF₃、CH₂F₂、CH₃F、C₄F₆、C₄F₈And combinations of the foregoing. In one embodiment, the target layer includes an interlayer dielectric layer disposed on a semiconductor structure, which includes a plurality of semiconductor fins. In one embodiment, the method further comprises filling a conductive material in the contact openings.

In one embodiment, a method of fabricating a semiconductor device includes forming a series of notches in a first intermediate layer of a compound photoresist layer disposed over a semiconductor structure; forming a patterned etch mask comprising a plurality of photoresist truncation islands in a second layer of photoresist disposed over the series of notches in the first intermediate layer of compound photoresist layer, the photoresist truncation islands spanning and filling a portion of the series of one or more notches in the first intermediate layer; transferring the series of notches and the patterned etching mask to a bottom layer of the compound photoresist layer to form a cut mask; and forming a plurality of contact openings through an interlayer dielectric layer disposed over the semiconductor structure using the cut-off mask, the contact openings exposing portions of source and drain regions of devices in the semiconductor structure. In one embodiment, forming the series of notches in the first intermediate layer of the compound photoresist layer includes forming a first series of notches in the first intermediate layer. In one embodiment, after forming the first series of notches, forming the series of notches in the first intermediate layer of the compound photoresist layer includes forming a second series of notches in the first intermediate layer, the second series of notches being offset from the first series of notches. In one embodiment, forming the patterned etch mask in the bottom layer of the compound photoresist layer includes using a hard mask layer disposed between the bottom layer of the compound photoresist layer and the interlayer dielectric layer as an etch stop layer for the bottom layer of the compound photoresist layer. In one embodiment, the hard mask layer is a material selected from the group consisting of tungsten carbide and titanium nitride. In one embodiment, a first surface of the hard mask layer is in contact with an underlayer of the compound photoresist layer, a second surface of the hard mask layer is in contact with the interlayer dielectric layer, and the second surface of the hard mask layer is opposite to the first surface of the hard mask layer. In one embodiment, forming the series of notches in the first intermediate layer of the compound photoresist layer includes using the second intermediate layer of the compound photoresist layer as a stop layer over the bottom layer of the compound photoresist layer.

In one embodiment, a method of fabricating a contact plug for a finfet device includes depositing a hard mask layer over a semiconductor structure; forming a four-layer photoresist layer above the hard mask layer; etching a series of notches in a first intermediate layer of the four photoresist layers; forming a patterned photoresist mask over the remaining portion of the first intermediate layer; transferring the patterned photoresist mask and the series of notches into an underlying layer of four photoresist layers; using the patterned photoresist mask and the series of notches in the bottom layer to form a kerf curtain layer in the hard mask layer; etching contact openings through an interlayer dielectric layer to surfaces of source and drain regions of the finfet devices in the semiconductor structure; and depositing a conductive material in the contact openings to form contact plugs of the finfet devices. In one embodiment, depositing a hard mask layer over the semiconductor structure includes depositing the hard mask layer in contact with an interlayer dielectric layer. In one embodiment, forming four photoresist layers over the hard mask layer includes depositing an underlayer of the four photoresist layers over the second surface of the hard mask layer, the underlayer being in contact with the second surface. In one embodiment, forming the patterned photoresist mask includes forming a plurality of photoresist truncation islands extending over and contacting the two or more remaining portions of the first intermediate layer over one or more of the series of notches located between the remaining portions of the first intermediate layer. In one embodiment, the method further includes using a second intermediate layer of the four photoresist layers as an etch stop layer for etching the series of notches in the first intermediate layer prior to the patterned photoresist mask and the series of notches into the bottom layer.

The components of several embodiments are summarized above so that those skilled in the art to which the disclosure pertains can more clearly understand the views of the embodiments of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, comprising:

depositing a first mask layer over a target layer;

forming a four-layer photoresist on the first mask layer;

transferring a notch pattern of a first photoresist layer of the four photoresist layers to a first intermediate layer of the four photoresist layers;

forming a notch pattern of an etching mask photoresist layer above the notch pattern of the first intermediate layer;

transferring the notch pattern to a bottom layer of the four-layer photoresist;

transferring the notch pattern and the cut pattern of the bottom layer into the first mask layer; and

the target layer is etched using the notch pattern and the cut pattern of the first mask layer to form a plurality of contact openings in the target layer.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising:

depositing a second photoresist layer on the first middle layer after transferring the notch pattern of the first photoresist layer to the first middle layer; and

transferring a second notch pattern of the second photoresist layer into the first intermediate layer of the four layers of photoresist, the second notch pattern being offset from and overlapping the notch pattern.

3. The method of claim 2, wherein transferring the notch pattern of the first layer of the four layers of photoresist into the first intermediate layer of the four layers of photoresist further comprises exposing a first surface of a second intermediate layer of the four layers of photoresist.

4. The method according to claim 3, wherein the first intermediate layer of the four-layer photoresist comprises a silicon oxynitride material.

5. The method of claim 1, wherein the target layer comprises an interlayer dielectric disposed on a semiconductor structure comprising a plurality of semiconductor fins.

6. The method of claim 1, further comprising filling a conductive material in the contact openings.

7. A method of manufacturing a semiconductor device, comprising:

forming a series of notches in a first intermediate layer of a compound photoresist layer disposed over a semiconductor structure;

forming a patterned etch mask comprising a plurality of photoresist truncation islands in a second layer of photoresist, the photoresist truncation islands disposed over the series of notches in the first intermediate layer of the compound photoresist layer, and the photoresist truncation islands spanning and filling a portion of one or more of the series of notches in the first intermediate layer;

transferring the series of notches and the patterned etch mask to a bottom layer of the compound photoresist layer to form a cut mask; and

a plurality of contact openings are formed using the cut-off mask, the contact openings passing through an interlayer dielectric layer disposed above the semiconductor structure, and the contact openings exposing portions of source and drain regions of a device in the semiconductor structure.

8. The method of claim 7, wherein forming the series of notches in the first intermediate layer of the compound photoresist layer comprises forming a first series of notches in the first intermediate layer.

9. The method of claim 7, wherein forming the patterned etch mask in the bottom layer of the compound photoresist layer comprises using a hardmask layer disposed between the bottom layer of the compound photoresist layer and the interlayer dielectric layer as an etch stop layer for the bottom layer of the compound photoresist layer.

10. A method of forming a contact plug for a finfet device, comprising:

depositing a hard mask layer over a semiconductor structure;

forming a four-layer photoresist layer above the hard mask layer;

etching a series of notches in a first intermediate layer of the four photoresist layers;

forming a patterned photoresist mask over the remaining portion of the first intermediate layer;

transferring the patterned photoresist mask and the series of notches into an underlying layer of the four photoresist layers;

using the patterned photoresist mask and the series of notches in the underlayer to form a kerf curtain layer in the hard mask layer;

etching contact openings through an interlayer dielectric layer to surfaces of source and drain regions of the finfet devices in the semiconductor structure; and

depositing a conductive material in the contact openings to form contact plugs of the finfet devices.