TWI824387B - Method for forming semiconductor memory structure - Google Patents

Abstract

A method for forming a semiconductor memory structure includes forming a first patterned hard mask layer over a conductive material, wherein the first patterned hard mask layer includes first strip patterns and a mesa pattern connected to the first strip patterns, forming a second patterned hard mask layer over the first patterned hard mask layer, wherein the second patterned hard mask layer includes second strip patterns overlapping the first strip patterns and first wire patterns overlapping the mesa pattern, etching the first patterned hard mask layer using the second patterned hard mask layer, wherein remaining portions of the first strip patterns form pad patterns, and remaining portions of the mesa pattern form second wire patterns, and transferring the pad patterns and the second wire patterns into the conductive material.

Description

Methods of forming semiconductor memory structures

The present disclosure relates to a method of forming a semiconductor memory structure, and in particular to a dynamic random access memory.

In order to increase the device density in a Dynamic Random Access Memory (DRAM) device and improve its overall performance, current DRAM device manufacturing technology continues to work toward miniaturization of device size. Therefore, improving the manufacturing method of DRAM devices is an important issue that must be faced at present.

Embodiments of the present invention provide methods for forming semiconductor memory structures. The method includes forming a conductive material on a dielectric structure, and forming a first patterned hard mask layer on the conductive material. The first patterned hard mask layer includes a plurality of first elongated patterns, and a first patterned hard mask layer. A raised platform pattern connected by long strips. The method also includes forming a second patterned hard mask layer on the first patterned hard mask layer, the second patterned hard mask layer including a plurality of second strip patterns overlapping the first strip patterns, and A plurality of first conductor patterns overlapping the mesa patterns. The method also includes etching the first patterned hard mask layer using a second patterned hard mask layer, the remaining portions of the first strip pattern forming a plurality of pad patterns, and the remaining portions of the mesas pattern forming a plurality of second conductive lines. pattern. The method also includes transferring the pad pattern and the second conductive line pattern to the conductive material.

Embodiments of the present invention provide methods for forming semiconductor memory structures. The method includes forming a first hard mask layer on a semiconductor substrate. The semiconductor substrate includes a memory cell array area and a peripheral circuit area. The method also includes forming a plurality of first elongated patterns on the first hard mask layer, and the first elongated patterns continuously extend in the memory cell array area and the peripheral circuit area. This method also forms a photoresist pattern on the first strip pattern to cover the peripheral circuit area and expose the memory cell array area, and uses the photoresist pattern and the first strip pattern to etch the first hard mask layer to form A plurality of second strip patterns located in the memory unit cell array area, and a mesas pattern located in the peripheral circuit area, and the second strip patterns and the mesas pattern of the patterned first hard mask layer are formed to respectively form A plurality of pad patterns in the memory cell array area and a plurality of conductor patterns located in the peripheral circuit area.

Please refer to Figures 17 and 17-1 first. The semiconductor memory structure 100 includes a substrate 102 and a dielectric structure 104 disposed on the substrate 102. The substrate 102 may define various device areas, such as the memory cell array area 50A, the peripheral circuit area 50B, and/or other applicable device areas. The left part of Figure 1-17 shows the memory cell array area 50A, which corresponds to the cross section A-A in the plan view; the right part of Figure 1-17 shows the peripheral circuit area 50B, which corresponds to the cross section B-B in the plan view. The peripheral circuit area 50B may be disposed adjacent to the memory cell array area 50A. Memory cells (eg, dynamic random access memory) are formed in the memory cell array area 50A to operate for data storage. Peripheral circuit devices are formed in the peripheral circuit area 50B to operate to access and/or control the memory cells in the memory cell array area 50A, for example, to perform read/write/erase operations.

In some embodiments, the substrate 102 may be or include a semiconductor substrate, which may be an elemental semiconductor substrate or a compound semiconductor substrate.

In the memory cell array region 50A of the substrate 102, the memory cell may include a gate structure (functioning as a word line) embedded in the semiconductor substrate, and a bit line disposed above the semiconductor substrate. The word lines extend through the active region of the substrate 102 and are combined with the source/drain regions in the active region to form a buried transistor. The bit lines may be electrically connected to the source/drain regions within the active region. The contact plug 160 is disposed in the dielectric structure 104 and is electrically connected to another source/drain region in the active region. Conductive pads (or landing pads) 162 are disposed on the dielectric structure 104 and are correspondingly disposed on the contact plugs 160 . In addition, dummy conductive pads 162D are provided at the edge of the memory cell array area 50A.

In the peripheral circuit region 50B of the substrate 102, the peripheral circuit devices may include planar transistors and/or multi-gate transistors including gate structures formed on the upper surface of the semiconductor substrate. The contact plug 108 is disposed in the dielectric structure 104 and the conductive wire 164 is disposed on the dielectric structure 104 . The wires 164 are electrically connected to the gate structure and/or the source/drain regions of the peripheral circuit device through the contact plugs 108 .

The conductive pads 162 in the memory cell array area 50A and the wires 164 in the peripheral circuit area 50B may be part of the interconnect structure and be metallization patterns at the same level (eg, zero metal layer (M1)). In the embodiment of the present invention, the conductive pads 162 and the conductive lines 164 are formed simultaneously by using the patterned hard mask layers 112A and 112B to transfer the pad patterns 210 and the conductive line patterns 208B to the conductive material. The method for forming the conductive pads 162 in the memory cell array area 50A and the conductive lines 164 in the peripheral circuit area 50B will be described in detail below.

Referring to FIG. 1 , a dielectric structure 104 is formed on the substrate 102 . The dielectric structure 104 may include one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), multiple layers of the foregoing, and/or combinations of the foregoing. The openings 106 may be formed in the dielectric structure 104 in the memory cell array region 50A through a patterning process (eg, including a photolithography process and an etching process).

Referring to FIG. 2 , one or more conductive materials 110 are formed on the dielectric structure 104 to overfill the opening 106 . The portion of conductive material 110 formed in opening 106 serves as contact plug 160 shown in FIG. 17 . The conductive material 110 may include polycrystalline silicon, metal silicides (eg, cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi)), metal nitrides (eg, titanium nitride (TiN)), or Tantalum nitride (TaN), metal materials (such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co) or ruthenium (Ru)), multiple layers of the foregoing, and/or combinations of the foregoing.

Next, a plurality of hard mask layers 112-128 are sequentially formed on the conductive material 110. The hard mask layer 112 is made of carbon-rich materials, such as diamond-like carbon (DLC), high selectivity transparent (HST) film, and/or spin-on carbon. carbon, SOC). Hard mask layer 114 is made of a semiconductor material, such as polysilicon. The hard mask layer 116 is made of a silicon-rich dielectric material, such as silicon-rich silicon oxynitride (Si-SiON) and/or silicon-rich anti-reflective layer (Si-BARC). Hard mask layer 118 is made of a carbon-rich material, such as a highly selective transparent film, diamond-like carbon, and/or spin-coated carbon. Hard mask layer 120 is made of a nitride layer, such as silicon nitride. Hard mask layer 122 is made of an oxide layer, such as silicon oxide. Hard mask layer 124 is made of a semiconductor material, such as polysilicon. Hard mask layer 126 is made of carbon-rich materials, such as spin-on carbon, diamond-like carbon, and/or highly selective transparent films. The hard mask layer 128 is made of a silicon-rich dielectric material, such as silicon-rich anti-reflective layer (Si-BARC) and/or silicon-rich silicon oxynitride (Si-SiON).

Next, through a first lithography process, a patterned photoresist layer 130 is formed on the hard mask layer 128 . The patterned photoresist layer 130 has elongated patterns 130A that are approximately equidistantly spaced from each other and are arranged in the memory cell array area 50A and the peripheral circuit area 50B. In some embodiments, the first lithography process uses immersion coating.

Referring to Figure 3, the patterned photoresist layer 130 is used to perform an etching process on the semiconductor memory structure 100 to sequentially etch and remove the portions of the hard mask layers 128, 126 and 124 that are not covered by the patterned photoresist layer 130. . The patterned photoresist layer 130 and the hard mask layer 128 can be completely consumed during the etching process, or removed through additional processes, such as etching or ashing processes. The etching process transfers the strip pattern 130A of the patterned photoresist layer 130 to the hard mask layers 126 and 124 to form the patterned hard mask layers 126A and 124A. The patterned hard mask layers 126A and 124A form the elongated pattern 202, which may also be referred to as a core pattern.

Referring to FIG. 4 , a spacer layer 132 is formed along the side walls and upper surface of the strip pattern 202 and the upper surface of the hard mask layer 122 . Next, a filling layer 134 is formed on the spacer layer 132 and the gaps between the long patterns 202 are excessively filled. Afterwards, portions of the spacer layer 132 and the filling layer 134 located above the upper surface of the elongated pattern 202 are removed to expose the patterned hard mask layer 126A. Spacer layer 132 is made of an oxide layer, such as silicon oxide. Filling layer 134 is made of spin-coated carbon.

Referring to Figures 5 and 5-1, an etching process is performed to remove the portion of the spacer layer 132 not covered by the filling layer 134, and further remove the portion of the hard mask layer 122 not covered by the filling layer 134 until the hard mask layer 122 is exposed. Mask layer 120. Since the material of spacer layer 132 (eg, silicon oxide) has a large etch selectivity difference from the material of fill layer 134 and hard mask layer 126 (eg, spin-on carbon), the etch process can be shifted in a self-aligned manner. Spacer layer 132 is removed without forming additional masks. The etching process also etches portions of the filling layer 134 and the patterned hard mask layer 126A.

After the etching process, the remaining portion of hard mask layer 122 is designated as 122A, the remaining portion of spacer layer 132 is designated as 132A, and the remaining portion of fill layer 134 is designated as 134A. The patterned hard mask layers 126A and 124A and the underlying hard mask layer 122A form a strip pattern 204 ₁ ; the filling layer 134A, the spacer layer 132A, and the underlying hard mask layer 122A form a strip pattern 204 ₂ .

The strip patterns 204 ₁ and 204 ₂ are alternately arranged in the memory cell array area 50A and the peripheral circuit area 50B. As shown in Figure 5-1, the strip patterns 204 (including 204 ₁ and 204 ₂ ) extend in the first direction D1 and are approximately equidistantly spaced from each other in the second direction D2. In some embodiments, the bit lines of the memory unit cell extend along the second direction D2, and the word lines of the memory unit cell extend along the third direction D3. The first direction D1 is not perpendicular to the second direction D2, and the second direction D2 is substantially perpendicular to the third direction D3.

Thereafter, fill layer 134A and patterned hard mask layer 126A may be removed.

Please refer to Figures 6 and 6-1. Through the second photolithography process, the photoresist pattern 136 is formed to cover the strip pattern 204 in the peripheral circuit area 50B and expose the strip pattern 204 in the memory cell array area 50A. . The photoresist pattern 136 is configured to prevent the elongated pattern 204 of the peripheral circuit area 50B from being transferred to the underlying hard mask layer. In some embodiments, the second lithography process uses lower-cost mid-ultraviolet mask (MUV Mask) technology.

Please refer to Figure 7, using the strip pattern 204 and the photoresist pattern 136, an etching process is performed on the semiconductor memory structure 100 to sequentially etch the portions of the hard mask layers 120 and 118 that are not covered by the strip pattern 204 and the photoresist pattern 136. . The spacer layer 132A and the patterned hard mask layer 124A in the memory cell array area 50A, and the photoresist pattern 136 in the peripheral circuit area 50B can be completely consumed during the etching process, or removed through additional processes. The etching process transfers the strip pattern 204 in the memory cell array area 50A to the hard mask layers 120 and 118 to form patterned hard mask layers 120A and 118A. Patterned hard mask layers 120A and 118A have elongated patterns 204 . Due to the coverage of the photoresist pattern 136, the strip pattern 204 is not transferred to the hard mask layers 120 and 118 in the peripheral circuit area 50B. Photoresist pattern 136 of peripheral circuit area 50B is transferred to hard mask layers 120 and 118 to form patterned hard mask layers 120B and 118B. Patterned hard mask layers 120B and 118B form mesas pattern 206 .

Referring to Figures 8 and 8-1, an etching process is performed on the semiconductor memory structure 100 to transfer the strip pattern 204 in the memory unit cell array area 50A to the hard mask layer 116 to form a patterned hard mask layer. 116A, and transfer the mesas pattern 206 in the peripheral circuit area 50B to the hard mask layer 116 to form the patterned hard mask layer 116B. The patterned hard mask layers 122A and 120A in the memory cell array region 50A may be completely consumed during the etching process. The etching process can be controlled so that the long pattern 204 in the peripheral circuit area 50B is completely consumed before being transferred to the patterned hard mask layer 118B, or the long pattern 204 in the peripheral circuit area 50B can be removed through an additional process, thereby This prevents the strip pattern 204 from being transferred to the high platform pattern 206. The platform pattern 206 is connected to a plurality of strip patterns 204, and the width of the platform pattern 206 in the second direction D2 is greater than the width of the strip pattern 204 in the second direction D2.

Due to the loading effect of the etching process, during the etching process, the portion of the photoresist pattern 136 (FIG. 6) adjacent to the boundary between the memory cell array area 50A and the peripheral circuit area 50B may be lost faster than the portion far from the boundary. . When the selection ratio difference between the photoresist pattern 136 and the hard mask layers 120 and/or 118 is small, when the strip pattern 204 in the memory cell array area 50A is transferred to the hard mask layers 120 and 118 At that time, some long strip patterns 204 in the peripheral circuit area 50B and close to the area boundary may also be transferred to the hard mask layers 120 and 118, and then further transferred to the hard mask layer 116. Thus, the conductive pattern 208B (FIG. 17) at the area boundary may encounter a pattern fail problem (also known as array punch through).

According to the embodiment of the present invention, since the hard mask layer 116 is a flat layer that has not been patterned, it can be adjusted by adjusting the parameters of the etching process (for example, a larger bias power, a higher etchant flow rate, and/or other suitable parameter), increasing the etching amount in the memory cell array area 50A, while maintaining a low etching amount of the photoresist pattern 136, so that there is a large gap between the photoresist pattern 136 and the hard mask layer 120 and/or 118. Choose than the difference. Therefore, the risk of the long pattern 204 at the area boundary being transferred to the hard mask layer 116 in the peripheral circuit area 50B can be greatly reduced. Therefore, the conductive pattern 208B is prevented from encountering pattern failure problems at the boundary between the memory cell array area 50A and the peripheral circuit area 50B, thereby improving the manufacturing yield of the semiconductor device.

Thereafter, patterned hard mask layers 118A and 118B may be removed.

Referring to FIG. 9 , a filling layer 138 is formed on the patterned hard mask layers 116A and 116B, and the gap between the patterned hard mask layers 116A is overfilled. Next, the portion of the filling layer 138 located above the patterned hard mask layers 116A and 116B is removed to expose the patterned hard mask layers 116A and 116B. Filling layer 134 is made of an oxide layer, such as silicon oxide.

Referring to FIG. 10 , a plurality of hard mask layers 140 - 150 are sequentially formed on the patterned hard mask layers 116A and 116B and the filling layer 138 . Hard mask layer 140 is made of a carbon-rich material, such as a highly selective transparent film, diamond-like carbon, and/or spin-coated carbon. Hard mask layer 142 is made of a nitride layer, such as silicon nitride. Hard mask layer 144 is made of an oxide layer, such as silicon oxide. Hard mask layer 146 is made of a semiconductor material, such as polysilicon. Hard mask layer 148 is made of a carbon-rich material, such as spin-coated carbon, diamond-like carbon, and/or a highly selective transparent film. The hard mask layer 150 is made of a silicon-rich dielectric material, such as silicon-rich anti-reflective layer (Si-BARC) and/or silicon-rich silicon oxynitride (Si-SiON).

Next, through a third photolithography process, a patterned photoresist layer 152 is formed on the hard mask layer 150, as shown in Figures 10 and 10-1. In the memory cell array area 50A, the patterned photoresist layer 152 has elongated patterns 152A and dummy patterns 152D located at the edges of the memory cell array area 50A. In the peripheral circuit area 50B, the patterned photoresist layer 152 has conductor patterns 152B. The long strip patterns 152A extend in the second direction D2 and are approximately equidistantly spaced from each other. In some embodiments, the third lithography process uses a dip coating method.

Referring to Figure 11, the patterned photoresist layer 152 is used to perform an etching process on the semiconductor memory structure 100 to sequentially etch and remove the portions of the hard mask layers 150, 148 and 146 that are not covered by the patterned photoresist layer 152. . Patterned photoresist layer 152 and hard mask layers 150 and 148 may be completely consumed during the etching process or removed through additional processes. The etching process transfers the strip patterns 152A and dummy patterns 152D of the patterned photoresist layer 152 to the hard mask layer 146 to form the patterned hard mask layer 146A. The patterned hard mask layer 146A has strip patterns 208A ₁ and dummy patterns (not shown). The conductive pattern 152B is transferred to the hard mask layer 146 to form the patterned hard mask layer 146B. Patterned hard mask layer 146B has conductor pattern 208B ₁ .

Referring to Figure 12, hard mask layers 154 and 156 are sequentially formed on the hard mask layer 144. Hard mask layer 154 is made of carbon-rich materials, such as spin-on carbon, diamond-like carbon, and/or highly selective transparent films. The hard mask layer 156 is made of a silicon-rich dielectric material, such as silicon-rich anti-reflective layer (Si-BARC) and/or silicon-rich silicon oxynitride (Si-SiON).

Next, through a fourth photolithography process, a patterned photoresist layer 158 is formed on the hard mask layer 156, as shown in Figures 12 and 12-1. In the memory cell array area 50A, the patterned photoresist layer 158 has a long pattern 158A and a dummy pattern 158D located at the edge of the memory cell array area 50A. In the peripheral circuit area 50B, the patterned photoresist layer 158 has a conductive pattern 158B. The elongated patterns 158A extend in the second direction D2 and are approximately equidistantly spaced from each other. In addition, the long pattern 158A is offset from the long pattern 208A ₁ of the patterned hard mask layer 146A, and the conductive pattern 158B is offset from the conductive pattern 208B ₁ of the patterned hard mask layer 146B. In some embodiments, the fourth lithography process uses a dip coating method.

Referring to Figures 13 and 13-1, the patterned photoresist layer 158 is used to perform an etching process on the semiconductor memory structure 100 to sequentially remove the hard mask layers 156 and 154 that are not covered by the patterned photoresist layer 158. part. The patterned photoresist layer 158 may be completely consumed during the etching process, or may be removed through additional processes. The etching process transfers the strip patterns 158A and dummy patterns 158D of the patterned photoresist layer 158 to the hard mask layers 156 and 154 to form the patterned hard mask layers 156A and 154A. Patterned hard mask layers 156A and 154A have strip patterns _208A2 and dummy patterns 208D. Wire pattern 158B is transferred to hard mask layers 156 and 154 to form patterned hard mask layers 156B and 154B. Patterned hard mask layers 156B and 154B constitute conductor pattern 208B ₂ .

Through two photolithography processes, the strip pattern 208A (including 208A ₁ and 208A ₂ ) in the memory cell array area 50A and the conductor pattern 208B (including 208B ₁ and 208B ₂ ) in the peripheral circuit area 50B are formed. Pattern density, which aids in the scaling of semiconductor memory devices.

Referring to Figure 14, the semiconductor memory structure 100 is subjected to an etching process to transfer the strip pattern 208A in the memory cell array area 50A to the hard mask layers 144, 142 and 140 to form a patterned hard mask layer. 144A, 142A, and 140A, and transfer the conductor pattern 208B in the peripheral circuit area 50B to the hard mask layers 144, 142, and 140 to form patterned hard mask layers 144B, 142B, and 140B. Although not shown, dummy pattern 208D is also transferred to hard mask layers 144, 142, and 140. Patterned hard mask layers 156A, 156B, 154A, 154B, 146A, and 146B may be completely consumed during the etching process, or may be removed through additional processes.

Please refer to Figures 15 and 15-1, and then use the strip pattern 208A, the dummy pattern 208D and the wire pattern 208B to perform an etching process on the semiconductor memory structure 100 to remove the patterned hard mask layers 116A and 116B and the filling. The portion of the layer 138 that is not covered by the strip pattern 208A, the dummy pattern 208D and the conductor pattern 208B. Patterned hard mask layers 144A, 144B, 142A, and 142B may be completely consumed during the etching process, or may be removed through additional processes.

The remaining portion of the patterned hard mask layer 116A after the etching process is labeled 116C, in which the strip pattern 204 is patterned into a pad pattern 210 in the center of the memory cell array area 50A, and in the memory cell array area 50A At the edge of the array area 50A, the strip pattern 204 is patterned into a dummy pad pattern 210D. The remaining portion of fill layer 138 after the etching process is designated 138A. For simplicity and clarity, the filling layer 138A is not shown in Figure 15-1. In the peripheral circuit area 50B, the etching process transfers the conductive pattern 208B to the patterned hard mask layer 116B, and the remaining portion of the patterned hard mask layer 116B is labeled 116D.

According to the embodiment of the present invention, the pad pattern 210 is formed by patterning twice. Specifically, the hard mask layer 116 is patterned for the first time (through the first lithography process and the second lithography process) to form the strip pattern 204, and then patterned for the second time (through the third and fourth lithography processes). Lithography process) to form the pad pattern 210. In some cases, if the hard mask layer 116 is first patterned into the strip pattern 208 through the third and fourth lithography processes, and then the strip pattern 208 is patterned through the first lithography process and the second lithography process. For the pad pattern 210, it is not possible to increase the etching amount in the memory cell array area 50A as described in FIG. 8 because this may cause the pad pattern in the memory cell array area to be deformed due to excessive etching. Therefore, the process steps disclosed in the embodiments of the present invention can relax the tolerance of the etching process for forming the pad pattern 210 .

Referring to Figure 16, the semiconductor memory structure 100 is subjected to an etching process to transfer the pad pattern 210 and the dummy pad pattern 210D in the memory cell array area 50A to the hard mask layers 114 and 112 to form patterning. Hard mask layers 114A and 112A, and the conductive pattern 208B in the peripheral circuit area 50B is transferred to the hard mask layers 114 and 112 to form patterned hard mask layers 114B and 112B. Patterned hard mask layers 140A and 140B may be completely consumed during the etching process, or may be removed through additional processes. In addition, since the material of the filling layer 138 (eg, silicon oxide) and the hard mask layer 116 (eg, silicon-rich silicon oxynitride) have a large etch selectivity difference, the filling layer 138A can be completely removed during the etching process. remove.

Referring to Figures 17 and 17-1, the semiconductor memory structure 100 is subjected to an etching process to transfer the pad patterns 210 and dummy pad patterns 210D in the memory unit cell array area 50A to the conductive material 110 to form conductive pads. 162 and dummy conductive pad 162D, and transfer the conductive pattern 208B in the peripheral circuit area 50B to the conductive material 110 to form the conductive line 164. Patterned hard mask layers 116C, 116D, 114A, and 114B may be completely consumed during the etching process, or may be removed through additional processes.

Afterwards, the patterned hard mask layers 112A and 112B can be removed through an etching or ashing process to expose the conductive pads 162 , the dummy conductive pads 162D and the wires 164 . In some embodiments, a capacitor may be formed on the conductive pad 162. The capacitor may include a lower electrode layer contacting the conductive pad 162, a capacitive dielectric layer on the lower electrode layer, and an upper electrode on the capacitive dielectric layer. layer. The lower electrode layer is electrically coupled to the source/drain regions in the active region through conductive pads 162 and contact plugs 160 .

The embodiment of the present invention simultaneously forms the pad pattern 210 in the memory cell array area 50A and the conductor pattern 208B in the peripheral circuit area 50B by using three dip coating methods and one-time ultraviolet mask technology. Therefore, compared with the case where the pad pattern in the memory cell array area and the conductor pattern in the peripheral circuit area are formed separately, embodiments of the present invention can save at least one photolithography process (eg, dip coating method). Therefore, the process cost of the semiconductor memory structure is saved and the process difficulty is reduced.

According to the above, the method for forming a semiconductor memory structure according to embodiments of the present invention can significantly reduce the risk of pattern transfer in the memory unit cell array area to the peripheral circuit area. Therefore, the conductor pattern in the peripheral circuit area is prevented from encountering pattern failure problems at the boundary between the memory cell array area and the peripheral circuit area, thereby improving the manufacturing yield of the semiconductor device.

Although the present invention is disclosed in the foregoing embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

50A: Memory unit cell array area 50B: Peripheral circuit area 100: Semiconductor memory structure 102: Substrate 104: Dielectric structure 106: Opening 108: Contact plug 110: Conductive material 112: Hard mask layer 112A: Patterned hard Mask layer 112B: Patterned hard mask layer 114: Hard mask layer 114A: Patterned hard mask layer 114B: Patterned hard mask layer 116: Hard mask layer 116A: Patterned hard mask layer 116B: Pattern Patterned hard mask layer 116C: Patterned hard mask layer 116D: Patterned hard mask layer 118: Hard mask layer 118A: Patterned hard mask layer 118B: Patterned hard mask layer 120: Hard mask layer 120A :Patterned hard mask layer 120B: Patterned hard mask layer 122: Hard mask layer 122A: Hard mask layer 124: Hard mask layer 124A: Patterned hard mask layer 126: Hard mask layer 126A: Pattern Hard mask layer 128: Hard mask layer 130: Patterned photoresist layer 130A: Strip pattern 132: Spacer layer 132A: Spacer layer 134: Filling layer 134A: Filling layer 136: Photoresist pattern 138: Filling layer 138A: Filling layer 140: Hard mask layer 140A: Patterned hard mask layer 140B: Patterned hard mask layer 142: Hard mask layer 142A: Patterned hard mask layer 142B: Patterned hard mask layer 144: Hard mask layer 144A: Patterned hard mask layer 144B: Patterned hard mask layer 146: Hard mask layer 146A: Patterned hard mask layer 146B: Patterned hard mask layer 148: Hard mask layer 150: Hard mask layer 152: Patterned photoresist layer 152A: Long pattern 152B: Wire pattern 152D: Dummy pattern 154: Hard mask layer 154A: Patterned hard mask layer 154B: Patterned hard mask layer 156: Hard mask Cover layer 156A: Patterned hard mask layer 156B: Patterned hard mask layer 158: Patterned photoresist layer 158A: Strip pattern 158B: Wire pattern 158D: Dummy pattern 160: Contact plug 162: Conductive pad 162D: Dummy Conductive pad 164: Wire 202: Long pattern 204: Long pattern 204 ₁ : Long pattern 204 ₂ : Long pattern 206: High platform pattern 208A: Long pattern 208A ₁ : Long pattern 208A ₂ : Long pattern 208B: Conductor pattern 208B ₁ : Conductor pattern 208B ₂ : Conductor pattern 208D: Dummy pattern 210: Pad pattern 210D: Dummy pad pattern D1: First direction D2: Second direction D3: Third direction

To make the features and advantages of the present invention more obvious and understandable, different embodiments are given below and are described in detail with reference to the accompanying drawings: 1 to 17 are schematic cross-sectional views showing different stages of forming a semiconductor memory structure according to some embodiments of the present invention. Nos. 5-1, 6-1, 8-1, 10-1, 12-1, 13-1, 15-1, and 17-1 are plan views of semiconductor memory structures according to some embodiments of the present invention.

50A: Memory unit cell array area 50B: Peripheral circuit area 204:Long pattern 206:High platform pattern D1: first direction D2: second direction D3: Third direction

Claims (8)

A method of forming a semiconductor memory structure, including: forming a conductive material on a dielectric structure; forming a first patterned hard mask layer on the conductive material, wherein the first patterned hard mask layer including a plurality of first strip patterns and a platform pattern connected to the first strip patterns; forming a second patterned hard mask layer on the first patterned hard mask layer, wherein the second patterned hard mask layer The two patterned hard mask layers include a plurality of second strip patterns overlapping the first strip patterns, and a plurality of first conductor patterns overlapping the platform patterns; the second patterned hard mask layer is used to etch the a first patterned hard mask layer, wherein the remaining portions of the first strip patterns form a plurality of pad patterns, and the remaining portions of the mesas patterns form a plurality of second conductor patterns; and combining the pad patterns and The second conductor patterns are transferred to the conductive material. The method for forming a semiconductor memory structure of claim 1, wherein the first strip patterns extend in a first direction, the second strip patterns extend in a second direction, and the second direction does not parallel to the first direction. The method of forming a semiconductor memory structure as claimed in claim 1, further comprising: forming a filling layer on the first patterned hard mask layer before forming the second patterned hard mask layer on the first patterned hard mask layer. above the strip patterns and between the first strip patterns; and remove the portion of the filling layer located above the first strip patterns. The method of forming a semiconductor memory structure as claimed in claim 3, further comprising: using the second patterned hard mask layer to etch the first patterned hard mask layer, and simultaneously using the second patterned hard mask layer to etch the filling layer; and completely removing the filling layer before transferring the pad patterns to the conductive material. The method for forming a semiconductor memory structure as claimed in claim 1 further includes: forming Before the first patterned hard mask layer: form a hard mask layer on the dielectric structure; form a plurality of third strip patterns on the hard mask layer; form a photoresist pattern to cover these a first portion of the third strip pattern, and expose a second portion of the third strip pattern; and using the third strip pattern and the photoresist pattern, etch the hard mask layer, wherein the The exposed second portion of the third strip pattern is transferred to the hard mask layer to form the first strip patterns, and the photoresist pattern is transferred to the hard mask layer to form the platform pattern. The method of forming a semiconductor memory structure as claimed in claim 1, wherein the dielectric structure has a plurality of openings, and the conductive material is formed in the openings of the dielectric structure to form a plurality of contact plugs. The pad pattern is transferred to the conductive material to form a plurality of conductive pads, and each conductive pad corresponds to each of the contact plugs. The method of forming the semiconductor memory structure further includes: removing the pad patterns; and forming a plurality of conductive pads. Capacitors are structured on the conductive pads. The method of forming a semiconductor memory structure as claimed in claim 1, wherein the second patterned hard mask layer further includes a plurality of fourth strip patterns, wherein the fourth strip patterns alternate with the second strip patterns. arrangement. The method of forming a semiconductor memory structure as claimed in claim 7, wherein forming the second strip patterns of the second patterned hard mask layer includes performing a first photolithography process, and forming the second patterned hard mask layer. The fourth elongated patterns of the cover layer include performing a second lithography process after the first lithography process.

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