CN111125981B

CN111125981B - Wiring method for integrated circuit VLSI

Info

Publication number: CN111125981B
Application number: CN201911363307.7A
Authority: CN
Inventors: 黄海山; 张亚东; 陈建利; 李起宏; 陆涛涛; 刘伟平
Original assignee: Beijing Empyrean Technology Co Ltd
Current assignee: Beijing Empyrean Technology Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2022-06-21
Anticipated expiration: 2039-12-26
Also published as: CN111125981A

Abstract

A method of routing an integrated circuit VLSI, comprising the steps of: 1) reading in net port information to generate port graph; 2) constructing a grid graph according to related parameters of wiring; 3) connecting two adjacent connected bodies to generate a new connected body, and taking a grid overlapped by the new connected body and the grid diagram as an expansion starting point participating in next iteration of connecting the two adjacent connected bodies; 4) and repeating the step 3) until all the port graphs and the connecting lines thereof in the wire net form a new connected body. The integrated circuit VLSI wiring method of the invention can be connected to other port graphs or wiring paths from a certain point in the generated wiring paths, breaks the limit that the traditional algorithms such as kruskal, prim and the like can only connect end graphs to end points, and obviously reduces the wiring line length.

Description

Wiring method for integrated circuit VLSI

Technical Field

The invention relates to the technical field of integrated circuit VLSI, in particular to a wiring method of the integrated circuit VLSI.

Background

In the detailed wiring stage of the VLSI of the very large scale integrated circuit, one net often has a plurality of port graphs waiting for connection, and in order to optimize the important cost value of the net line length after the net is connected, a commonly used algorithm is to construct the connection relationship between the net port graphs by using the idea of the minimum spanning tree algorithm such as prim, kruskal and the like, but the minimum spanning tree algorithm can only realize the connection from the port graphs to the port graphs, and cannot optimize and reduce the line length during wiring.

Disclosure of Invention

In order to solve the defects of the prior art, the invention aims to provide a wiring method for an integrated circuit VLSI, which can be connected to other port graphs or wiring paths from a certain point in the generated wiring paths in a detailed wiring stage, breaks through the limitation that the traditional algorithms such as kruskal and prim can only connect end graphs to end points, and remarkably reduces the length of the wiring line.

In order to achieve the above object, the present invention provides a wiring method for VLSI integrated circuits, comprising the steps of:

1) reading in net port information to generate port graph;

2) constructing a grid graph according to related parameters of wiring;

3) connecting two adjacent connected bodies to generate a new connected body, and taking a grid superposed by the new connected body and the grid diagram as an expansion starting point participating in next iteration of connecting the two adjacent connected bodies;

4) and repeating the step 3) until all the port graphs and the connecting lines thereof in the wire net form a new connected body.

Further, the method also comprises checking the wiring result and outputting the long data.

Further, the step 2) further comprises constructing the wiring area of the net into a three-dimensional structure consisting of rectangular blocks with rows and columns being multiplied by height.

Further, when two adjacent rectangular blocks are passed, a path of wiring is generated.

Further, the step 3) further comprises,

in an initial state, the port graphs do not have a connection relation, and each port graph is a communicating body;

in an iterative process of generating paths by routing, the via includes the port graph and the set of path graphs that generate path connectivity.

Further, the step 3) further includes that each of the port graphs includes a priority queue, the priority queues are sorted in ascending order according to the cost of the node, and the nodes with low cost are preferentially popped.

Further, the method includes that, initially, a lattice node where each port graph is overlapped with the grid is added into a priority queue corresponding to the port, and the priority queue is used as a starting point of the expansion wave corresponding to the port.

Further, the step 3) further includes that each of the connected bodies includes an expansion wave, and a plurality of the expansion waves simultaneously expand to find the connected body with the shortest manhattan distance.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the method for routing an integrated circuit VLSI as described above.

To achieve the above object, the present invention further provides a wiring device for a VLSI integrated circuit, comprising a memory and a processor, wherein the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the steps of the wiring method for the VLSI integrated circuit as described above.

The wiring method of the integrated circuit VLSI of the invention has the following beneficial effects:

1) in the detailed wiring stage, the variable kruskal algorithm of the invention is applied to connect the endpoints waiting for connection in the multi-terminal network by using a common tree structure or a Steiner tree structure, and simultaneously, the design rule constraint of the detailed wiring stage is satisfied as much as possible.

2) The generated wiring paths can be connected to other port graphs or the wiring paths from a certain point, so that the limitation that the traditional algorithms such as kruskal, prim and the like can only connect the end point graphs to the end points is broken, and the length of the wiring lines is obviously reduced.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of a method of routing an integrated circuit VLSI in accordance with the present invention;

FIG. 2 is a schematic view of a layout process layer geometric constraint setup page according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating multi-wave expansion of a multi-terminal net according to the present invention;

FIG. 4 is a schematic diagram of an initial distribution of ports of a multi-port net according to the present invention;

FIG. 5 is a diagram illustrating the result of multi-terminal net routing according to the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

In the embodiment of the invention, the processing analysis is carried out by using the multiple port graphs of a single net, and the subsequent processing method of the multiple port graphs aiming at the multiple nets is similar.

Fig. 1 is a flow chart of a wiring method of an integrated circuit VLSI according to the present invention, and the wiring method of the integrated circuit VLSI according to the present invention will be described in detail with reference to fig. 1.

First, in step 101, wiring port information is read in, and a port pattern to be connected is generated. In this step, a plurality of port patterns waiting for connection of a single or multiple nets in the wiring input file are read. According to geometric constraints, a multi-port wiring command is started, wiring port information is read, and information such as the size and the position of a plurality of ports of a wire net is displayed on a GUI interface.

At step 102, a grid map is constructed based on the routing related parameters. In the step, a grid is used for constructing the whole wiring area into a chessboard map structure with rows and columns, the grid map is a three-dimensional structure consisting of rectangular blocks with rows and columns and high, and in the expanding process, when the grid map passes through two adjacent rectangular blocks, a section of wiring path is formed.

In step 103, two nearest connected integers are connected in sequence, the two nearest connected integers and the connecting lines of the two nearest connected integers form a new connected integer, and the grid overlapped by the new connected integer and the grid map is used as an expansion starting point participating in the next iteration of connecting the two nearest connected integers. In the step, the modification is made on the basis of the original concept inspired by the idea of kruskal connection end points, and the method specifically comprises the following steps: in the initial state, no connection exists between every two port graphs, each single port graph is regarded as a communicated whole, two nearest communicated whole bodies are connected, the connected communicated whole bodies and the connecting lines of the connected communicated whole bodies are regarded as a new communicated whole body, one or more grids overlapped by the new communicated whole body and the chessboard map are used as the expansion starting points of the grids participating in the next iteration of connecting the two nearest communicated whole bodies, and the Dijkstra algorithm is used for starting the expansion of wiring nodes.

Preferably, the definition of connected ensemble includes: in the initial stage of multi-port network wiring, the whole connected graph refers to each independent port graph; in the iterative process of generating the path by the wiring, the connected whole refers to a set of the port graph and the path graph which are connected by the generated path, and a connected set of the port graph and the path graph is a connected whole.

Preferably, each port graph is regarded as an independent connected whole, each port graph is provided with a priority queue for maintaining the expansion process of the port graph, the priority queues are sorted in an ascending order according to the cost of the node, and the node with low cost is firstly popped up. Initially, one or more grid nodes where each port graph coincides with the grid map are added to the priority queues corresponding to the ports respectively, and the grid nodes serve as starting points of port wave front expansion.

FIG. 3 is a schematic diagram of multi-wave expansion of a multi-port net according to the present invention.

Preferably, as shown in fig. 3, each connected ensemble has a wave maintaining its own expansion, and multiple waves expand simultaneously to find the connected ensemble pair with the shortest manhattan distance.

Preferably, each time two connected integers are connected, the two connected integers and the connection line between the two connected integers are taken as a new connected integer to participate in the next iteration process for connecting the two nearest connected integers. This may achieve the effect of connecting from a certain point in the generated path to other end point graphics or path graphics.

FIG. 4 is a diagram illustrating an initial distribution of ports of a multi-port net according to the present invention.

In step 104, step 103 is repeated until all port patterns in the net and their connections constitute a new connected whole. In this step, the kruskal and Dijkstra algorithms are modified and applied.

In step 105, the wiring results are checked and relevant wire length data is output. In this step, the final wiring result is displayed on the GUI interface.

The invention is further described below in connection with a specific embodiment of a method for routing an integrated circuit VLSI.

FIG. 2 is a schematic diagram of a layout process layer geometric constraint setup page according to an embodiment of the invention.

(1) And reading the port information and the barrier information parameters of the multi-port network and displaying the port information and the barrier information parameters on a GUI (graphical user interface) as shown in FIG. 2.

(2) The multi-port net routing command is initiated to begin routing, with the routing results shown in FIG. 5.

The invention provides a method for constructing a wiring spanning tree by a variant kruskal algorithm considering the integral expansion of a multi-terminal net port and a connecting line in the VLSI detailed wiring, wherein in the detailed wiring stage, the variant kruskal algorithm of the invention is applied to connect the endpoints waiting for connection in the multi-terminal net by using a common tree structure or a Steiner tree structure, and simultaneously, the design rule constraint of the detailed wiring stage is satisfied as much as possible.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when running, performs the steps of the method for routing an integrated circuit VLSI as described above.

To achieve the above object, the present invention further provides a wiring device for an integrated circuit VLSI, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the wiring method for the integrated circuit VLSI as described above.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of routing an integrated circuit VLSI, comprising the steps of:

1) reading in net port information to generate port graph;

the step 1) further comprises that, in an initial state, no connection relation exists between the port graphs, and each port graph is a connected body;

2) constructing a grid graph according to related parameters of wiring;

3) connecting two adjacent connected bodies to generate a new connected body, and taking a grid overlapped by the new connected body and the grid diagram as an expansion starting point participating in next iteration of connecting the two adjacent connected bodies;

2. The method of routing in an integrated circuit VLSI according to claim 1, further comprising checking routing results and outputting long data.

3. The method of routing an integrated circuit VLSI as claimed in claim 1 wherein step 2) further comprises constructing the routing area of said net as a three-dimensional structure of row by column by height tiles.

4. A method of routing in an integrated circuit VLSI as claimed in claim 3 wherein a routing path is created when a routing node crosses two adjacent said tiles.

5. The method of routing an integrated circuit VLSI according to claim 1, wherein said step 3) further comprises,

in an iterative process of generating paths by routing, the via includes the port graph and the set of path graphs for path connectivity.

6. The method of routing integrated circuits VLSI as claimed in claim 1 wherein said step 3) further comprises each of said port patterns including a priority queue, said priority queue being ordered in ascending node cost and preferentially popping said nodes having a lower cost.

7. The integrated circuit VLSI routing method of claim 6, further comprising initially adding each grid node of said port pattern coinciding with a grid to a priority queue corresponding to said port as a starting point for a corresponding spreading wave expansion of said port.

8. The integrated circuit VLSI routing method of claim 1, wherein said step 3) further comprises each of said vias comprising an expansion wave, a plurality of said expansion waves simultaneously expanding for finding the shortest manhattan distance via.

9. A computer readable storage medium having computer instructions stored thereon, wherein said computer instructions when executed perform the method steps of integrated circuit VLSI as claimed in any of claims 1 to 8.

10. A wiring device for a VLSI integrated circuit, comprising a memory and a processor, said memory having stored thereon computer instructions for execution on said processor, said processor executing said computer instructions to perform the method steps of the integrated circuit VLSI wiring method of any of claims 1 to 8.