CN111124364A - Device and method for generating pseudo-random sequences with different levels - Google Patents
Device and method for generating pseudo-random sequences with different levels Download PDFInfo
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Abstract
The invention discloses a device for generating pseudo-random sequences of different levels, which is characterized by comprising a memory for receiving random pseudo codes sent by a plurality of variable length shift registers, wherein two adjacent variable length shift registers carry out binary addition operation of the random pseudo codes through an addition switch unit, and the random pseudo codes are output after being stored by the memory for improving the universality of the pseudo code generating device, and the implementation mode of the device is as follows: the device consists of a variable-length shift register, a binary addition switch unit and a memory. The variable-length shift register is composed of a plurality of shift register units, and is different from the traditional shift register, the variable-length shift register is provided with a control enabling end, and the switching of combinational logic and sequential logic can be carried out. When enabled, the shift register performs a sequential logic function, similar to a D flip-flop in a digital circuit, that is, passes input data to the output on the clock active edge.
Description
Technical Field
The invention relates to a random sequence generating device and a generating method thereof, in particular to a generating device and a generating method of pseudo-random sequences with different levels.
Background
The direct sequence spread spectrum modulation is used for expanding the bandwidth of a baseband signal by multiplying the baseband signal by a high-speed pseudo code sequence, and the signal after the spread spectrum is used for modulating a carrier wave and then is transmitted out with a lower signal-to-noise ratio; and after the carrier is stripped from the received signal by the receiving end, multiplying the signal by the synchronous local pseudo-random code to complete the de-spreading and recover the baseband signal. Therefore, the spread spectrum communication has the characteristic of good anti-interference performance, and is widely applied to the fields of satellite communication, navigation communication and the like.
In the related field, a pseudo code generating device can only generate a pseudo code sequence with fixed progression when direct sequence spread spectrum modulation is carried out, and the device cannot be continuously used when an application scene changes. In practical spread spectrum communication engineering, pseudo code sequences of different levels are often needed to verify the reliability of the system. This requires that the pseudo-code generating means be able to generate pseudo-code sequences of different order. Therefore, in the spread spectrum communication engineering, the pseudo code generating device with different levels and strong universality can provide great convenience for engineering implementation.
In order to solve the problems, the invention provides a strong-universality pseudo code generating device, and further provides an efficient engineering application method in order to further improve the efficiency of the pseudo code generating device. .
Disclosure of Invention
The invention aims to solve the technical problem that a pseudo code generating device can only generate a pseudo code sequence with fixed series, cannot be continuously used when an application scene is changed, and requires the pseudo code generating device to generate pseudo code sequences with different series.
The invention is realized by the following technical scheme:
a device for generating pseudo-random sequences of different numbers and a generating method thereof comprise that a memory receives random pseudo codes sent by a plurality of variable length shift registers, two adjacent variable length shift registers carry out binary addition operation of the random pseudo codes through an addition switch unit, and the random pseudo codes are stored by the memory and then output.
The invention provides an efficient method for reducing the pseudo code generation time consumption. The memory of the invention adopts a clock domain crossing device, namely a high-speed clock is adopted to generate pseudo codes to be stored in the memory, and the pseudo codes are read out at a pseudo code rate when the memory is used. The consumed time is 1022x0.017us 17.374us calculated by generating the pseudo code sequence with the length of 1023 by using the 60M system clock signal, compared with the pseudo code rate used as the pseudo code generating clock, the consumed time is saved by more than 7 times, and the specific efficiency is different according to the actual engineering situation.
Furthermore, the basic unit of the variable length shift register is RiSaid shift register unit Ri+1And RiIs marked as Xi+1Wherein n is a natural number, and i is 1, 2, and.
The adding switch unit being a binary adding switch unit SjWhether or not to perform a binary addition operation is controlled by the primitive polynomial, where j takes 1, 2.
When primitive polynomial poly [ k ]]When 1, SnWill output the binary addition result of the input signal, otherwise will Sk+1Is transmitted to the output, where k takes 1, 2.
When the generating device is powered on, when the control signal ctrl [ m ] is]When 1, the variable length register unit RmExecuting a shift function, otherwise, directly connecting the input and the output; at start-up, the register initial value is loaded by clock edge trigger, after start-up, the shift is performed under the control of clock edge, and each effective edge is shifted by one bit, the above-mentioned ctrl [ m ] is]And represents the m-th bit value of the ctrl signal, wherein m is 0, 2, and n-1.
A method for generating pseudo-random sequences of different numbers of levels, the method comprising the steps of: s1: determining the working number of the shift register units through the length control signal; s2: loading the initial value of the register in a shift register; s3: the addition unit is controlled by the primitive polynomial to generate the next clock write R1A value of (1); s4: r is to benThe value of (a) is stored in a memory; s5: and outputting the pseudo code through a memory.
The memory in the step S5 adopts a clock domain crossing device, and stores the generated pseudo code into the memory under a high-speed clock; when in use, the pseudo code is read out by the actually needed pseudo code clock.
When the clock domain crossing device generates the pseudo code, the write-in operation is executed, the write-in clock is a system clock, after the write-in is completed, the write-in is not performed unless the pseudo code sequence is updated, and then the read-out operation is executed according to the requirement of a rear-stage module.
The length control signal can control the number of working register units, thereby realizing the generation of pseudo code sequences of different stages.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the invention relates to a device and a method for generating pseudo-random sequences with different levels, and provides an efficient method for reducing pseudo code generation time consumption. The memory adopts a clock domain crossing device, namely a high-speed clock is adopted to generate pseudo codes to be stored in the memory, and the pseudo codes are read out at a pseudo code rate when the memory is used;
2. the invention relates to a device and a method for generating different-stage pseudo-random sequences, which realize the length control of a shift register by controlling an enabling signal of each shift register, and have the basic condition of generating different-stage pseudo-random sequences;
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The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a block diagram of the system of the present invention.
Reference numbers and corresponding part names in the drawings:
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Examples
As shown in figure 1, the device for generating pseudo-random sequences with different orders is characterized by comprising a memory for receiving random pseudo codes sent by a plurality of variable length shift registers, and two adjacent variable length shift registers carry out binary addition operation of the random pseudo codes through an addition switch unit and are stored by the memory and then output.
For improving the universality of the pseudo code generating device, the realization mode of the invention is as follows: the device consists of a variable-length shift register, a binary addition switch unit and a memory.
The variable-length shift register is composed of a plurality of shift register units, and is different from the traditional shift register, the variable-length shift register is provided with a control enabling end, and the switching of combinational logic and sequential logic can be carried out. When enabled, the shift register performs a sequential logic function, similar to a D flip-flop in a digital circuit, that is, passes input data to the output on the clock active edge. When enabled and disabled, it functions like a wire in combinational logic, passing input data directly to the output. By controlling the enable signal of each shift register, the length control of the shift registers is realized, and the basic condition for generating pseudo-random sequences with different levels is provided.
For the generation of different pseudo code sequences with the same series, we usually adopt a method of changing primitive polynomial to realize. For the conventional pseudo code generating device, after the primitive polynomial is determined, the structure of the circuit is fixed. In order to realize the generation of different pseudo code sequences with the same number of stages, a binary addition unit is used, and the unit and the traditional binary addition unit belong to combinational logic devices, but the unit can be controlled by corresponding digits of a primitive polynomial. The binary addition switch unit has three inputs, one output, and the three inputs are respectively: the output X of the shift register of this stageiOutput S of preceding binary addition uniti-1And a control input. When the enable signal, i.e. the corresponding bit of the primitive polynomial, is 1, the output is Xi+Si-1When the corresponding bit is 0, the output is Si-1Thus, the construction of different primitive polynomial circuits is realized, and based on the device, the device can be used for realizing the operation of the circuitIt can generate pseudo-random codes with different numbers of stages, same number of stages and different sequences.
In the spread spectrum engineering, after the design scheme is determined, the code rate of the pseudo-random sequence is determined accordingly. The clock added to the system is 60MHz, the code rate of the pseudo random code is 8MHz, if the working time of the shift register (i.e. the number of shifts times the clock period) is taken as the total time consumed by the pseudo code generating device, then we generate a pseudo random sequence with length of 1023, and the traditional method takes the code rate as the pseudo code generating clock, and the time is 1022 × 0.125us 127.75 us. The invention provides an efficient way to reduce the consumption of pseudo code generation time, compared to 17.374us for the pseudo code generation clock, which is the system clock.
Taking the generation of 10-level pseudo code as an example, when the system is powered on, the length control ctrl is made to be 10' b11_1111_1111, so that the length control ctrl controls the variable length shift register working unit to be R1To R10Then setting initial register value state and primitive polynomial poly value, starting pseudo code generation, and simultaneously, carrying out write operation on the memory; when the generation of the pseudo code is finished, the memory stops the write operation until the length of the register is controlled, the initial value of the register or the primitive polynomial is changed, and then the write operation is carried out again; after the write operation is completed, the memory performs a read operation according to the requirements of the subsequent circuit.
The basic unit of the variable length shift register is RiSaid shift register unit Ri+1And RiIs marked as Xi+1Wherein n is a natural number, and i is 1, 2, and.
The adding switch unit being a binary adding switch unit SjWhether or not to perform a binary addition operation is controlled by the primitive polynomial, where j takes 1, 2.
When primitive polynomial poly [ k ]]When 1, SnWill output the binary addition result of the input signal, otherwise will Sk+1Is transmitted to the output, where k takes 1, 2.
When the generating device is powered on, when the control signal ctrl [ m ] is]When 1, the variable length register unit RmPerforming a shift function, otherwise, straightening the input and outputConnecting; at start-up, the register initial value is loaded by clock edge trigger, after start-up, the shift is performed under the control of clock edge, and each effective edge is shifted by one bit, the above-mentioned ctrl [ m ] is]And represents the m-th bit value of the ctrl signal, wherein m is 0, 2, and n-1.
A method for generating pseudo-random sequences of different numbers of levels, the method comprising the steps of: s1: determining the working number of the shift register units through the length control signal; s2: loading the initial value of the register in a shift register; s3: the addition unit is controlled by the primitive polynomial to generate the next clock write R1A value of (1); s4: r is to benThe value of (a) is stored in a memory; s5: and outputting the pseudo code through a memory. The memory in the step S5 adopts a clock domain crossing device, and stores the generated pseudo code into the memory under a high-speed clock; when in use, the pseudo code is read out by the actually needed pseudo code clock. When the clock domain crossing device generates the pseudo code, the write-in operation is executed, the write-in clock is a pseudo code generating clock, after the write-in is completed, the write-in is not performed unless the pseudo code sequence is updated, and then the read-out operation is executed according to the requirement of a rear-stage module. The length control signal can control the number of working register units, thereby realizing the generation of pseudo code sequences of different stages.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A device for generating pseudo-random sequences with different series numbers is characterized by comprising a memory for receiving random pseudo codes sent by a plurality of variable length shift registers, wherein two adjacent variable length shift registers carry out binary addition operation of the random pseudo codes through an addition switch unit, and the random pseudo codes are stored by the memory and then output.
2. The apparatus of claim 1, wherein the variable length shift register has a basic unit of RiSaid shift register unit Ri+1And RiIs marked as Xi+1Wherein n is a natural number, and i is 1, 2, and.
3. The apparatus of claim 1, wherein the summing switch unit is a binary summing switch unit SjWhether or not to perform a binary addition operation is controlled by the primitive polynomial, where j takes 1, 2.
4. The apparatus for generating pseudo-random sequences of different orders as claimed in claim 3, wherein the primitive polynomial poly [ k ] is]When 1, SnWill output the binary addition result of the input signal, otherwise will Sk+1Is transmitted to the output, where k takes 1, 2.
5. The apparatus of claim 1, wherein the control signal ctrl [ m ] m is asserted when the apparatus is powered on]When 1, the variable length register unit RmExecuting a shift function, otherwise, directly connecting the input and the output; at start-up, the register initial value is loaded by clock edge trigger, after start-up, the shift is performed under the control of clock edge, and each effective edge is shifted by one bit, the above-mentioned ctrl [ m ] is]And represents the m-th bit value of the ctrl signal, wherein m is 0, 2, and n-1.
6. A method for generating pseudo-random sequences of different numbers of levels, the method comprising the steps of:
s1: determining the working number of the shift register units through the length control signal;
s2: loading the initial value of the register in a shift register;
s3: the addition unit is controlled by a primitive polynomial to generateWriting R for next clock1A value of (1);
s4: r is to benThe value of (a) is stored in a memory;
s5: and outputting the pseudo code through a memory.
7. The method for generating pseudo-random sequences of different orders according to claim 6, wherein the memory in step S5 uses a clock domain crossing device, and stores the generated pseudo-code into the memory under high-speed clock; when in use, the pseudo code is read out by the actually needed pseudo code clock.
8. The method of claim 6, wherein the cross-clock domain device performs a write operation when generating the pseudo code, the write clock generates a clock for the pseudo code, the write operation is not performed unless the pseudo code sequence is updated after the write operation is completed, and then the read operation is performed according to the requirement of a subsequent module.
9. The method as claimed in claim 6, wherein the length control signal controls the number of register units to generate different pseudo-code sequences.
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