CN111093319B

CN111093319B - Wiring device and method for transistor

Info

Publication number: CN111093319B
Application number: CN201911296670.1A
Authority: CN
Inventors: 吴一凡; 贾星辰; 方勇; 史良辰
Original assignee: Hefei Yangguang Electric Power Technology Co ltd
Current assignee: Hefei Yangguang Electric Power Technology Co ltd
Priority date: 2019-12-16
Filing date: 2019-12-16
Publication date: 2023-07-28
Anticipated expiration: 2039-12-16
Also published as: CN111093319A

Abstract

The embodiment of the invention discloses a wiring device and a wiring method of a transistor, wherein the device comprises the following steps: the transistor comprises an input lead, an output lead and a control lead which extend in parallel with each other, the laminated bus comprises at least two bus layers which are parallel with each other, the laminated bus is arranged relative to the transistor, and the input lead, the output lead and the control lead of the transistor penetrate through a abdication hole of the laminated bus and are not contacted with the laminated bus; the circuit board is arranged on one side of the laminated bus far away from the transistor in parallel, the via hole of the circuit board corresponds to the abdication hole of the laminated bus, and the input lead, the output lead, the control lead and the lead of the transistor respectively penetrate through the via hole of the circuit board and one or more circuits on the circuit board for welding. According to the embodiment of the invention, the structure of the laminated bus is optimized, so that the processing difficulty and cost of the laminated bus are reduced, the phenomenon that the fusion welding effect is difficult to detect can be avoided by adopting a brazing process, and the maintainability of the transistor wiring device is improved.

Description

Wiring device and method for transistor

Technical Field

The embodiment of the invention relates to the technical field of power converters, in particular to a wiring device and a wiring method of a transistor.

Background

The transistor utilizes the electric signal to control the opening and closing of the transistor, has very high switching speed, and has various functions of detection, rectification, amplification, switching, voltage stabilization, signal modulation and the like. The transistor can be applied to the field of power converters to realize the function of power conversion.

The geometry of the electrical connections of the transistors plays an important role in designing compact high power converters that can be manufactured in an automatic and efficient manner. In the prior art, transistors connected in parallel are connected into corresponding driving circuits respectively in a fusion welding mode to form a power conversion circuit. However, the connection mode needs more welding pins, the manufacturing process is complex, and meanwhile, the welded product has no maintainability and can only control the welding quality by means of process parameter monitoring. In addition, as the pin spacing of the transistor is smaller, glue filling is needed to ensure insulativity after welding, and an extremely high process threshold is needed, so that the manufacturability is lower.

Disclosure of Invention

The embodiment of the invention provides a wiring device and a wiring method of a transistor, which are used for simplifying the wiring process of the transistor and improving the manufacturability under the condition of not increasing the volume of devices and devices.

In a first aspect, an embodiment of the present invention provides a wiring device for a transistor, including: a transistor including an input lead, an output lead, and a control lead extending parallel to each other;

the laminated bus comprises at least two bus layers which are parallel to each other, the laminated bus is arranged relative to the transistor, and an input lead, an output lead and a control lead of the transistor penetrate through a yielding hole of the laminated bus and are not contacted with the laminated bus;

the circuit board is arranged in parallel on one side of the laminated bus away from the transistor, the via hole of the circuit board corresponds to the abdication hole of the laminated bus, and the input lead, the output lead, the control lead and the lead of the laminated bus of the transistor respectively penetrate through the via hole of the circuit board;

and the input lead, the output lead, the control lead and the lead of the laminated bus of the transistor are welded with one or more circuits on the circuit board.

Optionally, the laminated busbar includes a first busbar layer including a first bend lead and a second busbar layer including a second bend lead, the first bend lead including an input lead and an output lead, the second bend lead including an input lead and an output lead.

Optionally, the output lead of the first bending lead and the output lead of the second bending lead are opposite in bending direction.

Optionally, the laminated busbar further includes a third busbar layer, the third busbar layer includes a third bending lead, a bending direction of the third bending lead is perpendicular to a bending direction of the output lead of the first bending lead or the output lead of the second bending lead, and the third bending lead is arranged on the same line with the output lead of the first bending lead and the output lead of the second bending lead on the circuit board;

the laminated bus bar further comprises a first insulating layer and a second insulating layer, wherein the first insulating layer is arranged between the first bus bar layer and the second bus bar layer, and the second insulating layer is arranged between the second bus bar layer and the third bus bar layer.

Optionally, the arrangement sequence of the bending leads of the laminated bus in the preset direction on the circuit board is a third bending lead, an output lead of the first bending lead, an output lead of the second bending lead, or an output lead of the second bending lead, an output lead of the first bending lead and a third bending lead in sequence;

the arrangement sequence of the leads of two adjacent transistors on the circuit board comprises a first arrangement sequence and a second arrangement sequence;

the first arrangement sequence is sequentially an output lead, an input lead and a control lead in the arrangement direction of the bending leads of the laminated bus, and the second arrangement sequence is sequentially a control lead, an input lead and an output lead in the arrangement direction of the bending leads of the laminated bus.

Optionally, the wiring device of the transistor further comprises a capacitor and a capacitor bus, wherein the capacitor is electrically connected with the capacitor bus;

the capacitive bus comprises at least two capacitive bus layers which are parallel to each other, and an output lead of each capacitive bus layer penetrates through a through hole of the circuit board and is welded with the first bending lead and the second bending lead.

Optionally, the capacitor bus is fixedly connected with the laminated bus.

Optionally, the wiring device of the transistor further comprises an insulating support, and the laminated bus bar, the capacitor bus bar and the circuit board are fixed on the insulating support.

Optionally, a copper sheet is arranged on the circuit board, and the copper sheet is welded on the current wiring.

Optionally, the laminated busbar comprises a first abdicating hole, and two sides of the first abdicating hole are respectively provided with a second abdicating hole and a third abdicating hole;

and the lead wires of the laminated bus bar penetrate through the first abdicating hole, and the input lead wires, the output lead wires and the control lead wires of the transistor penetrate through the second abdicating hole and/or the third abdicating hole.

Optionally, the lengths of the input lead, the output lead and the control lead are equal.

In a second aspect, an embodiment of the present invention further provides a method for wiring a transistor, where the method for wiring a transistor includes:

providing a transistor comprising an input lead, an output lead and a control lead extending parallel to each other;

arranging at least two bus layers parallel to each other relative to the transistor to form a laminated bus, and penetrating an input lead, an output lead and a control lead of the transistor through a yielding hole of the laminated bus and not contacting with the laminated bus;

a circuit board is placed in parallel on one side of the laminated bus away from the transistor, a via hole of the circuit board corresponds to a yielding hole of the laminated bus, and an input lead, an output lead, a control lead and a lead of the transistor respectively penetrate through the via hole of the circuit board;

the input leads, output leads, control leads, and leads of the laminated bus bar of the transistor are soldered to one or more circuits on the circuit board.

According to the technical scheme provided by the embodiment of the invention, after the heat dissipation assembly is fixed through the insulating support piece, the transistor, the heat dissipation assembly, the laminated bus and the circuit board are welded into a whole through a brazing process, so that the welding can be completed at one time, the production time of the device is shortened, and the production efficiency is improved. By optimizing the structure of the laminated bus, the processing difficulty of the laminated bus is reduced, and enough gaps and creepage distances are arranged between the input lead, the output lead and the control lead of the transistor and the laminated bus, so that a glue filling process can be omitted, the production process is greatly optimized, and the production cost is reduced. Compared with the prior art, the brazing process can avoid the phenomenon that the fusion welding effect is difficult to detect and the scrapping risk that the device with poor welding cannot be maintained, and is beneficial to improving the maintainability of the transistor wiring device.

Drawings

Fig. 1 is a schematic structural diagram of a wiring device of a transistor according to an embodiment of the present invention;

fig. 2 is an exploded schematic view of a wiring device of a transistor according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a laminated bus bar according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a laminated busbar after hot pressing according to an embodiment of the present invention;

FIG. 5 is an enlarged view of a laminated busbar output lead provided by an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another wiring device of a transistor according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a connection structure between a stacked bus and a transistor lead according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another wiring device of a transistor according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another wiring device of a transistor according to an embodiment of the present invention;

fig. 10 is a flowchart of a wiring method of a transistor according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural diagram of a wiring device of a transistor according to an embodiment of the present invention, and fig. 2 is an exploded structural diagram of a wiring device of a transistor according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, the wiring device of a transistor includes: a transistor 10 including an input lead C, an output lead E, and a control lead G extending parallel to each other;

a laminated bus bar 20, the laminated bus bar 20 including at least two bus bar layers parallel to each other, the laminated bus bar 20 being disposed with respect to the transistor 10, an input lead C, an output lead E, and a control lead G of the transistor 10 penetrating a relief hole 21 of the laminated bus bar 20 and not being in contact with the laminated bus bar 20;

the circuit board 30, the circuit board 30 is placed in parallel on one side of the laminated busbar 20 far away from the transistor 10, the via hole 31 of the circuit board 30 corresponds to the abdication hole 21 of the laminated busbar 20, and the input lead C, the output lead E, the control lead G and the lead of the laminated busbar 20 of the transistor 10 respectively penetrate through the via hole 31 of the circuit board 30;

wherein one or more driving circuits are provided on the circuit board 30, and the input lead C, the output lead E, the control lead G, and the leads of the laminated bus bar 20 of the transistor 10 are soldered to one or more circuits on the circuit board 30.

Specifically, the transistor 10 may be fixed to the heat sink assembly 100 by a spring clip, and the heat sink assembly 100 may be fixed by an insulating support (not shown) when the wiring device of the transistor is assembled. The laminated busbar 20 is arranged on an insulating support, and the input lead C, the output lead E and the control lead G of the transistor 10 all penetrate through the relief hole 21 of the laminated busbar 20. Illustratively, a plurality of transistors 10 are fixed on both sides of each heat dissipation assembly 100, and the input lead C, the output lead E, and the control lead G of each transistor 10 penetrate through the via hole 31 on the circuit board 30 through the corresponding relief hole 21 on the laminated bus 20. The lengths of the input lead C, the output lead E and the control lead G of the transistor 10 are equal, a sufficient gap exists between each lead of the transistor 10 and the laminated bus 20, the leads are not contacted with the abdication holes 21 on the laminated bus 20, the leads of the transistor 10 and the leads of the laminated bus 20 can be welded through a wave soldering or other brazing process at one time, and the welding spot size and the gap required by the fusion welding process are not required to be considered, so that a sufficient electrical gap can be reserved on the laminated bus 20 to ensure good insulation, and insulation is not required to be ensured through a glue filling mode.

The laminated bus bar 20 includes at least two bus bar layers parallel to each other, each bus bar layer is electrically connected to one lead of the transistor 10, at least two bus bar layers parallel to each other are hot pressed to form the laminated bus bar 20, a circuit board 30 is disposed parallel to a side of the laminated bus bar 20 away from the transistor 10, and one or more circuits (not shown in fig. 2) are disposed on the circuit board 30, for example, may be a driving circuit for driving the transistor 10 to operate normally. The input lead C, the output lead E, and the control lead G of the transistor 10 are electrically connected to corresponding circuits through the relief hole 21 of the laminated bus bar 20 and the via hole 31 of the circuit board 30, respectively, so that a transistor wiring device having a plurality of transistor parallel structures can be configured.

According to the technical scheme provided by the embodiment of the invention, the transistor, the heat radiation component, the laminated bus and the circuit board are welded into a whole through a brazing process, and the input lead, the output lead and the control lead of the transistor are provided with enough gaps and creepage distances with the laminated bus, so that a glue filling process can be omitted, the production process is optimized to a great extent, and the production cost is reduced. Compared with the prior art, the brazing process can avoid the phenomenon that the fusion welding effect is difficult to detect and the scrapping risk that the device with poor welding cannot be maintained, and is beneficial to improving the maintainability of the transistor wiring device.

Optionally, fig. 3 is a schematic structural diagram of a laminated busbar according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of a laminated busbar according to an embodiment of the present invention after hot pressing, and referring to fig. 2 and 3, the laminated busbar 20 includes a first busbar layer 210 and a second busbar layer 220, the first busbar layer 210 includes a first bending lead 201, the second busbar layer 220 includes a second bending lead 202, the first bending lead 201 includes an input lead 2011 and an output lead 2012, and the second bending lead 202 includes an input lead 2021 and an output lead 2022.

Specifically, the first bending lead 201 includes an input lead 2011 of the first bus bar layer 210 and an output lead 2012 of the first bus bar layer 210, and the first bending lead 201 may be a positive electrode lead. The second bend lead 202 includes an input lead 2021 of the second bus bar layer 220 and an output lead 2022 of the second bus bar layer 220, and the second bend lead 202 may be a negative lead. Referring to fig. 4, the input lead 2011 of the first bus bar layer 210 and the input lead 2021 of the second bus bar layer 220 may be disposed at the outer edge of the laminated bus bar 20, and bent toward the side of the laminated bus bar 20 away from the transistor, and serve as a power supply voltage input positive terminal of the transistor, so as to facilitate connection with an external power supply.

Optionally, with continued reference to fig. 3 and 4, the output lead 2012 of the first bend lead 201 and the output lead 2022 of the second bend lead 202 are bent in opposite directions based on the above-described embodiments.

Specifically, the output lead 2012 of the first bus bar layer 210 and the output lead 2022 of the second bus bar layer 220 penetrate through the relief hole 21 of the laminated bus bar 20 to serve as the output negative terminal of the transistor, and the bending directions of the output lead 2012 of the first bus bar layer 210 and the output lead 2022 of the second bus bar layer 220 are opposite, so that the first bus bar layer 210 and the second bus bar layer 220 can be ensured to have the smallest non-laminated area, and stray inductance on the laminated bus bar 20 can be reduced.

Optionally, with continued reference to fig. 3 and 4, in addition to the above embodiment, the laminated busbar 20 further includes a third busbar layer 230, the third busbar layer 230 includes a third bending lead 203, a bending direction of the third bending lead 203 is perpendicular to a bending direction of the output lead 2012 of the first bending lead 201 or the output lead 2022 of the second bending lead 202, and the third bending lead 203 is aligned on the same line with the output lead 2012 of the first bending lead 201 and the output lead 2022 of the second bending lead 202 on the circuit board;

the laminated bus bar 20 further includes a first insulating layer 240 and a second insulating layer 250, the first insulating layer 240 being disposed between the first bus bar layer 210 and the second bus bar layer 220, and the second insulating layer 250 being disposed between the second bus bar layer 220 and the third bus bar layer 230.

Specifically, the third bus layer 230 may be an ac bus layer, and in an application scenario such as a bridge-type power converter, an ac voltage may be output through the third bent lead 203 of the third bus layer 230. Fig. 5 is an enlarged view of a laminated busbar output lead provided in an embodiment of the present invention, referring to fig. 5, in which the third bending lead 203 is only used as an output lead, aligned with the output lead 2012 of the first bending lead 201 and the output lead 2022 of the second bending lead 202 on the circuit board, and the bending direction thereof is perpendicular to the bending direction of the output lead 2012 of the first bending lead 201 or the output lead 2012 of the second bending lead 202, and the bending direction of the output lead 2012 of the first bending lead 201 and the output lead 2022 of the second bending lead 202 are opposite to each other, that is, the output lead 2012 of the first bending lead 201 is bent in the X direction and the third bending lead 203 is bent in the Y direction, so that the wiring device of the transistor can be minimized, and the non-laminated area of the first busbar layer 210 and the second busbar layer 220 can be ensured to be minimized, thereby being beneficial to reducing the stray inductance of the laminated busbar 20; and the bending direction of the third bending lead 203 is perpendicular to the bending direction of the output lead 2012 of the first bending lead 201 or the output lead 2022 of the second bending lead 202, so that the width of the third bending lead 203 can be increased under the condition that three bending leads are arranged on the same straight line, and the overcurrent capacity of the third bending lead 203 can be enhanced.

In addition, the first insulating layer 240 is provided between the first bus bar layer 210 and the second bus bar layer 220, and the second insulating layer 250 is provided between the second bus bar layer 220 and the third bus bar layer 230, so that insulation between two adjacent bus bar layers can be enhanced, and the laminated bus bar 20 can be prevented from being shorted. After the first bus bar layer 210, the first insulating layer 240, the second bus bar layer 220, the second insulating layer 250 and the third bus bar layer 230 are subjected to hot pressing treatment, the laminated bus bar 20 shown in fig. 4 is formed, and compared with the prior art, the number of bending leads of the laminated bus bar 20 is greatly reduced, so that the processing difficulty of the laminated bus bar 20 is reduced.

Optionally, fig. 6 is a schematic structural diagram of another wiring device for a transistor according to an embodiment of the present invention, fig. 7 is a schematic structural diagram of a connection structure between a laminated bus bar and a transistor lead according to an embodiment of the present invention, and on the basis of the above embodiment, referring to fig. 6 and fig. 7, an arrangement order of the bent leads of the laminated bus bar 20 along a preset direction on the circuit board 30 is a third bent lead 203, an output lead 2012 of the first bent lead 201, an output lead 2022 of the second bent lead 202, or an output lead 2022 of the second bent lead 202, an output lead 2012 of the first bent lead 201, and a third bent lead 203 in sequence;

the arrangement order of the leads of the adjacent two transistors 10 on the circuit board 30 includes a first arrangement order and a second arrangement order;

the first arrangement order is an output lead E, an input lead C, and a control lead G in order in the arrangement direction of the bent leads of the laminated bus bar 20, and the second arrangement order is a control lead G, an input lead C, and an output lead E in order in the arrangement direction of the bent leads of the laminated bus bar 20.

In particular, as regards the arrangement of the bent leads of the laminated busbar 20 on the circuit board 30, it is possible to derive different arrangements, viewed from different angles. The embodiment of the present invention illustrates the arrangement sequence of the bent leads of the laminated bus 20 on the circuit board 30 by taking the preset direction as the direction indicated by the arrow in fig. 7, however, in other embodiments, the preset direction may be other directions. As illustrated in fig. 6 and 7, after the transistor 10 and the laminated busbar 20 are fixed together, the output leads of the laminated busbar 20 are sequentially a third bent lead 203, an output lead 2012 of the first bent lead 201, and an output lead 2022 of the second bent lead 202 in the order of the arrow direction, and a group of output leads is formed, the third bent lead 203 may be an ac lead of the laminated busbar 20, the output lead 2012 of the first bent lead 201 may be a positive lead of the laminated busbar 20, and the output lead 2022 of the second bent lead 202 may be a negative lead of the laminated busbar 20. After placement of the circuit board 30 on the side of the laminated busbar 20 remote from the transistor 10, the leads and output lead sets of the transistor 10 extend through the vias 31 of the circuit board 30. The power conversion circuit comprises an output lead group, a group of transistors 10 arranged on two sides of the output lead group, a group of transistors 10 arranged above the output lead group and a group of transistors 10 arranged below the output lead group, wherein the group of transistors 10 is called an upper bridge arm transistor, the upper bridge arm transistor and the lower bridge arm transistor form a parallel structure through the output lead group, and the upper bridge arm transistor and the lower bridge arm transistor are connected in a lap joint mode to form the power conversion circuit. For example, the control leads G of the upper bridge arm transistor and the lower bridge arm transistor are each electrically connected to a driving circuit on the circuit board 30 to drive the transistors on or off; the input lead C of the upper leg transistor is electrically connected to the output lead 2012 of the first bent lead 201, the output lead E of the upper leg transistor is electrically connected to the third bent lead 203, the output lead E of the lower leg transistor is electrically connected to the output lead 2022 of the second bent lead 202, and the input lead C of the lower leg transistor is electrically connected to the third bent lead 203. That is, according to the principle of parallel connection of transistor single tubes, the current flow direction after the upper bridge arm transistor and the lower bridge arm transistor are connected in parallel is as follows: first bent bus 201 (positive electrode of laminated bus 20) -input lead of upper arm transistor C-output lead of upper arm transistor E-third bent bus 203 (ac output of laminated bus 20) -input lead of lower arm transistor C-output lead of lower arm transistor E-second bent lead 202 (negative electrode of laminated bus 20). The advantage of setting the connection mode of the leads of the transistor is that the lengths of the positive electrode line and the negative electrode line of the laminated bus 20 are equal, the total length of the positive electrode line, the negative electrode line and the alternating current output line is shortest, the influence of parasitic parameters of the lines on the switching characteristic of the transistor is reduced to the greatest extent, and the power density of the whole circuit system is improved.

Optionally, fig. 8 is a schematic structural diagram of another wiring device for a transistor according to an embodiment of the present invention, and referring to fig. 8, on the basis of the above embodiment, the wiring device for a transistor further includes a capacitor 40 and a capacitor bus 410, where the capacitor 40 is electrically connected to the capacitor bus 410;

the capacitive busbar 410 comprises at least two capacitive busbar layers parallel to each other, the output lead 401 of each capacitive busbar layer extending through the via 31 of the circuit board 30 and being soldered to the first bent lead 201 and the second bent lead 202.

Specifically, the capacitor 40 may be a supporting capacitor between the first bending lead 201 and the second bending lead 202, and is used for absorbing the high-amplitude pulsating current and the high-amplitude pulsating voltage generated by the first bending lead 201 and the second bending lead 202, so as to prevent the transistor 10 from being irreversibly damaged by transient overvoltage and overcurrent. The output lead 401 of the capacitor bus layer penetrates through the via hole 31 on the circuit board 30 to be electrically connected with a circuit on the circuit board 30, and the capacitor bus is fixedly connected with the laminated bus 20. Illustratively, the output leads 401 of the capacitive buss layer may be soldered with the input leads 2011 of the first buss layer 210 and the input leads 2021 of the second buss layer 220 through the vias 31 of the circuit board 30. Of course, the capacitor bus bar and the laminated bus bar 20 may be directly connected by screws. The capacitor bus layer is vertically arranged on the capacitor 40 and fixedly connected with the laminated bus 20 through a screw, and meanwhile, the first bending lead 201 of the first bus layer 210 of the laminated bus 20 and the second bending lead 202 of the second bus layer 220 can also be arranged to be mutually matched, so that the arrangement has the advantages of reducing the occupied space of high-voltage devices on the circuit board 30, being beneficial to optimizing the layout of the circuit board 30 and reducing the size of the circuit board.

Optionally, with continued reference to fig. 8, the wiring device of the transistor further includes an insulating support on which the laminated bus bar 20, the capacitor 40, the capacitor bus bar 410, and the circuit board 30 are fixed, in accordance with the above-described embodiment.

Specifically, the transistor 10 may be fixed on the heat dissipation assembly 100, and the laminated bus bar 20 is disposed on the insulating support, where the input lead C, the output lead E, and the control lead G of the transistor 10 all penetrate through the relief hole 21 of the laminated bus bar 20.

Wherein, the laminated busbar 20 includes a first relief hole 211, and two sides of the first relief hole 211 are respectively provided with a second relief hole 212 and a third relief hole 213; the leads of the laminated bus bar 20 extend through the first relief hole 211, and the input lead C, the output lead E, and the control lead G of the transistor 10 extend through the second relief hole 212 and/or the third relief hole 213. For example, referring to fig. 2 and 4, the output lead 2012 of the first bus layer 210, the output lead 2022 of the second bus layer 220, and the third bent lead 203 of the laminated bus 20 penetrate through the first relief hole 211 on the laminated bus 20, where the first bus layer 210, the second bus layer 220, and the third bus layer 230 are respectively provided with a relief hole corresponding to the first relief hole 211, and after the three bus layers are subjected to hot pressing, the corresponding relief holes on the three bus layers together form the first relief hole 211. Since the overcurrent conditions of the output lead 2012 of the first bus bar layer 210, the output lead 2022 of the second bus bar layer 220, and the third bent lead 203 are not completely identical, the third bent lead 203 can be isolated from the output lead 2012 of the first bus bar layer 210 and the output lead 2022 of the second bus bar layer 220, and short circuits caused by mutual contact of the three leads in the actual operation process can be prevented. Three leads of the upper bridge arm transistor penetrate through the second abdicating hole 212, and three leads of the lower bridge arm transistor penetrate through the third abdicating hole 213, so that virtual connection of the upper bridge arm and the lower bridge arm transistor leads can be effectively prevented.

Optionally, fig. 9 is a schematic structural diagram of another wiring device for a transistor according to an embodiment of the present invention, and referring to fig. 9, a copper sheet 32 is disposed on a circuit board 30, and the copper sheet 32 is soldered on a current trace.

Specifically, because the current-carrying capability of the circuit board 30 is limited, when the power density of the transistor is high, the current on the circuit board 30 is excessively large to generate a large amount of heat, so that the device always works in a high-temperature environment and is easy to burn. Therefore, the copper sheet 32 is disposed on the current trace of the circuit board 30, so that the overcurrent capacity of the circuit board 30 can be increased, the heat dissipation area can be increased, and the local temperature rise of the circuit board 30 can be effectively reduced.

According to the technical scheme provided by the embodiment of the invention, the transistor, the capacitor, the laminated bus and the circuit board are welded into a whole through the insulating support piece by a brazing process, so that the welding can be completed at one time, the production time of the device is shortened, and the production efficiency is improved. Compared with the prior art, the brazing process can avoid the phenomenon that the fusion welding effect is difficult to detect and the scrapping risk that the device with poor welding cannot be maintained, and is beneficial to improving the maintainability of the transistor wiring device. In addition, through optimizing the structure of laminated bus, the quantity of bending leads of each bus layer is reduced, the processing difficulty of laminated bus is reduced, and sufficient gaps and creepage distances are arranged between the input leads, the output leads and the control leads of the transistor and the laminated bus, so that a glue filling process can be omitted, the production process is optimized to a great extent, and the production cost is reduced.

The embodiment of the invention also provides a wiring method of the transistor, referring to fig. 10, fig. 10 is a flowchart of the wiring method of the transistor, where the method includes:

step 610, providing a transistor including an input lead, an output lead, and a control lead extending parallel to each other.

Step 620, at least two bus layers parallel to each other are disposed relative to the transistor to form a laminated bus, and the input lead, the output lead and the control lead of the transistor are inserted through the relief holes of the laminated bus and are not in contact with the laminated bus.

And 630, placing a circuit board in parallel on one side of the laminated bus far from the transistor, wherein the via hole of the circuit board corresponds to the abdication hole of the laminated bus, and respectively penetrating the input lead, the output lead, the control lead and the lead of the laminated bus of the transistor through the via hole of the circuit board.

Step 640, soldering the input leads, output leads, control leads, and leads of the laminated bus bar of the transistor to one or more circuits on the circuit board by soldering.

The wiring method of the transistor provided by the embodiment of the invention is used for completing the wiring device of the transistor provided by the embodiment, so that the wiring method of the transistor provided by the embodiment of the invention has the beneficial effects described in the embodiment.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A wiring device of a transistor, comprising:

a transistor including an input lead, an output lead, and a control lead extending parallel to each other;

wherein, one or more circuits are arranged on the circuit board, and the input lead, the output lead, the control lead and the lead of the laminated bus of the transistor are welded with one or more circuits on the circuit board;

the laminated busbar comprises a first busbar layer and a second busbar layer, the first busbar layer comprises a first bending lead, the second busbar layer comprises a second bending lead, the first bending lead comprises an input lead and an output lead, and the second bending lead comprises an input lead and an output lead;

the output lead of the first bending lead and the output lead of the second bending lead are opposite in bending direction.

2. The wiring device of a transistor according to claim 1, wherein the laminated bus bar further comprises a third bus bar layer including a third bending lead having a bending direction perpendicular to a bending direction of the output lead of the first bending lead or the output lead of the second bending lead, the third bending lead being aligned on the same line as the output lead of the first bending lead and the output lead of the second bending lead on the circuit board.

3. The wiring device of a transistor of claim 2, wherein the laminated bus bar further comprises a first insulating layer and a second insulating layer, the first insulating layer disposed between the first bus bar layer and the second bus bar layer, the second insulating layer disposed between the second bus bar layer and the third bus bar layer.

4. The wiring device of a transistor according to claim 2, wherein the arrangement order of the bent leads of the laminated bus bar in the predetermined direction on the circuit board is a third bent lead, an output lead of the first bent lead, an output lead of the second bent lead, or an output lead of the second bent lead, an output lead of the first bent lead, a third bent lead;

5. The wiring device of a transistor according to claim 1, further comprising a capacitor and a capacitor bus, the capacitor being electrically connected to the capacitor bus;

6. The transistor wiring device according to claim 5, wherein the capacitor bus bar is fixedly connected to the laminated bus bar.

7. The transistor wiring device of claim 6, further comprising an insulating support, wherein the laminated bus bar, the capacitor bus bar, and the circuit board are fixed to the insulating support.

8. The transistor wiring device of claim 1, wherein the circuit board is provided with a copper sheet, and wherein the copper sheet is soldered to the current trace.

9. The wiring device of a transistor according to claim 1, wherein the laminated bus bar includes a first relief hole, and a second relief hole and a third relief hole are respectively provided on both sides of the first relief hole;

10. The wiring device of a transistor according to any one of claims 1 to 9, wherein lengths of the input lead, the output lead, and the control lead are equal.

11. A wiring method of a transistor, comprising:

soldering the input leads, the output leads, the control leads, and the leads of the laminated bus bar of the transistor to one or more circuits on the circuit board by soldering;