CN219371020U - Power module and apparatus - Google Patents

Abstract

The utility model discloses a power module and equipment, wherein the power module comprises an upper bridge substrate, a lower bridge substrate, an upper bridge power chip and a lower bridge power chip, the upper bridge substrate comprises an upper bridge top substrate and an upper bridge bottom substrate, and the upper bridge top substrate and the upper bridge bottom substrate are oppositely arranged; the lower bridge substrate comprises a lower bridge top substrate and a lower bridge bottom substrate, and the lower bridge top substrate and the lower bridge bottom substrate are oppositely arranged; the upper bridge power chip comprises a first chip arranged on one surface of the upper bridge top substrate, which faces the upper bridge bottom substrate, and a second chip arranged on one surface of the upper bridge bottom substrate, which faces the upper bridge top substrate; the lower bridge power chip comprises a third chip arranged on one surface of the lower bridge top substrate facing the lower bridge bottom substrate and a fourth chip arranged on one surface of the lower bridge bottom substrate facing the lower bridge top substrate.

Description

Power module and apparatus

Technical Field

The present utility model relates to the field of power modules, and in particular, to a power module and a device.

Background

In the prior art, when a power module with a single plane structure is conducted, larger overshoot voltage is easy to cause, the problems of increased chip switching loss and the like exist, the reliability of the power module is low, and the service life of the power module is easy to influence.

Disclosure of Invention

The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, an object of the present utility model is to provide a power module, which can reduce the inductance of the power current loop, is not easy to cause large overcharge voltage, reduces the switching loss of the chip, and improves the reliability and service life of the power module.

Another object of the utility model is to propose a device.

In order to achieve the above object, a power module according to an embodiment of a first aspect of the present utility model includes: the upper bridge substrate comprises an upper bridge top substrate and an upper bridge bottom substrate, and the upper bridge top substrate and the upper bridge bottom substrate are oppositely arranged; the lower bridge substrate comprises a lower bridge top substrate and a lower bridge bottom substrate, and the lower bridge top substrate and the lower bridge bottom substrate are oppositely arranged; the upper bridge power chip comprises a first chip and a second chip which are connected with each other, the first chip is arranged on one surface of the upper bridge top substrate facing the upper bridge bottom substrate, and the second chip is arranged on one surface of the upper bridge bottom substrate facing the upper bridge top substrate; the lower bridge power chip comprises a third chip and a fourth chip which are connected with each other, wherein the third chip is arranged on one surface of the lower bridge top substrate facing the lower bridge bottom substrate, and the fourth chip is arranged on one surface of the lower bridge bottom substrate facing the lower bridge top substrate.

According to the power module provided by the embodiment of the utility model, the first chip and the second chip are respectively arranged on the upper bridge top substrate and the upper bridge bottom substrate of the upper bridge substrate, the third chip and the fourth chip are respectively arranged on the lower bridge top substrate and the lower bridge bottom substrate of the lower bridge substrate, and the upper bridge top substrate and the upper bridge bottom substrate are oppositely arranged, and the lower bridge top substrate and the lower bridge bottom substrate are oppositely arranged.

In some embodiments of the present utility model, the upper bridge substrate is located on one side of the lower bridge substrate, the upper bridge top substrate is disposed in side-to-side alignment with the lower bridge top substrate, and the upper bridge bottom substrate is disposed in side-to-side alignment with the lower bridge bottom substrate.

In some embodiments of the utility model, the upper bridge top substrate, the upper bridge bottom substrate, the lower bridge top substrate, and the lower bridge bottom substrate each comprise a bottom plate, an insulating layer, and a metal layer, the bottom plate, the insulating layer, and the metal layer being stacked.

In some embodiments of the utility model, the power module further comprises: the front shell is positioned at the front sides of the upper bridge substrate and the lower bridge substrate, the upper end of the front shell is connected with the upper bridge top substrate and the lower bridge top substrate, and the lower end of the front shell is connected with the upper bridge bottom substrate and the lower bridge bottom substrate; the rear shell is positioned at the rear sides of the upper bridge substrate and the lower bridge substrate, the upper end of the rear shell is connected with the upper bridge top substrate and the lower bridge top substrate, and the lower end of the rear shell is connected with the upper bridge bottom substrate and the lower bridge bottom substrate.

In some embodiments of the utility model, an edge of the bottom plate of the upper bridge top substrate grows out of an edge of the insulating layer of the upper bridge top substrate to form a first step, and an edge of the bottom plate of the lower bridge top substrate grows out of an edge of the insulating layer of the lower bridge top substrate to form a second step; the edge of the bottom plate of the upper bridge bottom substrate is longer than the edge of the edge layer of the upper bridge bottom substrate to form a third step, and the edge of the bottom plate of the lower bridge bottom substrate is longer than the edge of the edge layer of the lower bridge bottom substrate to form a fourth step; the upper end of the front shell is erected on the first step and the second step, the lower end of the front shell is erected on the third step and the fourth step, the upper end of the rear shell is erected on the first step and the second step, and the lower end of the rear shell is erected on the third step and the fourth step.

In some embodiments of the present utility model, the drain electrode of the first chip is disposed on the metal layer of the upper bridge top substrate, the drain electrode of the second chip is disposed on the metal layer of the upper bridge bottom substrate, the drain electrode of the third chip is disposed on the metal layer of the lower bridge top substrate, and the drain electrode of the fourth chip is disposed on the metal layer of the lower bridge bottom substrate.

In some embodiments of the present utility model, a first bridging metal layer is further disposed on the insulating layer of the lower bridge top substrate and separated from the metal layer of the lower bridge top substrate, and the first bridging metal layer is located on a side of the lower bridge top substrate close to the upper bridge top substrate, and the first bridging metal layer is connected to the source electrode of the third chip.

In some embodiments of the utility model, the power module further comprises: a DC power terminal connected with the first chip and the third chip, and an AC power terminal connected with the second chip and the fourth chip.

In some embodiments of the utility model, the DC power terminal comprises: one end of the DC positive electrode terminal is connected with the metal layer of the upper bridge top substrate; and a DC negative electrode terminal, one end of which is connected with the first bridging metal layer.

In some embodiments of the utility model, the other end of the DC positive terminal and the other end of the DC negative terminal are bent, and the other end of the DC positive terminal and the other end of the DC negative terminal are led out from between the upper bridge top substrate and the lower bridge top substrate.

In some embodiments of the utility model, the power module further comprises: the first middle shell is arranged between the upper bridge top substrate and the lower bridge top substrate, a first DC terminal leading-out hole and a second DC terminal leading-out hole are formed in the first middle shell, the other end of the DC positive terminal is led out from the first DC terminal leading-out hole, and the other end of the DC negative terminal is led out from the second DC terminal leading-out hole.

In some embodiments of the present utility model, a second bridging metal layer is disposed on the insulating layer of the upper bridge bottom substrate and separated from the metal layer of the upper bridge bottom substrate, the second bridging metal layer is located on a side of the upper bridge bottom substrate close to the lower bridge bottom substrate, and the second bridging metal layer is connected to the source electrode of the second chip.

In some embodiments of the utility model, the AC power terminal comprises: a first AC terminal having one end connected to the second bridging metal layer; and one end of the second AC terminal is connected with the metal layer of the lower bridge bottom substrate.

In some embodiments of the utility model, the other end of the first AC terminal and the other end of the second AC terminal are bent, and the other end of the first AC terminal and the other end of the second AC terminal are led out from below between the upper bridge bottom substrate and the lower bridge bottom substrate.

In some embodiments of the utility model, the power module further comprises: the second middle shell is arranged between the upper bridge bottom substrate and the lower bridge bottom substrate, a first AC terminal leading-out hole and a second AC terminal leading-out hole are formed in the second middle shell, the other end of the first AC terminal is led out from the first AC terminal leading-out hole, and the other end of the second AC terminal is led out from the second AC terminal leading-out hole.

In some embodiments of the present utility model, the metal layer of the upper bridge top substrate, the metal layer of the upper bridge bottom substrate, the metal layer of the lower bridge top substrate, and the metal layer of the lower bridge bottom substrate each include a chip conductive region and a signal transmission region that are separated, and the power chips are respectively disposed in the corresponding chip conductive regions; the power module further comprises signal terminals respectively arranged on the upper bridge top substrate, the upper bridge bottom substrate, the lower bridge top substrate and the lower bridge bottom substrate, one ends of the signal terminals are connected with corresponding signal transmission areas, and the other ends of the signal terminals are led out from the corresponding substrates.

In some embodiments of the present utility model, a gate signal extraction hole and a source signal extraction hole are provided on each substrate; the signal transmission area comprises a grid signal transmission area and a source signal transmission area, the grid signal transmission area is connected with a grid of a power chip arranged on the same substrate, and the source signal transmission area is connected with a source of the power chip arranged on the same substrate; the signal terminals comprise gate signal terminals and source signal terminals, one ends of the gate signal terminals are connected with the corresponding gate signal transmission areas, the other ends of the gate signal terminals are led out from the gate signal leading-out holes, one ends of the source signal terminals are connected with the corresponding source signal transmission areas, and the other ends of the source signal terminals are led out from the source signal leading-out holes.

In some embodiments of the present utility model, the first chip, the second chip, the third chip, and the fourth chip each include a plurality of power chips distributed in chip conductive regions of a corresponding substrate; the signal transmission area is positioned at the central position of the corresponding substrate, and the chip conductive area surrounds the signal transmission area.

In some embodiments of the utility model, the power module further comprises: the upper bridge connection metal block is positioned on one side of the upper bridge substrate, which is far away from the lower bridge substrate, one end of the upper bridge connection metal block is connected with the source electrode of the first chip, and the other end of the upper bridge connection metal block is connected with the source electrode of the second chip.

In some embodiments of the utility model, the upper bridge substrate further comprises: the upper bridge side substrate is arranged on one side, far away from the lower bridge substrate, of the upper bridge substrate and is connected with the upper bridge top substrate and the upper bridge bottom substrate, the upper bridge side substrate comprises an insulating layer and a metal layer, the insulating layer and the metal layer are arranged in a laminated manner, and the metal layer of the upper bridge side substrate is connected with the metal layer of the upper bridge top substrate and the metal layer of the upper bridge bottom substrate; the upper bridge side surface substrate is positioned at the outer side of the upper bridge connecting metal block, and a space is reserved between the metal layer of the upper bridge side surface substrate and the upper bridge connecting metal block.

In some embodiments of the utility model, the power module further comprises: the left shell is arranged on the outer side of the upper bridge side surface substrate and is connected with the front shell and the rear shell respectively.

In some embodiments of the utility model, the power module further comprises: the lower bridge connection metal block is positioned on one side, far away from the upper bridge substrate, of the lower bridge substrate, one end of the lower bridge connection metal block is connected with the source electrode of the third chip, and the other end of the lower bridge connection metal block is connected with the source electrode of the fourth chip.

In some embodiments of the utility model, the lower bridge substrate further comprises: the lower bridge side substrate is arranged on one side, far away from the upper bridge substrate, of the lower bridge substrate and is connected with the lower bridge top substrate and the lower bridge bottom substrate, the lower bridge side substrate comprises an insulating layer and a metal layer, the insulating layer and the metal layer are arranged in a laminated manner, and the metal layer of the lower bridge side substrate is connected with the metal layer of the lower bridge top substrate and the metal layer of the lower bridge bottom substrate; the lower bridge side substrate is positioned at the outer side of the lower bridge connecting metal block, and a space is reserved between the metal layer of the lower bridge side substrate and the lower bridge connecting metal block.

In some embodiments of the utility model, the power module further comprises: the right shell is arranged on the outer side of the lower bridge side surface substrate and is respectively connected with the front shell and the rear shell.

In some embodiments of the utility model, an insulating gel is encapsulated in the gap inside the power module.

In order to achieve the above object, an embodiment of a second aspect of the present utility model proposes an apparatus comprising a power module as described in any one of the above.

According to the device provided by the embodiment of the utility model, the power module of the embodiment can reduce the power current loop inductance, so that large overcharge voltage is not easy to cause, the chip switching loss is reduced, and the reliability and the service life of the device are improved.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The foregoing and/or additional aspects and advantages of the present utility model will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a power module according to one embodiment of the utility model;

FIG. 2 is a schematic diagram of a power module according to one embodiment of the utility model;

FIG. 3 is a schematic diagram of a portion of a power module according to one embodiment of the utility model;

FIG. 4 is a schematic diagram of a portion of a power module according to another embodiment of the utility model;

FIG. 5 is a schematic diagram of a portion of a power module according to yet another embodiment of the utility model;

FIG. 6 is a schematic diagram of a power module according to another embodiment of the utility model;

FIG. 7 is a block diagram of a power module according to another embodiment of the utility model;

FIG. 8 is a schematic diagram of a power module according to yet another embodiment of the utility model;

fig. 9 is a block diagram of an apparatus according to one embodiment of the utility model.

Reference numerals:

the apparatus 100;

a power module 10;

an upper bridge substrate 1, a lower bridge substrate 2, an upper bridge power chip 3, a lower bridge power chip 4, a DC power terminal 5, an AC power terminal 6, an upper bridge connection metal block 7, a lower bridge connection metal block 8, a front case 91, a first intermediate case 93, a second intermediate case 94, a left case 95, and a right case 96;

an upper bridge top substrate 11, an upper bridge bottom substrate 12, an upper bridge side substrate 13, a lower bridge top substrate 21, a lower bridge bottom substrate 22, a lower bridge side substrate 23, a first chip 31, a second chip 32, a third chip 41, a fourth chip 42, a DC positive terminal 51, a DC negative terminal 52, a first AC terminal 61, a second AC terminal 62;

The semiconductor device comprises a bottom plate A, an insulating layer B, a metal layer C, a first metal block E, a second metal block F, a first bridging metal layer C1, a second bridging metal layer C2, a chip conducting region M, a signal transmission region N, a gate signal transmission region N1, a source signal transmission region N2, a gate signal extraction hole N1, a source signal extraction hole N2, a signal terminal P, a gate signal terminal P1 and a source signal terminal P2.

Detailed Description

Embodiments of the present utility model are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary, and power modules of embodiments of the present utility model are described in detail below with reference to fig. 1-8.

In some embodiments of the present utility model, as shown in fig. 1, a block diagram of a power module according to an embodiment of the present utility model is shown, wherein a power module 10 includes an upper bridge substrate 1, a lower bridge substrate 2, an upper bridge power chip 3, and a lower bridge power chip 4.

The structure of the various parts of the power module 10 of an embodiment of the present utility model may be understood below in conjunction with fig. 2-5. FIG. 2 is a schematic diagram of a power module according to one embodiment of the utility model; FIG. 3 is a schematic diagram of a portion of a power module according to one embodiment of the utility model; FIG. 4 is a schematic diagram of a portion of a power module according to another embodiment of the utility model; fig. 5 is a schematic diagram of a portion of a power module according to yet another embodiment of the utility model.

As shown in fig. 2, the upper bridge substrate 1 includes an upper bridge top substrate 11 and an upper bridge bottom substrate 12, the upper bridge top substrate 11 and the upper bridge bottom substrate 12 being disposed opposite to each other. The lower bridge substrate 2 includes a lower bridge top substrate 21 and a lower bridge bottom substrate 22, and the lower bridge top substrate 21 and the lower bridge bottom substrate 22 are disposed opposite to each other.

The upper bridge substrate 1 and the lower bridge substrate 2 are not provided on one substrate, the upper bridge top substrate 11 and the upper bridge bottom substrate 12 are divided into two substrates, and the lower bridge top substrate 21 and the lower bridge bottom substrate 22 are also divided into two substrates and are provided opposite to each other, that is, the upper bridge top substrate 11 and the upper bridge bottom substrate 12 are placed in a stacked state, and the lower bridge top substrate 21 and the lower bridge bottom substrate 22 are placed in a stacked state, and when the upper bridge circuit and the lower bridge circuit are conducted, a current flows from the upper bridge top substrate 11 to the upper bridge bottom substrate 12, that is, a current direction in the upper bridge top substrate 11 is opposite to a current direction in the upper bridge bottom substrate 12, and when a current flows from the lower bridge bottom substrate 22 to the lower bridge top substrate 21, a current direction in the lower bridge bottom substrate 22 and a current direction in the lower bridge top substrate 21 are also opposite. By adopting the design structure, the circuits in the whole power module 10 can have reverse current structures in the upper bridge substrate 1 and the lower bridge substrate 2 in the working process, and magnetic fields generated by reverse currents can be mutually coupled, so that the power module 10 has mutual inductance offset effect, and the inductance of the whole power module 10 can be reduced.

In some embodiments of the present utility model, the upper bridge substrate 1 is located on one side of the lower bridge substrate 2 and the upper bridge top substrate 11 is disposed side-to-side with the lower bridge top substrate 21 and the upper bridge bottom substrate 12 is disposed side-to-side with the lower bridge bottom substrate 22.

Further, the upper bridge top substrate 11, the upper bridge bottom substrate 12, the lower bridge top substrate 21, and the lower bridge bottom substrate 22 each include a bottom plate a, an insulating layer B, and a metal layer C, wherein the bottom plate a, the insulating layer B, and the metal layer C are stacked. Wherein, the bottom plate A is positioned on the outermost layer and can be a copper bottom plate with a certain thickness, and the surface area of the bottom plate A is the same as that of the insulating layer B, so that the bottom plate A can be used for heat dissipation; the insulating layer B is positioned in the middle layer and can be used for isolating the bottom plate A from the metal layer C; the metal layer C is positioned at the innermost layer and can be used for conducting electricity and radiating heat.

As shown in fig. 1 and 2, the upper bridge power chip 3 includes a first chip 31 and a second chip 32 connected to each other, the first chip 31 being disposed on a side of the upper bridge top substrate 11 facing the upper bridge bottom substrate 12, and the second chip 32 being disposed on a side of the upper bridge bottom substrate 12 facing the upper bridge top substrate 11. That is, chips are provided on both the upper bridge substrate 1 and the lower bridge substrate 2, and the upper bridge power chip 3 and the lower bridge power chip 4 are provided on opposite surfaces of the upper bridge substrate 1 and the lower bridge substrate 2, respectively.

Specifically, as shown in fig. 2, the drain electrode of the first chip 31 is erected on the metal layer C of the upper bridge top substrate 11, and the drain electrode of the second chip 32 is erected on the metal layer C of the upper bridge bottom substrate 12, so that the side of the first chip 31 and the second chip 32 contacting the metal layer C is the drain electrode of the chip, and the side opposite to the drain electrode is the source electrode of the chip. The lower bridge power chip 4 includes a third chip 41 and a fourth chip 42 connected to each other, the third chip 41 being disposed on a side of the lower bridge top substrate 21 facing the lower bridge bottom substrate 22, the fourth chip 42 being disposed on a side of the lower bridge bottom substrate 22 facing the lower bridge top substrate 21. The drain of the third chip 41 is built up on the metal layer C of the lower bridge top substrate 21 and the drain of the fourth chip 42 is built up on the metal layer C of the lower bridge bottom substrate 22. In the same manner as the first chip 31 and the second chip 32, the side of the third chip 41 and the fourth chip 42, which is in contact with the metal layer C, is the drain of the chip, the side opposite to the drain is the source of the chip, and when the power module 10 is turned on, current flows in from the drain of the chip and flows out from the source of the chip. In addition, in die attachment, the die may be directly sintered on the metal layer C.

According to the power module 10 provided by the embodiment of the utility model, the first chip 31 and the second chip 32 are respectively arranged on the upper bridge top substrate 11 and the upper bridge bottom substrate 12 of the upper bridge substrate 1, and the third chip 41 and the fourth chip 42 are respectively arranged on the lower bridge top substrate 21 and the lower bridge bottom substrate 22 of the lower bridge substrate 2, and by arranging the upper bridge top substrate 11 and the upper bridge bottom substrate 12 opposite to each other and arranging the lower bridge top substrate 21 and the lower bridge bottom substrate 22 opposite to each other, when the chips are conducted, current flows through the first chip 31 and the second chip 32 in the upper bridge substrate 1, and current flows through the third chip 41 and the fourth chip 42 in the lower bridge substrate 2, so that reverse currents exist in the upper bridge substrate 1 and the lower bridge substrate 2, two reverse currents exist in the power module 10, magnetic fields generated by the reverse currents are mutually coupled, and therefore, the inductance of a power current loop is reduced, the large overcharge voltage is not easy to cause, the switching loss of the chips is reduced, and the reliability and the service life of the power module 10 is improved.

In some embodiments of the present utility model, as shown in fig. 6, a schematic diagram of a power module according to another embodiment of the present utility model is shown. The power module 10 further comprises a front housing 91 and a rear housing, wherein the rear housing is not shown in the figures.

The front case 91 is located at the front side of the upper and lower bridge substrates 1 and 2, the upper end of the front case 91 is connected to the upper and lower bridge top substrates 11 and 21, and the lower end of the front case 91 is connected to the upper and lower bridge bottom substrates 12 and 22. Further, the arrangement position of the rear case can be understood in conjunction with the front case 91 shown in fig. 6, specifically, the rear case is located at the rear side of the upper bridge substrate 1 and the lower bridge substrate 2, the upper end of the rear case is connected to the upper bridge top substrate and 11, the lower bridge top substrate 21, and the lower end of the rear case is connected to the upper bridge bottom substrate 12 and the lower bridge bottom substrate 22.

Further, when the front case 91 and the rear case are provided, the edge of the bottom plate a of the upper bridge top substrate 11 is grown out of the edge of the insulating layer B of the upper bridge top substrate 11 to form a first step, and the edge of the bottom plate a of the lower bridge top substrate 21 is grown out of the edge of the insulating layer B of the lower bridge top substrate 21 to form a second step; the edge of the bottom plate a of the upper bridge bottom substrate 12 is longer than the edge of the edge layer B of the upper bridge bottom substrate 12 to form a third step, and the edge of the bottom plate a of the lower bridge bottom substrate 22 is longer than the edge of the edge layer B of the lower bridge bottom substrate 22 to form a fourth step; the upper end of the front case 91 is erected on the first step and the second step, the lower end of the front case 91 is erected on the third step and the fourth step, the upper end of the rear case is erected on the first step and the second step, and the lower end of the rear case is erected on the third step and the fourth step. By providing the front case 91 and the rear case, the upper bridge substrate 1 and the lower bridge substrate 2 can be connected to form a single structure. And the upper bridge substrate 1 and the lower bridge substrate 2 are not directly electrified.

In some embodiments of the present utility model, as shown in fig. 7, a block diagram of a power module according to another embodiment of the present utility model is shown, wherein the power module 10 further comprises a DC power terminal 5 and an AC power terminal 6.

The DC power terminals 5 are connected to the first chip 31 and the third chip 41, and in particular, the DC power terminals 5 of the embodiment of the present utility model and the connection of the DC power terminals 5 to the first chip 31 and the third chip 41 can be understood in conjunction with fig. 2 to 7.

As shown in fig. 2 and 3, the DC power terminal 5 includes a DC positive terminal 51 and a DC negative terminal 52. The first chip 31 is connected to the DC positive terminal 51, and the third chip 41 is connected to the DC negative terminal 52, and specifically, the DC positive terminal 51 and the DC negative terminal 52 may be directly soldered on the corresponding upper bridge top substrate 11 and lower bridge top substrate 21.

As shown in fig. 4, the DC positive terminal 51 and the DC negative terminal 52 are each located at one end of the upper bridge top substrate 11 and the lower bridge top substrate 21 that are close to each other. One end of the DC positive terminal 51 is connected to the metal layer C of the upper bridge top substrate 11, specifically, one end of the DC positive terminal 51 is directly lapped on the metal layer C of the upper bridge top substrate 11, one surface of the first chip 31, which contacts the metal layer C, is the drain electrode of the first chip 31, the DC positive terminal 51 is directly conducted with the drain electrode of the first chip 31 through the metal layer C of the upper bridge top substrate 11, and when the power module 10 is conducted, current flows from the DC positive terminal 51 to the drain electrode of the first chip 31 through the metal layer C of the upper bridge top substrate 11.

As shown in fig. 4, the insulating layer B of the lower bridge top substrate 21 is further provided with a first bridging metal layer C1 spaced apart from the metal layer C of the lower bridge top substrate 21, and the first bridging metal layer C1 is located on one side of the lower bridge top substrate 21 close to the upper bridge top substrate 11, and the side of the third chip 41 in contact with the metal layer C is the drain electrode of the third chip 41, so that the DC negative terminal 52 is prevented from contacting the drain electrode of the third chip 41 by spacing the metal layer C of the lower bridge top substrate 21 from the first bridging metal layer C1, thereby facilitating the connection between the first bridging metal layer C1 and the source electrode of the third chip 41. And, as shown in fig. 4, two ends of the second metal block F may be respectively overlapped on the source electrode of the third chip 41 and the first bridging metal layer C1, so as to connect and conduct the source electrode of the third chip 41 and the first bridging metal layer C1. One end of the DC negative terminal 52 is connected to the first bridging metal layer C1, so that the source of the third chip 41 is connected to one end of the DC negative terminal 52 via the first bridging metal layer C1, and when the power module 10 is turned on, a current flows from the source of the third chip 41 to the DC negative terminal 52 via the second metal block F and the first bridging metal layer C1.

In other embodiments, as shown in fig. 2 or 3, the other end of the DC positive terminal 51 and the other end of the DC negative terminal 52 are bent, and led out between the upper bridge top substrate 11 and the lower bridge top substrate 21.

In some embodiments, as shown in fig. 2-4, the power module 10 further includes a first intermediate housing 93, the first intermediate housing 93 being disposed between the upper bridge top substrate 11 and the lower bridge top substrate 21, the first intermediate housing 93 having a first DC terminal exit hole from which the other end of the DC positive terminal 51 exits and a second DC terminal exit hole from which the other end 52 of the DC negative terminal exits. Wherein the first intermediate housing 93 is used to connect the upper bridge top base 11 and the lower bridge top base 21 as a unitary structure. And the upper bridge top substrate 11 and the lower bridge top substrate 21 are not directly energized.

Two holes for extracting the DC positive terminal 51 and the DC negative terminal 52, that is, a first DC terminal extracting hole and a second DC terminal extracting hole, may be opened between the upper bridge top substrate 11 and the lower bridge top substrate 21.

Further, the first DC terminal lead-out hole and the second DC terminal lead-out hole may be coaxial holes and have the same size, and the lengths of the DC positive terminal 51 and the DC negative terminal 52 are the same, that is, the DC positive terminal 51 and the DC negative terminal 52 are stacked, and the plastic packaging material is disposed inside the first DC terminal lead-out hole and the second DC terminal lead-out hole, or the sizes of the two lead-out holes may not be the same, or the shapes and the sizes of the DC positive terminal 51 and the DC negative terminal 52 may not be the same, which is convenient for installation. In addition, after the other ends of the DC positive terminal 51 and the DC negative terminal 52 are drawn out from between the upper bridge top substrate 11 and the lower bridge top substrate 21, filling of the insulating paste may be performed in the gaps between the DC power terminal 5, the DC negative terminal 52, and the first and second DC terminal drawing holes to prevent the DC positive terminal 51 and the DC negative terminal 52 from being short-circuited at the portion of the power module 10.

Based on the above, the DC positive terminal 51 and the DC negative terminal 52 are sintered on the metal layer C of the upper bridge top substrate 11 and the first bridging metal layer C1 of the lower bridge top substrate 21 respectively, and the first DC terminal lead-out hole and the second DC terminal lead-out hole are set to coaxial holes, so that the DC positive terminal 51 and the DC negative terminal 52 are stacked, a current conversion loop of the power module can be reduced as much as possible, and parasitic inductance of the upper bridge top substrate 11 and the lower bridge top substrate 21 can be reduced effectively.

In some embodiments, the AC power terminals 6 are connected with the second chip 32 and the fourth chip 42. In particular, the AC power terminal 6 of the embodiment of the present utility model, and the connection of the AC power terminal 6 with the second chip 32 and the fourth chip 42 can be understood in conjunction with fig. 2, 5 and 6.

Wherein, as shown in fig. 2, the AC power terminal 6 includes a first AC terminal 61 and a second AC terminal 62, specifically, the second chip 32 is connected to the first AC terminal 61, the fourth chip 42 is connected to the second AC terminal 62, the first AC terminal 61 and the second AC terminal 62 are each located at one end of the upper bridge base substrate 12 and the lower bridge base substrate 221 close to each other, specifically, the first AC terminal 61 and the second AC terminal 62 may be directly soldered on the upper bridge base substrate 12 and the lower bridge base substrate 22.

As shown in fig. 4, the insulating layer B of the upper bridge bottom substrate 12 is provided with a second bridging metal layer C2 spaced apart from the metal layer C of the upper bridge bottom substrate 12, and the second bridging metal layer C2 is located on one side of the upper bridge bottom substrate 12 close to the lower bridge bottom substrate 22, and the side of the second chip 32 in contact with the metal layer C is the drain electrode of the second chip 32, so that the first AC terminal 61 is prevented from contacting the drain electrode of the second chip 32 by spacing the metal layer C of the upper bridge bottom substrate 12 from the second bridging metal layer C2, so as to facilitate the connection between the second bridging metal layer C2 and the source electrode of the second chip 32. And, as shown in fig. 5, two ends of the second metal block F may be respectively overlapped on the source electrode of the second chip 32 and the second bridging metal layer C2, so as to connect and conduct the source electrode of the second chip 32 and the second bridging metal layer C2. One end of the DC negative terminal 52 is disposed to be connected to the first bridging metal layer C1 such that the source of the third chip 41 is connected to one end of the DC negative terminal 52 via the first bridging metal layer C1, and one end of the first AC terminal 61 is disposed to be connected to the second bridging metal layer C2 such that the source of the second chip 32 is connected to one end of the first AC terminal 61 via the second bridging metal layer C2. When the power module 10 is turned on, a current flows from the source of the second chip 32 to the first AC terminal 61 through the second metal block F and the second bridging metal layer C2.

As shown in fig. 4, one end of the second AC terminal 62 is connected to the metal layer C of the lower bridge base substrate 22. Specifically, one end of the second AC terminal 62 is directly lapped on the metal layer C of the lower bridge bottom substrate 22, the side of the fourth chip 42 contacting the metal layer C is the drain of the fourth chip 42, the second AC terminal 62 is directly conducted with the drain of the fourth chip 42 through the metal layer C of the lower bridge bottom substrate 22, and when the power module 10 is conducted, the current flows from the second AC terminal 62 to the drain of the fourth chip 42 through the metal layer C of the lower bridge bottom substrate 22.

In other embodiments, as shown in fig. 2, the other end of the first AC terminal 61 and the other end of the second AC terminal 62 are both bent, leading out between the upper bridge base substrate 12 and the lower bridge base substrate 22.

In some embodiments, as shown in fig. 2 and 5, the power module 10 further includes a second intermediate housing 94, the second intermediate housing 94 being disposed between the upper bridge base substrate 12 and the lower bridge base substrate 22, the second intermediate housing 94 having a first AC terminal exit hole from which the other end of the first AC terminal 61 exits and a second AC terminal exit hole from which the other end of the second AC terminal 62 exits. Wherein the second intermediate housing 94 is used to connect the upper bridge floor 12 to the lower bridge floor 22 in a unitary structure. And the upper bridge base substrate 12 and the lower bridge base substrate 22 are not directly energized.

Two holes for leading out the first AC terminal 61 and the second AC terminal 62, that is, a first AC terminal leading-out hole and a second AC terminal leading-out hole, may be opened between the upper bridge base substrate 12 and the lower bridge base substrate 22.

Further, the first AC terminal extraction hole and the second AC terminal extraction hole may be provided as coaxial holes and are identical in size, and the lengths of the first AC terminal 61 and the second AC terminal 62 are identical, that is, the first AC terminal 61 and the second AC terminal 62 are placed in a stack, and the inside of the first AC terminal extraction hole and the second AC terminal extraction hole is provided with a molding material. Or the sizes of the two lead-out holes may be different, or the shapes and the sizes of the first AC terminal 61 and the second AC terminal 62 may be different, so that the installation is convenient. In addition, after the other ends of the first and second AC terminals 61 and 62 are drawn out from between the upper and lower bridge base substrates 12 and 22, filling of an insulating paste may be performed in a gap between the first and second AC terminal drawing holes to prevent short circuits from occurring at portions of the first and second AC terminals 61 and 62 located inside the power module 10.

Based on the above, the first AC terminal lead-out hole and the second AC terminal lead-out hole are set to coaxial holes, so that the first AC terminal 61 and the second AC terminal 62 are stacked, facilitating connection of the first AC terminal 61 and the second AC terminal 62 with the external motor terminal.

Further, the DC positive terminal 51, the DC negative terminal 52, the first AC terminal 61, and the second AC terminal 62 above may be directly welded to the corresponding upper bridge top substrate 11, lower bridge top substrate 21, upper bridge bottom substrate 12, and lower bridge bottom substrate 22. And, as shown in fig. 2-5, when the number of the first chip 31, the second chip 32, the third chip 41 and the fourth chip 42 is plural, the drains of the chips disposed on the same metal layer C can be directly connected and conducted with the corresponding terminals, and the source connections of the chips on the same metal layer C can be connected and conducted by overlapping the first metal block E on the chip surface.

In addition, the number of AC power terminals 6 may be 1, and it is only necessary to design terminals that can connect the upper bridge base substrate 12 and the lower bridge base substrate 22.

According to the power module 10 according to the embodiment of the present utility model, the first chip 31 and the second chip 32 are respectively disposed on the upper bridge top substrate 11 and the upper bridge bottom substrate 12 of the upper bridge substrate 1, and the third chip 41 and the fourth chip 42 are respectively disposed on the lower bridge top substrate 21 and the lower bridge bottom substrate 22 of the lower bridge substrate 2, by disposing the upper bridge top substrate 11 and the upper bridge bottom substrate 12 opposite to each other, and disposing the lower bridge top substrate 21 and the lower bridge bottom substrate 22 opposite to each other, when the chips are turned on, current flows from the DC power terminal 5 into the first chip 31 and flows from the AC power terminal 6 via the second chip 32, and current flows from the AC power terminal 6 into the third chip 41 and flows from the DC power terminal 5 via the fourth chip 42, and the power loop current direction in the power module 10 is bidirectional. And the upper bridge substrate 1 and the lower bridge substrate 2 are provided with reverse currents, so that two reverse currents exist in the power module 10, magnetic fields generated by the reverse currents are mutually coupled, and therefore the power current loop inductance can be reduced, large overcharging voltage is not easy to cause, the chip switching loss is reduced, and the reliability and the service life of the power module 10 are improved.

In some embodiments of the present utility model, as shown in fig. 4 and 5, the metal layer C of the upper bridge top substrate 11, the metal layer C of the upper bridge bottom substrate 12, the metal layer C of the lower bridge top substrate 21, and the metal layer C of the lower bridge bottom substrate 22 each include a chip conductive region M and a signal transmission region N that are spaced apart, and the power chips are respectively disposed in the corresponding chip conductive regions M.

In some embodiments, the first chip 31, the second chip 32, the third chip 41 and the fourth chip 42 each include a plurality of power chips, and the plurality of power chips are distributed in the chip conductive areas M of the corresponding substrate. That is, the number of the first chip 31, the second chip 32, the third chip 41, and the fourth chip 42 may be plural, for example, may be 2 or 3 or 4 or 6, etc., and is not particularly limited herein. The arrangement condition of the chips on the substrate can be various, for example, the chips can be uniformly distributed along the edge of the substrate, and by adopting the design mode, the distance from each chip in the chip conductive area M to the signal transmission area N can be ensured to be equal as much as possible, the arrangement and the wiring are convenient, and the heat dissipation of each substrate can be uniform.

Specifically, taking four chips, which are arranged in a 2×2 arrangement, as an example, the first chip 31, the second chip 32, the third chip 41, and the fourth chip 42 shown in fig. 4 and 5, sources of two chips located in the same row are connected. For two chips in the same row in each row, the first metal block E can be lapped on the surface of the chip to conduct the source connection of the two chips in the same row on the same metal layer C.

The area where the chip is located is the chip conductive area M, and a signal transmission area N is arranged at a part far away from the chip conductive area M. Specifically, the signal transmission area N is located at a central position of the corresponding substrate, and the chip conductive area M surrounds the signal transmission area N.

And, in some embodiments, the power module 10 further includes signal terminals P disposed on the upper bridge top substrate 11, the upper bridge bottom substrate 12, the lower bridge top substrate 21, and the lower bridge bottom substrate 22, respectively, and the signal terminals P and the signal transmission areas N of the embodiments of the present utility model can be understood in conjunction with fig. 3-8. Fig. 8 is a schematic diagram of a power module according to yet another embodiment of the utility model. Only the signal terminals P provided on the upper bridge top substrate 11 are labeled in fig. 3, 6 and 8.

Specifically, one end of the signal terminal P is connected to the corresponding signal transmission area N, and the other end of the signal terminal P is led out from the corresponding substrate, and the other end of the signal terminal P may be externally connected to a driving circuit or a driving board. The signal terminal P passes through the insulating layer B and the bottom plate A to be led out, corresponding holes are reserved on the insulating layer B and the bottom plate A, the holes are insulated and encapsulated after connection is completed, the outer parts of the signal terminal P, which are connected with the driving plate, are subjected to outer insulation treatment, and the length of a driving loop can be reduced by adopting the connection mode, so that the inductance of the driving loop is reduced.

Specifically, in some embodiments, as shown in fig. 6, a gate signal extraction hole n1 and a source signal extraction hole n2 are provided on each substrate; the signal transmission area N comprises a grid signal transmission area N1 and a source signal transmission area N2, the grid signal transmission area N1 is positioned at the grid signal extraction hole N1, and the source signal transmission area N2 is positioned at the source signal extraction hole N2.

As shown in fig. 4 or 5, the gate signal transmission region N1 is connected to the gate of the power chip provided on the same substrate, and the source signal transmission region N2 is connected to the source of the power chip provided on the same substrate. When the first chip 31, the second chip 32, the third chip 41 and the fourth chip 42 are disposed, the chips that may be disposed on the same metal layer C are arranged in such a manner that the gate ends are arranged opposite to each other, so that the distance between the gate of each chip on the same metal layer C and the gate signal transmission area N1 is substantially the same.

For example, the cutting may be directly performed on the central position of the prepared substrate, and after the cutting is completed, two holes or one large hole is formed on the central position of the substrate, and the two cut parts are used as the gate signal transmission area N1 and the source signal transmission area N2, so that the components of the gate signal transmission area N1 and the source signal transmission area N2 are the same as the substrate, and each include the bottom plate a, the insulating layer B and the metal layer C which are stacked. The gate signal transmission area N1 and the source signal transmission area N2 are placed in two holes or one large hole, the gate signal transmission area N1, the source signal transmission area N2 and the substrate are not contacted, the gate signal transmission area N1 is provided with a gate signal leading-out hole N1, and the source signal transmission area N2 is provided with a source signal leading-out hole N2.

More specifically, as shown in fig. 3, the signal terminal P includes a gate signal terminal P1 and a source signal terminal P2, and inside the power device 10, as shown in fig. 4 or 5, the gate is connected to the gate signal transmission region N1 through a gate lead, one end of the gate signal terminal P1 is connected to the corresponding gate signal transmission region N1, and the other end of the gate signal terminal P1 is led out from the gate signal lead-out hole N1 as shown in fig. 6. As shown in fig. 4 or 5, the source and source signal transmission regions N2 are connected by source leads, one end of the source signal terminal P2 is connected to the corresponding source signal transmission region N2, the other end of the source signal terminal P2 is led out from the source signal lead-out hole N2 as shown in fig. 6, and the lead-out directions of the gate signal terminal P1 and the source signal terminal P2 are directions in which the substrate is not sintered.

In some embodiments, the power module 10 further includes an upper bridge connection metal block 7 and a lower bridge connection metal block 8, and the upper bridge substrate 1 further includes an upper bridge side substrate 13, and the lower bridge substrate 2 further includes a lower bridge side substrate 23.

Wherein the upper bridge connecting metal block 7, the lower bridge connecting metal block 8, the upper bridge side substrate 13 and the lower bridge side substrate 23 of an embodiment of the present utility model can be understood in conjunction with fig. 2-5, 8.

As shown in fig. 2, the upper bridge connection metal block 7 is located on one side of the upper bridge substrate 1 away from the lower bridge substrate 2, one end of the upper bridge connection metal block 7 is connected to the source of the first chip 31, and the other end of the upper bridge connection metal block 7 is connected to the source of the second chip 32. As can be seen from the above, the upper bridge power chip 3 includes the first chip 31 and the second chip 32 connected to each other, and then the source and drain electrodes of the first chip 31 and the second chip 32 need to be connected to each other.

Specifically, for four first chips 31 and four second chips 32, each arranged in a 2×2 arrangement, one end of the upper bridge connection metal block 7 may be sintered on the source of the first chip 31 of the upper bridge top substrate 11, and the other end of the upper bridge connection metal block 7 may be sintered on the source of the second chip 32 located opposite to the upper bridge bottom substrate 12, so as to realize source connection of two first chips 31 located in different rows of the upper bridge top substrate 11 and two second chips 32 located opposite to the upper bridge bottom substrate 12.

The upper bridge side substrate 13 is disposed on a side of the upper bridge substrate 1 away from the lower bridge substrate 2 and is connected with the upper bridge top substrate 11 and the upper bridge bottom substrate 12, the upper bridge side substrate 13 includes an insulating layer B and a metal layer C which are stacked, and the metal layer C of the upper bridge side substrate 13 is connected with the metal layer C of the upper bridge top substrate 11 and the metal layer C of the upper bridge bottom substrate 12. Since the drain electrode of the first chip 31 is connected to the metal layer C of the upper bridge top substrate 11, and since the drain electrode of the second chip 32 is connected to the metal layer C of the upper bridge bottom substrate 12, the metal layers C of the upper and lower substrates are connected by the metal layer C of the upper bridge side substrate 13, so that the drain electrode of the first chip 31 can be connected to the drain electrode of the second chip 32.

As shown in fig. 3 and 4, the upper bridge side substrate 13 is located outside the upper bridge connection metal block 7, and a space is provided between the metal layer C of the upper bridge side substrate 13 and the upper bridge connection metal block 7, and further, after plastic packaging, insulating glue filling may be performed in the whole plastic packaging area, so as to ensure that the drain and the source of the first chip 31 and the second chip 32 are in an insulating state.

In some embodiments, as shown in fig. 2-5 and 6, the power module 10 further includes a left housing 95, the left housing 95 being disposed outside the upper bridge side substrate 13, the left housing 95 being connected to the front housing 91, the rear housing, the upper bridge top substrate 11 and the upper bridge bottom substrate 12, respectively.

And, as shown in fig. 2, the lower bridge connection metal block 8 is located on one side of the lower bridge substrate 2 away from the upper bridge substrate 1, one end of the lower bridge connection metal block 8 is connected to the source of the third chip 41, and the other end of the lower bridge connection metal block 8 is connected to the source of the fourth chip 42. As can be seen from the above, the lower bridge power chip 4 includes the third chip 41 and the fourth chip 42 connected to each other, and then the source and drain electrodes of the third chip 41 and the fourth chip 42 need to be connected to each other.

Specifically, for the four third chips 41 and the four fourth chips 42, each arranged in a 2×2 arrangement, one end of the lower bridge connection metal block 7 may be sintered on the source of the third chip 41 of the lower bridge top substrate 21, and the other end of the lower bridge connection metal block 7 may be sintered on the source of the fourth chip 42 located opposite to the lower bridge bottom substrate 22, so as to realize source connection of two third chips 41 located in different rows of the lower bridge top substrate 21 and two fourth chips 42 located opposite to the lower bridge bottom substrate 22.

The lower bridge side substrate 23 is disposed on a side of the lower bridge substrate 2 away from the upper bridge substrate 1 and is connected to the lower bridge top substrate 21 and the lower bridge bottom substrate 22, the lower bridge side substrate 23 includes an insulating layer B and a metal layer C which are stacked, and the metal layer C of the lower bridge side substrate 23 is connected to the metal layer C of the lower bridge top substrate 21 and the metal layer C of the lower bridge bottom substrate 22. Since the drain electrode of the third chip 41 is connected to the metal layer C of the lower bridge top substrate 21, and since the drain electrode of the fourth chip 42 is connected to the metal layer C of the lower bridge bottom substrate 22, the metal layer C of the lower bridge side substrate 23 is used to connect the metal layers C of the upper and lower substrates, so that the drain electrode of the third chip 41 can be connected to the drain electrode of the fourth chip 42.

In some embodiments, as shown in fig. 2-5 and 6, the power module 10 further includes a right housing 96, the right housing 96 being disposed outside the lower bridge side substrate 23, the right housing 96 being connected to the front housing 91, the rear housing, the lower bridge top substrate 21 and the lower bridge bottom substrate 22, respectively.

Based on the above, the upper bridge substrate 1, the lower bridge substrate 2, the upper bridge side substrate 13, and the lower bridge side substrate 23 of the embodiment of the present utility model are all disposed in the insulating case composed of the front case 91, the rear case, the first middle case 93, the second middle case 94, the left case 95, and the right case 9, and the bottom plate a of the upper bridge substrate 1 and the bottom plate a of the lower bridge substrate 2 are exposed outside the case, that is, the entire case may be a semi-plastic package structure, wrapping at least the sides of the power module 10 except the upper bridge top substrate 11, the upper bridge bottom substrate 12, the lower bridge top substrate 21, and the lower bridge bottom substrate 22. The front case 91, the rear case, the first middle case 93, the second middle case 94, the left case 95 and the right case 9 plastic-package all elements together except the bottom plate a, which is not in the plastic-packaged area, the bottom plate a is exposed to better exert its heat radiation function.

And as shown in fig. 3 and 5, the lower bridge side substrate 23 is located at the outer side of the lower bridge connection metal block 8, and a space is provided between the metal layer C of the lower bridge side substrate 23 and the lower bridge connection metal block 8, and further, after plastic packaging, insulating glue filling may be performed in the whole plastic packaging area, so as to ensure that the drain and source electrodes of the third chip 41 and the fourth chip 42 are in an insulating state.

Based on the above, when the power module 10 of the embodiment of the utility model is turned on, there is a current flowing in and out, the current flows in from the DC positive terminal 51, flows to the drain of the first chip 31 through the metal layer C of the upper bridge top substrate 11, flows to the drain of the second chip 32 through the metal layer C of the upper bridge top substrate 11, the metal layer C of the upper bridge side substrate 13 and the metal layer C of the lower bridge top substrate 21, the current in the first chip 31 flows from the drain of the first chip 31 to the source of the first chip 31, and the current flowing out from the source of the second chip 32 through the upper bridge connection metal block 7 flows out from the first AC terminal 61 through the first bridge metal layer C1. And, the current flows from the second AC terminal 62, through the metal layer C of the lower bridge bottom substrate 22 to the drain of the fourth chip 4, and through the metal layer C of the lower bridge bottom substrate 22, the metal layer C of the lower bridge side substrate 23, and the metal layer C of the lower bridge top substrate 21 to the drain of the third chip 41. The current in the fourth chip 4 flows from the drain of the third chip 41 to the source of the third chip 41, and the current flowing out of the source of the third chip 41 via the lower bridge connection metal block 8 flows out of the DC negative terminal 52 via the second bridge metal layer C2. The currents flowing through the upper bridge top substrate 11 and the upper bridge bottom substrate 12 are reverse currents, the currents flowing through the lower bridge top substrate 21 and the lower bridge bottom substrate 22 are reverse currents, and after the upper bridge substrate 1 and the lower bridge substrate 2 of the power module 10 are both in a folded structure, two reverse currents exist in the power module under the conduction condition, magnetic fields generated by the reverse currents are mutually coupled, so that the total inductance of the whole power module 10 can be reduced, the overshoot voltage of the power module 10 can be effectively reduced, the switching loss of a chip is reduced, and the reliability and the service life of the low module are improved.

In some embodiments of the present utility model, the gaps inside the power module 10 are filled with insulating glue, i.e. the insulating glue is filled in the plastic sealing area. For example, an insulating paste is applied to a gap between the metal layer C of the lower bridge top substrate 21 and the first bridging metal C1, a gap between the metal layer C of the upper bridge bottom substrate 12 and the second bridging metal layer C2, and the like. And filling insulating glue into gaps formed in the metal insulating layer B and the bottom plate A for the gate signal transmission area N1 and the source signal transmission area N2. And, to the terminal perforation that sets up on casing 9, draw forth each terminal from the terminal perforation after, still need to carry out insulating encapsulating to the gap between terminal perforation and the terminal, and then can prevent to take place the short circuit between the structure that the distance is nearer but not contact, promote the stability of whole power module 10.

In some embodiments of the present utility model, an apparatus is also presented, as shown in fig. 9, which is a block diagram of an apparatus according to one embodiment of the present utility model, wherein the apparatus 100 comprises a power module 10 according to any of the embodiments above.

According to the device 100 provided by the embodiment of the utility model, by adopting the power module 10 of the embodiment, the power current loop inductance can be reduced, large overcharging voltage is not easy to cause, the chip switching loss is reduced, and the reliability and the service life of the device 100 are improved.

Other configurations and operations of the device 100 and the power module 10 according to embodiments of the present utility model are known to those of ordinary skill in the art and will not be described in detail herein.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.

While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.

Claims (26)

1. A power module, comprising:

the upper bridge substrate comprises an upper bridge top substrate and an upper bridge bottom substrate, and the upper bridge top substrate and the upper bridge bottom substrate are oppositely arranged;

the lower bridge substrate comprises a lower bridge top substrate and a lower bridge bottom substrate, and the lower bridge top substrate and the lower bridge bottom substrate are oppositely arranged;

the upper bridge power chip comprises a first chip and a second chip which are connected with each other, the first chip is arranged on one surface of the upper bridge top substrate facing the upper bridge bottom substrate, and the second chip is arranged on one surface of the upper bridge bottom substrate facing the upper bridge top substrate;

the lower bridge power chip comprises a third chip and a fourth chip which are connected with each other, wherein the third chip is arranged on one surface of the lower bridge top substrate facing the lower bridge bottom substrate, and the fourth chip is arranged on one surface of the lower bridge bottom substrate facing the lower bridge top substrate.

2. The power module of claim 1, wherein the power module comprises a power supply,

the upper bridge substrate is arranged on one side of the lower bridge substrate, the upper bridge top substrate and the lower bridge top substrate are arranged in a left-right parallel manner, and the upper bridge bottom substrate and the lower bridge bottom substrate are arranged in a left-right parallel manner.

3. The power module of claim 2, further comprising:

the front shell is positioned at the front sides of the upper bridge substrate and the lower bridge substrate, the upper end of the front shell is connected with the upper bridge top substrate and the lower bridge top substrate, and the lower end of the front shell is connected with the upper bridge bottom substrate and the lower bridge bottom substrate;

the rear shell is positioned at the rear sides of the upper bridge substrate and the lower bridge substrate, the upper end of the rear shell is connected with the upper bridge top substrate and the lower bridge top substrate, and the lower end of the rear shell is connected with the upper bridge bottom substrate and the lower bridge bottom substrate.

4. The power module of claim 3 wherein the upper bridge top substrate, the upper bridge bottom substrate, the lower bridge top substrate, and the lower bridge bottom substrate each comprise a bottom plate, an insulating layer, and a metal layer, the bottom plate, the insulating layer, and the metal layer being stacked.

5. The power module of claim 4, wherein the power module further comprises a power supply,

the edge of the bottom plate of the upper bridge top substrate is longer than the edge of the insulating layer of the upper bridge top substrate to form a first step, and the edge of the bottom plate of the lower bridge top substrate is longer than the edge of the insulating layer of the lower bridge top substrate to form a second step;

The edge of the bottom plate of the upper bridge bottom substrate is longer than the edge of the edge layer of the upper bridge bottom substrate to form a third step, and the edge of the bottom plate of the lower bridge bottom substrate is longer than the edge of the edge layer of the lower bridge bottom substrate to form a fourth step;

the upper end of the front shell is erected on the first step and the second step, the lower end of the front shell is erected on the third step and the fourth step, the upper end of the rear shell is erected on the first step and the second step, and the lower end of the rear shell is erected on the third step and the fourth step.

6. The power module of claim 4, wherein the drain of the first chip is mounted on the metal layer of the upper bridge top substrate, the drain of the second chip is mounted on the metal layer of the upper bridge bottom substrate, the drain of the third chip is mounted on the metal layer of the lower bridge top substrate, and the drain of the fourth chip is mounted on the metal layer of the lower bridge bottom substrate.

7. The power module of claim 6, wherein the power module further comprises a power supply,

the insulating layer of the lower bridge top substrate is also provided with a first bridging metal layer which is separated from the metal layer of the lower bridge top substrate, the first bridging metal layer is positioned on one side of the lower bridge top substrate, which is close to the upper bridge top substrate, and the first bridging metal layer is connected with the source electrode of the third chip.

8. The power module of claim 7, further comprising:

a DC power terminal connected with the first chip and the third chip, and an AC power terminal connected with the second chip and the fourth chip.

9. The power module of claim 8, wherein the DC power terminal comprises:

one end of the DC positive electrode terminal is connected with the metal layer of the upper bridge top substrate;

and a DC negative electrode terminal, one end of which is connected with the first bridging metal layer.

10. The power module of claim 9 wherein the other end of the DC positive terminal and the other end of the DC negative terminal are bent, the other end of the DC positive terminal and the other end of the DC negative terminal leading from between the upper bridge top substrate and the lower bridge top substrate.

11. The power module of claim 10, further comprising:

the first middle shell is arranged between the upper bridge top substrate and the lower bridge top substrate, a first DC terminal leading-out hole and a second DC terminal leading-out hole are formed in the first middle shell, the other end of the DC positive terminal is led out from the first DC terminal leading-out hole, and the other end of the DC negative terminal is led out from the second DC terminal leading-out hole.

12. The power module of claim 8, wherein the power module further comprises a power supply,

the insulating layer of the upper bridge bottom substrate is provided with a second bridging metal layer which is separated from the metal layer of the upper bridge bottom substrate, the second bridging metal layer is positioned on one side of the upper bridge bottom substrate, which is close to the lower bridge bottom substrate, and the second bridging metal layer is connected with the source electrode of the second chip.

13. The power module of claim 12, wherein the AC power terminal comprises:

a first AC terminal having one end connected to the second bridging metal layer;

and one end of the second AC terminal is connected with the metal layer of the lower bridge bottom substrate.

14. The power module of claim 13, wherein the other end of the first AC terminal and the other end of the second AC terminal are bent, and the other end of the first AC terminal and the other end of the second AC terminal are led out from below between the upper bridge bottom substrate and the lower bridge bottom substrate.

15. The power module of claim 14, further comprising:

the second middle shell is arranged between the upper bridge bottom substrate and the lower bridge bottom substrate, a first AC terminal leading-out hole and a second AC terminal leading-out hole are formed in the second middle shell, the other end of the first AC terminal is led out from the first AC terminal leading-out hole, and the other end of the second AC terminal is led out from the second AC terminal leading-out hole.

16. The power module of claim 6, wherein the power module further comprises a power supply,

the metal layer of the upper bridge top substrate, the metal layer of the upper bridge bottom substrate, the metal layer of the lower bridge top substrate and the metal layer of the lower bridge bottom substrate all comprise separated chip conducting areas and signal transmission areas, and the power chips are respectively arranged in the corresponding chip conducting areas;

the power module further comprises signal terminals respectively arranged on the upper bridge top substrate, the upper bridge bottom substrate, the lower bridge top substrate and the lower bridge bottom substrate, one ends of the signal terminals are connected with corresponding signal transmission areas, and the other ends of the signal terminals are led out from the corresponding substrates.

17. The power module of claim 16, wherein the power module further comprises a power supply,

each substrate is provided with a grid signal leading-out hole and a source signal leading-out hole;

the signal transmission area comprises a grid signal transmission area and a source signal transmission area, the grid signal transmission area is connected with a grid of a power chip arranged on the same substrate, and the source signal transmission area is connected with a source of the power chip arranged on the same substrate;

the signal terminals comprise gate signal terminals and source signal terminals, one ends of the gate signal terminals are connected with the corresponding gate signal transmission areas, the other ends of the gate signal terminals are led out from the gate signal leading-out holes, one ends of the source signal terminals are connected with the corresponding source signal transmission areas, and the other ends of the source signal terminals are led out from the source signal leading-out holes.

18. The power module of claim 17, wherein the power module further comprises a power supply,

the first chip, the second chip, the third chip and the fourth chip comprise a plurality of power chips, and the power chips are distributed in chip conductive areas of the corresponding substrates;

the signal transmission area is positioned at the central position of the corresponding substrate, and the chip conductive area surrounds the signal transmission area.

19. The power module of claim 6, further comprising:

the upper bridge connection metal block is positioned on one side of the upper bridge substrate, which is far away from the lower bridge substrate, one end of the upper bridge connection metal block is connected with the source electrode of the first chip, and the other end of the upper bridge connection metal block is connected with the source electrode of the second chip.

20. The power module of claim 19, wherein the upper bridge substrate further comprises:

the upper bridge side substrate is arranged on one side, far away from the lower bridge substrate, of the upper bridge substrate and is connected with the upper bridge top substrate and the upper bridge bottom substrate, the upper bridge side substrate comprises an insulating layer and a metal layer, the insulating layer and the metal layer are arranged in a laminated manner, and the metal layer of the upper bridge side substrate is connected with the metal layer of the upper bridge top substrate and the metal layer of the upper bridge bottom substrate;

The upper bridge side surface substrate is positioned at the outer side of the upper bridge connecting metal block, and a space is reserved between the metal layer of the upper bridge side surface substrate and the upper bridge connecting metal block.

21. The power module of claim 20, further comprising:

the left shell is arranged on the outer side of the upper bridge side surface substrate and is respectively connected with the front shell and the rear shell.

22. The power module of claim 6, further comprising:

the lower bridge connection metal block is positioned on one side, far away from the upper bridge substrate, of the lower bridge substrate, one end of the lower bridge connection metal block is connected with the source electrode of the third chip, and the other end of the lower bridge connection metal block is connected with the source electrode of the fourth chip.

23. The power module of claim 22, wherein the lower bridge substrate further comprises:

the lower bridge side substrate is arranged on one side, far away from the upper bridge substrate, of the lower bridge substrate and is connected with the lower bridge top substrate and the lower bridge bottom substrate, the lower bridge side substrate comprises an insulating layer and a metal layer, the insulating layer and the metal layer are arranged in a laminated manner, and the metal layer of the lower bridge side substrate is connected with the metal layer of the lower bridge top substrate and the metal layer of the lower bridge bottom substrate;

The lower bridge side substrate is positioned at the outer side of the lower bridge connecting metal block, and a space is reserved between the metal layer of the lower bridge side substrate and the lower bridge connecting metal block.

24. The power module of claim 23, further comprising:

the right shell is arranged on the outer side of the lower bridge side surface substrate and is respectively connected with the front shell and the rear shell.

25. The power module of any one of claims 4-24, wherein an insulating gel is encapsulated in the gaps inside the power module.

26. An apparatus comprising the power module of any one of claims 1-25.