CN111090895A - Logic destruction system and method for EMMC (embedded multi-media card) memory - Google Patents

Abstract

The invention relates to an EMMC memory logic destruction system, which comprises a trigger signal, an EMMC controller, a high-speed analog switch, an external MCU and an EMMC memory, wherein the trigger signal is electrically connected with the EMMC controller; the EMMC controller receives the trigger signal and sends a switching signal to the high-speed analog switch, and the high-speed analog switch receives the switching signal sent by the EMMC controller and switches the conduction state according to the switching signal to enable the external MCU to be electrically connected with the EMMC memory to perform read-write operation or enable the EMMC controller to be electrically connected with the EMMC memory to perform logic destruction operation. It also relates to a destruction method. The invention adopts the high-speed analog switch to enable the external MCU and the EMMC controller to perform read-write or logic destruction operation on the EMMC memory in a time-sharing manner.

Description

Logic destruction system and method for EMMC (embedded multi-media card) memory

Technical Field

The invention relates to the technical field of memory logic destruction, in particular to an EMMC memory logic destruction system and method.

Background

With the development of informatization, data is more and more important, particularly in some sensitive occasions, the data is required to be rapidly destroyed, and along with the requirement, a large number of products with SATA hard disks and NVME hard disks for logical destruction exist in China at present, and the products can destroy the data through a destruction signal.

In the embedded field, a part of MCU (microprogrammed control Unit) cannot be directly started from an SATA (serial advanced technology attachment) hard disk and an NVME (network video management) hard disk, can only be started from an SPI (serial peripheral interface) FLASH or an EMMC (embedded multi-media card) memory, and is mounted with a hard disk with logic destruction after the start is finished. The hard disk with logic destruction is high in price, data in the hard disk can be destroyed only, and the data stored in the SPI FLASH or EMMC memory cannot be destroyed because the common MCU does not have an interface corresponding to the EMMC. When the device is carelessly lost or acquired by an adversary, confidential information or sensitive data is easily leaked.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an EMMC memory logic destroying system and a destroying method for realizing read-write or logic destroying operation on an EMMC memory by time-sharing control on the EMMC memory.

The technical scheme for solving the technical problems is as follows: the logic destruction system for the EMMC memory comprises a trigger signal, an EMMC controller, a high-speed analog switch, an external MCU and an EMMC memory;

the trigger signal is electrically connected with the EMMC controller, so that the EMMC controller outputs a switching signal according to the trigger signal;

the EMMC controller is electrically connected with the high-speed analog switch and used for outputting a switching signal to the high-speed analog switch according to a trigger signal;

the high-speed analog switch is respectively electrically connected with the EMMC memory and the external MCU and is used for switching the conduction state according to the switching signal so that the external MCU is electrically connected with the EMMC memory to perform read-write operation or the EMMC controller is electrically connected with the EMMC memory to perform logic destruction operation.

On the basis of the technical scheme, in order to achieve the convenience of use and the stability of equipment, the invention can also make the following improvements on the technical scheme:

further, the trigger signal is a power-on signal or a destruction signal, and when the trigger signal is the power-on signal, the external MCU is electrically connected with the EMMC memory to perform read-write operation; and when the trigger signal is a destruction signal, the EMMC controller is electrically connected with the EMMC memory to destroy the data in the EMMC memory.

Further, the system also comprises a destroy button, and a destroy signal is sent to the EMMC controller by pressing the destroy button.

Furthermore, the EMMC controller is electrically connected with the EMMC memory through an SDIO driving program, and data in the EMMC memory is destroyed by writing SDIO driving according to the sequence of the EMMC interface so that the common EMMC controller without the EMMC interface can achieve the purpose.

Further, the high-speed analog switch is the SGM37222, a high-speed analog switch switching matrix is formed by adopting 4 SGM7222 analog switches, and the data transmission rate can reach 500Mhz, so that the integrity of the EMMC interface signal is effectively ensured.

Further, the EMMC controller is electrically connected with a CTRL pin of the high-speed analog switch and sends a switching signal to the high-speed analog switch by controlling the state of the CTRL pin; when the trigger signal is a destruction signal, the EMMC control pin CTRL is switched to a state '1', and the high-speed analog switch is reversely switched to enable the EMMC controller to be electrically connected with the EMMC memory to perform logic operation.

The invention also comprises an EMMC memory logic destroying method which is characterized by comprising the following steps:

step 210, powering on, namely powering on the logic destruction system of the EMMC;

step 220, reading the destruction flag bit, and reading the state of the data bit corresponding to the pin CTRL;

step 230, destroy enable, to determine whether the data in the EMMC memory 150 is being destroyed before power off, if yes, go to step 270 to continue erasing the BLOCK in the memory; otherwise, go to step 240;

step 240, destruction triggering detection, which is to detect whether the triggering signal is a destruction signal;

step 250, judging whether the duration time of the destruction signal is longer than 2 seconds, if not, returning to the step 240 of continuously detecting the type of the trigger signal; if yes, go to step 260;

step 260, setting a destruction flag bit, namely setting a data bit corresponding to the pin CTRL to be 1;

step 270, erasing Block, and erasing data in the EMMC memory 150;

step 280, judging whether the whole-disk erasing is finished, if not, returning to continue to execute the step 270 to continuously erase the data in the EMMC memory 150; if yes, go to step 290;

and 290, clearing the destroying flag bit, and setting the data bit corresponding to the pin CTRL to be 0 after destroying is finished.

The invention has the beneficial effects that: the invention adopts the high-speed analog switch to realize the time-sharing read-write or logic destruction operation of the external MCU and the EMMC controller on the EMMC memory, thereby ensuring the timely destruction of the data in the EMMC controller, avoiding information leakage and improving the safety; by writing SDIO drive, the common EMMC controller without the EMMC interface has the function of destroying data in the EMMC memory, and the development cost of products is reduced.

Drawings

FIG. 1 is a schematic structural diagram of an EMMC memory logic destruction system;

FIG. 2 is a schematic diagram of a circuit structure of an EMMC memory for logic destruction;

FIG. 3 is a schematic diagram of a circuit structure of the EMMC during read/write operations;

FIG. 4 is a flow chart of EMMC memory logic destruction.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

As shown in fig. 1 to 3, an EMMC memory logic destruction system includes a trigger signal 110, an EMMC controller 120, a high-speed analog switch 130, an external MCU140, and an EMMC memory 150;

the trigger signal 110 is electrically connected with the EMMC controller 120 of the GD32 series, so that the EMMC controller 120 outputs a switching signal according to the trigger signal 110;

the EMMC controller 120 is electrically connected to the high-speed analog switch 130, and is configured to output a switching signal to the high-speed analog switch 130 according to the trigger signal 110;

the high-speed analog switch 130 is electrically connected to the EMMC memory 150 and the external MCU140, and is configured to switch the on state according to the switching signal to electrically connect the external MCU140 and the EMMC memory 150 for performing the read/write operation or electrically connect the EMMC controller 120 and the EMMC memory 150 for performing the logic destruction operation.

The trigger signal 110 is a power-on signal or a destruction signal, and when the trigger signal 110 is a power-on signal, the external MCU140 is electrically connected to the EMMC memory 150 to perform read-write operation; when the trigger signal 110 is a destroy signal, the EMMC controller 120 is electrically connected to the EMMC memory 150 to perform a logic destroy operation on data in the EMMC memory 150.

A destruction button is also included that sends a destruction signal to the EMMC controller 120 by pressing the destruction button.

The EMMC controller 120 is electrically connected with the EMMC memory 150 through an SDIO driver, and data in the EMMC memory 150 can be destroyed by writing SDIO drive according to the sequence of the EMMC interface so that the common EMMC controller 120 without the EMMC interface can also achieve destruction.

The high-speed analog switch 130 is an SGM37222, a high-speed analog switch switching matrix is formed by adopting 4 SGM7222 analog switches, and the data transmission rate can reach 500Mhz, so that the integrity of an EMMC interface signal is effectively ensured.

The EMMC controller 120 is electrically connected with a CTRL pin of the high-speed analog switch 130, and sends a switching signal to the high-speed analog switch 130 by controlling the state of the CTRL pin; when the trigger signal 110 is a power-on signal, the EMMC controller 120 controls the pin CTRL of the high-speed analog switch 130 to switch to the state "0", so that the CMD, RST, CLK, Strobe, D0, D1, D2, and D3 of the EMMC interface are connected to the external MCU140, that is, the EMMC memory 150 is electrically connected to the external MCU140, and performs read-write operation; when the trigger signal 110 is a destruction signal, the EMMC controller 120 first performs a 2S delay debounce operation on the trigger signal 110 to prevent an erroneous operation, and after the destruction signal is confirmed, the EMMC controller 120 controls the pin CTRL of the high-speed analog switch 130 to switch to the state "1", the CMD, RST, CLK, Strobe, D0, D1, D2, and D3 of the EMMC interface are electrically connected to the EMMC controller 120, that is, the EMMC memory 150 is electrically connected to the EMMC controller 120, and a reset command is sent through the RST pin to reset the EMMC memory 150, and after the reset is completed, data in the EMMC memory 150 is erased.

Fig. 4 shows a flowchart of the logical destruction method for the EMMC memory, which includes the following steps:

step 210, powering on, namely powering on the logic destruction system of the EMMC;

step 220, reading the destruction flag bit, and reading the state of the data bit corresponding to the pin CTRL;

step 230, destroy enable, to determine whether the data in the EMMC memory 150 is being destroyed before power off, if yes, go to step 270 to continue erasing the BLOCK in the memory; otherwise, go to step 240;

step 240, destruction triggering detection, which is to detect whether the triggering signal is a destruction signal;

step 250, judging whether the duration time of the destruction signal is longer than 2 seconds, if not, returning to the step 240 of continuously detecting the type of the trigger signal; if yes, go to step 260;

step 260, setting a destruction flag bit, namely setting a data bit corresponding to the pin CTRL to be 1;

step 270, erasing Block, and erasing data in the EMMC memory 150;

step 280, judging whether the whole-disk erasing is finished, if not, returning to continue to execute the step 270 to continuously erase the data in the EMMC memory 150; if yes, go to step 290;

and 290, clearing the destroying flag bit, and setting the data bit corresponding to the pin CTRL to be 0 after destroying is finished.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (7)

1. The logic destruction system of the EMMC memory is characterized by comprising a trigger signal, an EMMC controller, a high-speed analog switch, an external MCU and an EMMC memory, wherein the trigger signal is electrically connected with the EMMC controller; the EMMC controller receives the trigger signal and sends a switching signal to the high-speed analog switch, and the high-speed analog switch receives the switching signal sent by the EMMC controller and switches the conduction state according to the switching signal to enable the external MCU to be electrically connected with the EMMC memory to perform read-write operation or enable the EMMC controller to be electrically connected with the EMMC memory to perform logic destruction operation.

2. The EMMC memory logic destruction system of claim 1, wherein the trigger signal is a power-on signal or a destruction signal.

3. The EMMC memory logical destruction system of claim 2, further comprising a destruction button that is depressed to send a destruction signal to the EMMC controller.

4. The EMMC memory logic destruction system of claim 1, wherein the EMMC controller is electrically connected to the EMMC memory through an SDIO driver.

5. The EMMC memory logic destruction system of claim 1, wherein the high speed analog switch is SGM 37222.

6. The EMMC memory logic destruction system of claim 5, wherein the EMMC controller is electrically connected to a CTRL pin of the high speed analog switch and sends a switching signal to the high speed analog switch by controlling a state of the CTRL pin.

7. A method for destroying logic of an EMMC memory is characterized by comprising the following steps:

step 210, powering on, namely powering on the logic destruction system of the EMMC;

step 220, reading the destruction flag bit, and reading the state of the data bit corresponding to the pin CTRL;

step 230, destroy enable, to determine whether the data in the EMMC memory 150 is being destroyed before power off, if yes, go to step 270 to continue erasing the BLOCK in the memory; otherwise, go to step 240;

step 240, destruction triggering detection, which is to detect whether the triggering signal is a destruction signal;

step 250, judging whether the duration time of the destruction signal is longer than 2 seconds, if not, returning to the step 240 of continuously detecting the type of the trigger signal; if yes, go to step 260;

step 260, setting a destruction flag bit, namely setting a data bit corresponding to the pin CTRL to be 1;

step 270, erasing Block, and erasing data in the EMMC memory 150;

step 280, judging whether the whole-disk erasing is finished, if not, returning to continue to execute the step 270 to continuously erase the data in the EMMC memory 150; if yes, go to step 290;

and 290, clearing the destroying flag bit, and setting the data bit corresponding to the pin CTRL to be 0 after destroying is finished.

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