CN110232945A - Memory device and its write/erase method - Google Patents
Memory device and its write/erase method Download PDFInfo
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- CN110232945A CN110232945A CN201810182528.3A CN201810182528A CN110232945A CN 110232945 A CN110232945 A CN 110232945A CN 201810182528 A CN201810182528 A CN 201810182528A CN 110232945 A CN110232945 A CN 110232945A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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Abstract
The present invention provides a kind of memory device and its write/erase methods.The memory device includes state buffer, memory array, Memory Controller, interface control circuit and write-in control logic circuit.Interface control circuit is controlled by Memory Controller to execute the operation of data write/erase to memory array and memory array is re-write/wiped in when the operation of data write/erase does not complete.Write-in control logic circuit counts the number for re-writing/wiping and compares retries count value to generate a retries count value and retry critical value to generate consequential signal, and consequential signal is sent to state buffer.State buffer updates stored result position according to consequential signal.Memory Controller reads result position from state buffer, to judge whether the operation of data write/erase succeeds.The present invention can find out whether write/erase operation succeeds, and further learn the extent of deterioration of storage unit.
Description
Technical field
The present invention relates to a kind of memory devices, and especially with regard to a kind of memory device and its write/erase
Method.
Background technique
For memory device (such as flash memory), being repeatedly written to same memory cell will be will cause with erasing
Or even storage unit slack-off to the reading speed of this memory cell is damaged and is not available.However, being write to memory
Enter/erasing operation when, not can confirm that instruction write/erase operation whether successful mechanism.It is corresponding being read from memory
Just the write/erase of discovery at that time operates not successfully when data and reading data and write-in data are not met.
Summary of the invention
Therefore, the present invention provides a kind of memory device and write/erase method, can find out write/erase operation
Whether succeed, and further learns the extent of deterioration of storage unit.
One embodiment of the invention provides a kind of memory device.Memory device includes state buffer, the first storage
Device array, Memory Controller, interface control circuit and write-in control logic circuit.State buffer stores multiple states
Position and one first critical value, wherein those mode bits include a result position.Interface control circuit is controlled by Memory Controller
To execute data write/erase operation to first memory array and start in when the operation of data write/erase does not complete
One retries mode so that first memory array is re-write/be wiped.Control logic circuit is written to count during retrying mode
The number that first memory array is re-write/wiped reads first from state buffer and faces to generate a retries count value
Dividing value is as critical value is retried, to compare retries count value and retry critical value to generate a consequential signal, and by consequential signal
It is sent to state buffer.State buffer is according to consequential signal come more result position.Interface control circuit is read from state buffer
It takes result position and is sent to Memory Controller, and Memory Controller judges that data write/erase is operated according to result position
Whether succeed.
One embodiment of the invention provides a kind of write/erase method, is used for a memory device.This write/erase side
Method is the following steps are included: one write-in of transmission enables the flash memory of instruction to memory device, to indicate that flash memory will be written into/wipe；
It transmits a write/erase to instruct to flash memory, to execute data write/erase operation to the first memory array in flash memory；
It transmits first state buffer and reads instruction to flash memory；It is read and is instructed according to first state buffer, it is temporary from the state in flash memory
Storage reads a busy bit；According to busy bit, judge whether data write/erase operation is completed；When judging this
When the operation of data write/erase is completed, one second state buffer of transmission reads instruction to flash memory；It is temporary according to the second state
Device reads instruction, reads a result position from state buffer；And judge that data write/erase is operated according to result position
Whether succeed.
The present invention can find out whether write/erase operation succeeds, and further learn the extent of deterioration of storage unit.
For above-mentioned purpose of the invention, feature and advantage can be clearer and more comprehensible, a preferred embodiment is cited below particularly, and match
Appended schema is closed, is described in detail below.
Detailed description of the invention
Fig. 1 shows display devices according to an embodiment of the invention.
Fig. 2 indicates mode bit according to an embodiment of the invention.
Fig. 3 indicates the flow chart of write/erase method according to an embodiment of the invention.
Fig. 4 indicates the flow chart of write/erase method according to another embodiment of the present invention.
Drawing reference numeral
1~memory device；
10~Memory Controller；
11~flash memory；
110~interface control circuit；
111~state buffer；
111A~state storage circuitry；
111B~state keeps in controller；
111C~latch circuit；
112~write-in control logic circuit；
112A~retryCounter；
112B~buffer；
112C~comparator；
113~write protection logical AND row decoding circuit；
The decoding of 114~column and buffer circuit；
115,116~memory array；
ADD~address signal；
Bstatus~mode bit；
Comm10~instruction；
D112A~retries count value；
D112C~consequential signal；
D100A, D100B~control signal；
Din~input data；
Dout~reading data；
S0 ... S16~mode bit；
S30 ... S36~step；
S40, S41~step.
Specific embodiment
The example of multiple embodiments of the invention will be explained referring to correlative type below.
Fig. 1 is to indicate memory device according to an embodiment of the invention.Refering to fig. 1, memory device 1 includes memory
Controller 10 and memory 11.Memory 11 can be a nonvolatile memory, such as flash memory.Memory 11 includes interface control
Circuit 110 processed, state buffer 111, write-in control logic circuit 112, write protection logical AND row decoding circuit (write
Protection logic and decoding row circuit) 113, column decoding with buffer circuit (column
Decoding and buffer circuit) 114, memory array 115 and 116.10 send instructions of Memory Controller
Comm10 is to interface control circuit 110 by control flash memory 11.10 send instructions of Memory Controller are to interface control circuit 110
Comm10 is instructed to can be the enabled instruction of reading, write-in enables instruction, reads instruction, write/erase instruction, the reading of state buffer
Instruction fetch etc..Interface control circuit 110 is then decoded the instruction received to transmit control signal and/or address and believe
Number to state buffer 111, write-in control logic circuit 112, write protection logical AND row decoding circuit 113 and/or column solution
Code and buffer circuit 114, control its operation whereby, are operated with being read out, being written or wipe etc..In this embodiment, interface
Control circuit 110 is a tandem perimeter interface (serial peripheral interface, SPI) control circuit.Citing comes
It says, memory device 1 is then SPI Flash.Detailed operation will describe below with explanation.
State buffer 111 includes state storage circuitry 111A, the temporary controller 111B of state and latch circuit
111C.State storage circuitry 111A stores the mode bit of the mode of operation about flash memory 11.These mode bits pass through memory control
Device 10 processed is kept in the control of controller 111B to interface control circuit 110 and state and is written to state storage circuitry 111A.
When Memory Controller 10, which transmits a state buffer, reads instruction to interface control circuit 110, state keeps in controller
111B is controlled by interface control circuit 110 and executes status read operation to state storage circuitry 111A.At this point, being stored from state
The mode bit of circuit 111A is temporarily stored into latch circuit 111C.Interface control circuit 110 reads mode bit from latch circuit 111C, and
The mode bit Bstatus of reading is sent to Memory Controller 10.For example, shape is transmitted according to interface control circuit 110
The sequence of state position.First group of coding includes position S0~S7, respectively BYSY, WEL, BP0, BP1, BP2, T/B, SEC, SRP0.Its
In, BUSY is busy bit, indicates whether flash memory 10 is just executing the operation of data write/erase；WEL is that enabled bolt-lock is written
The position (write enable latch), indicates whether write operation is enabled；It BP0, BP1, is that block protects (block with BP2
Protect) position provides the control and protection of write protection；T/B is that up/down block protects (top/bottom block
Protect) position, control zone block protection position (BP0, BP1 and BP2) are the upper block or lower block for memory array；
SEC is that section/block protects the position (sector/block protect), and control zone block protection position (BP0, BP1 and BP2) is
Protection is in the upper block of memory array or the section or block of lower block；SRP0 is state buffer guard bit, and instruction is
It is no first group of coding (position S0~S7) to be written.
Second group of coding includes position S8~S15, respectively SRP1, QE, P/F, LB1, LB2, LB3, CMP, SUS.Wherein,
SRP1 is state buffer guard bit, indicates whether that second group of coding (S8~S15) of energy is written；QE is that four ray modes make
Energy (quad enable) instructs SRP, indicates whether enabled four line SPI operation；P/F indicates result position, indicates that data are write
Enter/whether erase status succeed；LB1, LB2, LB3 are temporary locking positions (security register lock) safely, are mentioned
Safe buffer is given for write protection control and state；CMP is supplement protection position (complement protect), with position
SEC, T/B, BP2, BP1, it is protected with mono- group of use of BP0 with providing more flexible memory array；SUS is erasing/write-in pause
State (erase/program suspend state) instruction indicates whether to execute one erasing/write-in pause instruction.It is above-mentioned
Position included by first group of coding and second group of coding is only an example embodiment.In other embodiments, the quantity of code set
And the bit quantity in each code set can set or configure according to practical application with sequence, be not limited with that shown in Figure 2.
State storage circuitry 111A, which is also stored, retries critical value for retry operation.When state keeps in 111B pairs of controller
When state storage circuitry 111A executes status read operation, retries critical value and be temporarily stored into latch circuit 111C.Control logic is written
Circuit 112 then retries critical value Dth from latch circuit 111C reading, and is stored in it.
Refering to fig. 1, write-in control logic circuit 112 includes retryCounter 112A, buffer 112B and comparator
112C.During carrying out write/erase operation to memory array 115/116, retryCounter 112A is by from interface
The control of the control signal D100A of control circuit 110 re-writes/wipes to memory array 115/116 during this period to count
The number removed, and retries count value D112A is generated according to count results.Whenever retryCounter 112A obtains retries count value
Retries count value D112A is sent to comparator 112C by D112A.Buffer 112B storage reads from latch circuit 111C's
Retry critical value Dth.When operation is compared in comparator 112C execution, critical value Dth is retried from buffer 112B reading, and compare
Compared with retries count value D112A and retry critical value Dth.Comparator 112C generates consequential signal D112C according to comparison result, and
It is sent to state buffer 111.The state of state buffer 111 keep in controller 11B then according to consequential signal D112C come
State storage circuitry 111A is written, to update result position P/F (S10).
The write/erase for illustrating memory device 1 by FIG. 1 to FIG. 4 is operated below.
When being intended to write data into memory array 115, memory device 1 is into during the operation of data write/erase.?
During data write/erase operates, the enabled instruction of the transmission write-in of Memory Controller 10 is to interface control circuit 110, with instruction
Write/erase operation enables.Memory Controller 10 then transmits write/erase instruction and input data Din to interface
Control circuit 110.Interface control circuit 110 is decoded the write/erase instruction received.At this point, interface control circuit
110 state of a controls keep in the position BUSY (S0) that controller 111B setting state storage circuitry 111A is stored, and are at instruction
The positive state (such as S0=1) for executing the operation of data write/erase.Interface control circuit 110 more transmits corresponding address signal
ADD and control signal D100B are to write protection logical AND row decoding circuit 113.Write protection logical AND row decoding circuit 113
The content of input data Din is written into memory array 115 according to address signal ADD and control signal D100B
Particular memory location.During the operation of data write/erase, whenever to the progress write-once/wiping of memory array 115/116
It removes, 10 control interface control circuit 110 of Memory Controller holds memory array 115 with buffer circuit 114 by arranging decoding
One read operation of row reads data Dout to read one from the particular memory location of corresponding address signal ADD, and memory controls
Device 10 judges to read whether data Dout meets input data Din.Judge that reading data Din is not inconsistent in Memory Controller 10
When closing input data Dout, Memory Controller 10 then judges that the operation of this data write/erase does not complete, and starting retries mould
Formula.Under the mode that retries, 10 control interface control circuit 110 of Memory Controller re-writes/wipes to memory array 115
It removes.At this point, the transmission control signal D100A to retryCounter 112A of interface control circuit 110, is started counting herein with controlling it
The number that memory array 115/116 is re-write/wiped during write/erase.Judge until in Memory Controller 10
Read that data Din is consistent with input data Dout or one default retries at the end of period (i.e. until the data write-in/wiping out
When being completed except operation), the end of Memory Controller 10 retries mode.At the end of retrying mode, retryCounter 112A stops
It counts, and retries count value D112A is sent to comparator 112C.Later, retryCounter 112A is controlled by Interface Controller electricity
Road and reset.Comparator 112C then generates consequential signal D112C according to comparison result, to update P/F S10 of result.In addition,
When data write/erase, which operates, to be completed, 110 state of a control of interface control circuit keeps in controller 111B more new state storage electricity
The position the BUSY S0 that road 111A is stored is at and indicates non-positive state (such as the S0=for executing the operation of data write/erase
0)。
During the operation of data write/erase, Memory Controller 10 transmits a state buffer and reads instruction (the first shape
State buffer reads instruction) to interface control circuit 110, to be read by interface control circuit 110 from state storage circuitry 111A
Take position S0~S7 in mode bit Bstatus.Memory Controller 10 judges that data write/erase is grasped according to BUSY (S0)
It is completed.At this point, Memory Controller 10 transmits another state buffer reading instruction, (reading of the second state buffer refers to
Enable) to interface control circuit 110, to pass through interface control circuit 110 from state storage circuitry 111A reading state position Bstatus
In position S8~S15.Memory Controller 10 judges whether the operation of data write/erase succeeds according to P/F (S10).
In general, read-write to this memory cell will be will cause with wiping by being repeatedly written to same memory cell
It slows, the data of write error, write/erase fail, even storage unit is damaged and is not available.Memory retries
Mode is that storage unit is re-write/wiped, and is written correctly into input data to memory array with expectation.Work as storage unit
Impaired degree is more serious, and the number that memory cell is re-write/wiped is more, that is, time for re-writing/wiping
Several degree being damaged to storage unit are associated (directly proportional).Therefore, according to embodiments of the present invention, by comparing retries count value
D112A judges whether the operation of data write/erase succeeds with critical value Dth is retried, and whether to use speculative memory array
It damages and can't bear to use, in this way, which the system of application memory device 1 can first carry out some preventions before loss becomes serious
Mechanism.For example, when judging that the operation of data write/erase is failed, then control interface controls Memory Controller 10
Circuit 110, which is switched to, executes the operation of data write/erase to another memory array 116.
In one embodiment, the critical value Dth that retries of state storage circuitry 111A storage is default threshold value, can be system
(i.e. appearance write/erase retries counting to retries count value corresponding when the damage of estimated memory array after making quotient after tested
Value).Therefore, when retries count value D112A arrival retries critical value Dth, memory array 115, which is considered as, have been damaged, and data
Write/erase operation is failed.In another embodiment, after the factory of memory device 1, another critical value can be written to shape
State storage circuit 111A is to replace default threshold value to retry critical value Dth as new.This is new retry critical value Dth be less than it is silent
Recognize critical value, for example, percent 70 (70%) of default threshold value.In the case, when judge data write/erase grasp
When making failed, memory array 115 is not yet damaged, and input data may be written correctly into memory array 115.This
When, Memory Controller 10 can by read P/F come it is preparatory learn the current state of memory array 115 close to damage,
And further execute prevention operation, such as be switched to another memory array 116 is read out or write/erase operation.
Fig. 3 is to indicate write/erase operation according to an embodiment of the invention.When data write/erase to be executed operates
When, the enabled instruction of one write-in of the transmission of Memory Controller 10 is to flash memory 11 (step S30), to indicate that flash memory 11 will be written into/wipe
It removes.Then, Memory Controller 10 transmits write/erase and instructs to flash memory 11 (step S31).Flash memory 11 receive write-in/
After erasing instruction, write/erase instruction is decoded, will be come from controlling write protection logical AND row decoding circuit 113
The input data Din of Memory Controller 10 is written to corresponding storage unit.During the operation of data write/erase, storage
Device controller 10 transmits a state buffer and reads instruction (first state buffer read instruction) to flash memory 10 (step S32),
And from position S0~S7 (step S33) in 111 reading state position Bstatus of state buffer.Then, Memory Controller 10 is sentenced
Whether be disconnected BUSY (S0) in logic state " 1 " (BUSY=1?), to judge whether the operation of data write/erase is completed
(step S34).
When being in logic state " 1 " (BUSY=1) for BUSY (step S34- is), Memory Controller 10 judges data
Write/erase operation is still carrying out, and not yet completes.At this point, write/erase operating method returns to step S32, to continue to read
Whether BUSY be completed to judge that data write/erase operates.When BUSY it is non-be in logic state " 1 " (i.e. BUSY
=0) when (step S34- is no), Memory Controller 10 judges that the operation of data write/erase is completed.Then, memory controls
Device 10 transmits another state buffer and reads instruction (the second state buffer reads instruction) to flash memory 10 (step S35), with logical
Interface control circuit 110 is crossed from position S8~S15 in state storage circuitry 111A reading state position Bstatus.Memory control
Device 10 checks the logic state (step S36) of P/F (S10), and judges that data are write according to the logic state of P/F (S10)
Enter/whether erasing operation succeed.
In another embodiment, be intended to change it is above-mentioned retry critical value, then need to be before entering the operation of data write/erase
It completes.Refering to Fig. 4, the enabled instruction of one write-in of the transmission of Memory Controller 10 to flash memory 11 (step S40), to indicate that flash memory 11 will
It is written into/wipes.Memory Controller 10 then transmits a write state buffer and instructs to flash memory 11 (step S41).Flash memory
11 interface control circuit 110 then instructed according to write state buffer keep in controller 111B come state of a control will be new critical
Value write-in is to state storage circuitry 111A, to replace default threshold value to retry critical value Dth as new.Later, work as memory
When the data write/erase to be executed of device 1 operates, then step S30~S36 in Fig. 3 embodiment is executed.Narration is omitted herein.
According to embodiments of the present invention, the 110 received mode bit Bstatus of institute of interface control circuit of SPI Flash 1, which has, closes
In write/erase operation by/failure position (P/F), by its place value it can be seen that the current state of memory array 115 whether
Close to damage.In addition, SPI Flash 1 also have it is one critical equal to a percentage of appearance write/erase retries count value
Value, as the foundation for updating P/F.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can change and retouch, therefore protection scope of the present invention is when view
Subject to as defined in claim.
Claims (15)
1. a kind of memory device characterized by comprising
One state buffer stores multiple mode bits and one first critical value, wherein multiple mode bit includes a result
Position；
One first memory array；
One Memory Controller；
One interface control circuit is controlled by the Memory Controller to execute a data write-in/wiping to the first memory array
Except operation and in when the data write/erase operation do not complete when starting one retry mode with to the first memory array again
Write/erase；And
One write-in control logic circuit, what counting re-write/wipes to the first memory array during this retries mode
Number reads first critical value to retry critical value as one to generate a retries count value, from the state buffer, compares
The retries count value retries critical value with this to generate a consequential signal, and the consequential signal is sent to the state buffer；
Wherein, which updates the result position according to the consequential signal；And
Wherein, which reads the result position from the state buffer and is sent to the Memory Controller, and should
Memory Controller judges whether data write/erase operation succeeds according to the result position.
2. memory device as described in claim 1, which is characterized in that
Wherein, during data write/erase operation, which transmits an input data, and controls the interface
It is multiple specific to the first memory array being written the input data that control circuit executes data write/erase operation
Storage unit；
Wherein, during data write/erase operation, which controls the interface control circuit and first deposits to this
Memory array executes a read operation to read data from multiple particular memory location, and judges that the reading data are
It is no to meet the input data；And
Wherein, when the Memory Controller judges that the reading data do not meet the input data, Memory Controller judgement
Data write/erase operation does not complete, and starts one and retry mode to control the interface control circuit to the first memory
Array re-writes/wipes.
3. memory device as described in claim 1, which is characterized in that the state buffer includes:
One state storage circuitry stores first critical value and multiple mode bit, wherein multiple mode bit includes indicating
The data write/erase operates the busy bit whether being carrying out；
One latch circuit couples the state storage circuitry；
One state keeps in controller, to the state storage circuitry execute a status read operation so that first critical value and
Multiple mode bit reads out to the latch circuit；
Wherein, which reads first critical value from the latch circuit, and the interface control circuit certainly should
Latch circuit reads multiple mode bit.
4. memory device as described in claim 1, which is characterized in that
Wherein, when the Memory Controller, which sends a critical value setting, to be instructed to the interface control circuit, Interface Controller electricity
It controls the temporary controller of the state one second critical value is written to the state storage circuitry；And
Wherein, after second critical value is written to the state storage circuitry, the write-in control logic circuit is temporary from the state
Device reads second critical value to retry critical value as this.
5. memory device as claimed in claim 4, which is characterized in that first critical value is higher than second critical value.
6. memory device as described in claim 1, which is characterized in that the write-in control logic circuit includes:
One retryCounter is controlled by the interface control circuit, and to count, the memory array is again during this retries mode
The number of write/erase is to generate the retries count value；
One buffer stores this and retries critical value；And
One comparator, couple the retryCounter and the buffer with receive respectively the retries count value and this retry it is critical
Value, and compare the retries count value and this retries critical value to generate the consequential signal.
7. memory device as described in claim 1, which is characterized in that further include:
One second memory array；
Wherein, the data write-in/wiping to the first memory array is judged according to the result position when the Memory Controller
Except operate it is unsuccessful when, the Memory Controller control the interface control circuit be switched to the second memory array execute should
The operation of data write/erase.
8. memory device as described in claim 1, which is characterized in that the memory device is set to the sudden strain of a muscle of a tandem perimeter interface
It deposits.
9. a kind of write/erase method is used for a memory device characterized by comprising
One write-in of transmission is enabled to be instructed to a flash memory of the memory device, to indicate that the flash memory will be written into/wipe；
A write/erase is transmitted to instruct to the flash memory, in the flash memory a first memory array execute a data write-in/
Erasing operation；
It transmits a first state buffer and reads instruction to the flash memory；
It is read and is instructed according to the first state buffer, read a busy bit from the state buffer in the flash memory；
According to the busy bit, judge whether data write/erase operation is completed；
When judging that data write/erase operation is completed, one second state buffer of transmission reads instruction to the flash memory；
It is read and is instructed according to the second state buffer, read a result position from the state buffer；And
Judge whether data write/erase operation succeeds according to the result position.
10. write/erase method as claimed in claim 9, which is characterized in that further include:
During data write/erase operation, an input data is written to multiple spies of a memory array in the flash memory
Determine storage unit；
During data write/erase operation, data are read from multiple particular memory location；
Judge whether the reading data meet the input data；
When the reading data do not meet the input data, judge that data write/erase operation does not complete, and start one and retry
Mode is to re-write/wipe to the memory array.
11. write/erase method as claimed in claim 10, which is characterized in that the result position is according to the memory array
Whether the retries count value for re-writing/wiping reaches one and retries critical value to determine.
12. write/erase method as claimed in claim 11, which is characterized in that further include:
It transmits a write state buffer to instruct to the flash memory, this is written, to retry a state of the critical value into the flash memory temporary
Device.
13. write/erase method as claimed in claim 11, which is characterized in that the retries count value and the storage array
Extent of deterioration is directly proportional.
14. write/erase method as claimed in claim 9, which is characterized in that the result position is stored in the shape in the flash memory
State buffer.
15. write/erase method as claimed in claim 9, which is characterized in that the memory device is set to a tandem perimeter interface
Memory device.
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Cited By (1)
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