JP2001056787A - Device and method for write for memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high reliability memory writer for preventing a program from being incompletely written as much as possible and surely performing the version-up or change of the program by discriminating a password and the number of times of write corresponding to a memory write request and discriminating the completion of write from the coincidence of data when running the program after write. SOLUTION: A memory 5 for program storage is provided with an erasure/ write inhibit block B1. The erasure and write inhibit block B1 is provided with a write discriminating processing means 6f having a password verifying means 6g, a write time storage means 6d for storing the number of times of write and a completion time storage means 6e for storing the number of times of write completion. Corresponding to the memory write request from an external controller 7, the password and the number of times of write in the write time storage means 6d are discriminated, and when running a program after write, it is discriminated from the coincidence of data between the write time storage means 6d and the completion time storage means 6e whether write is completed or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory writing device having a built-in CPU and a memory for storing a program, and a writing method therefor. More specifically, the present invention relates to a program for storing a program stored in a rewritable nonvolatile memory. 1. Field of the Invention The present invention relates to a memory writing device and a writing method for enabling a change.

[0002]

2. Description of the Related Art Conventionally, some program storage memories require that the memory be removed from an IC socket to rewrite the program when the program is changed. In this case, there is a problem that it takes time to insert / remove from the IC socket, and the signal processing and the signal processing for each destination are performed, such as a case where a relatively frequent version upgrade is performed and a display device which is shipped to countries around the world. Efficient use of non-volatile memory, such as flash memory, which can be electrically erased and written and whose program can be changed while mounted on the socket, such as small-quantity multi-products with different specifications such as display and products just after development Have been. FIG. 7 shows a conventional example. Hereinafter, a case where a program change such as an upgrade of an apparatus using a flash memory as a program storage memory will be described with reference to the drawings. 51 is a display device, 52 is a CPU,
53 is a communication means. The communication unit 53 transmits and receives commands and data to and from the external control device 57 using a protocol such as RS232C. 54 is a RAM, and CP
It is used for registers and data buffers necessary for controlling U52. Reference numeral 55 denotes a program storage memory, for example, a RAM or an electrically erasable / writable flash memory can be used. In the case of a flash memory, the inside is divided into several blocks or sectors, for example, from B51 to B57. 5
Reference numeral 6 denotes a write control program, which is arranged in, for example, the above-described block B51 and has a memory control program 56a for controlling erasing / writing of a program storage memory therein, and performs data transmission / reception by communication with an external control device. The communication control program 56b stores the stored program code in R
A transfer program 56c to be transferred to the AM is stored. In the above configuration, when a program needs to be changed, the CPU 5 receives a command from the external control device 57.
2 receives program data from the external control device 57 by the communication control program 56b through the communication means 53,
Once buffered in the RAM 54, the memory control program 5
The program data is written to the program storage memory 55 by 6a. After writing, the program stored in the program storage memory 55 may be executed.

[0003] However, even when a flash memory is used, the conventional control method has the following problems to be solved. First, if a failure such as a power failure or a drop in power supply voltage occurs during execution of a flash memory rewriting program, data being transferred may be destroyed. In addition, since writing to the flash memory takes a long time, there is a possibility that the power supply may be erroneously cut off before the completion. In particular, when a person unfamiliar with handling performs a writing operation, there is a risk of handling mistakes as described above, and writing a program with a different purpose or a program with a different specification and version from the destination. . Furthermore, when a flash memory is used, there is a limit on the number of times of erasing / writing that is allowed. If erasing / writing is performed more than a predetermined number of times, data may not be written correctly. Was. If the program stored in the program storage memory is executed in an incomplete state as described above, a problem may occur or the program may run away, and in the worst case, the device may be destroyed. In addition, the memory control program and the communication control program for writing the contents of the program storage memory are changed to the erase / write-inhibited block in the storage section of the memory control program and the communication control program as conventionally performed. No
In addition, if it is included in the part to be rewritten, it will not be possible to transfer the program itself if the writing is incomplete.
There was also a problem.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been described in consideration of a power failure during a writing operation, an inexperienced operator performing an inadvertent writing operation, and a number of writing operations of a memory element. To provide a highly reliable memory writing device and a writing method for the same that can prevent program writing from being performed incompletely due to, for example, exceeding a limit, and can reliably upgrade or change the version of the program. It is intended to be.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a CPU, communication means connected to the CPU for transmitting and receiving data to and from an external control device, and built-in or connected to the CPU. And a program storage memory comprising a plurality of blocks, wherein the program storage memory has a communication control program for controlling communication and a memory control for erasing and writing the program storage memory. A transfer program for transferring a program and a stored program code to a RAM, wherein at the time of writing, the communication control program and the memory control program are arranged in the RAM by the transfer program; A memory writing device for transferring and writing data to the program storage memory; A memory for storing the memory control program, the communication control program, the transfer program, a write determination processing unit, a write count storage unit for storing the write count, and a completion count storage unit for storing the write completion count in a memory for storing the program. The above object is achieved by providing at least one erase / write prohibition block having the following.

Further, the program storage memory is constituted by an electrically erasable / writable nonvolatile memory.

In order to reduce the number of erasures, a program to be written into the program storage memory is completely arranged in each block unit of the program storage memory. It has a jump table to the main internal programs.

A CPU, communication means connected to the CPU for transmitting and receiving data to and from an external control device, and a RAM built in or connected to the CPU and a program storage memory comprising a plurality of blocks. Prepared,
The program storage memory includes a communication control program for controlling communication, a memory control program for erasing and writing the program storage memory, and a transfer program for transferring stored program codes to the RAM. During writing, the transfer program causes the communication control program and the memory control program to be stored in the RA.
M, and transfers data from the external control device to the program storage memory for writing. In the program storage memory, the memory control program, the communication control program, At least one erase / write-inhibiting block comprising a transfer program, a write determination processing means, a write count storage means for storing a write count, and a completion count storage means for storing a write completion count is provided. In response to a memory write request from a control device, the write determination processing means sets a memory write mode when the number of writes is equal to or less than a predetermined number and the number of writes matches the number of completions, The number of times of writing is increased by one time to execute a writing process, and after completion of writing, the number of times of completion is increased by one time.

The program written in the program storage memory compares data of the number of times of writing and the number of times of completion at the time of execution. Is not executed.

If the data stored in the number-of-writes storage means does not match the data stored in the number-of-completions storage means, the memory write mode is maintained until the data is retransmitted.

[0011] Further, the write count storage means and the completion count storage means are configured such that the increase in the write count erases a bit, and the count is stored by the number of erased bits.

Further, during the memory write mode,
The display for identification is performed.

Further, the write determination processing means includes a password authentication means, and when the passwords do not match, the apparatus does not enter the memory write mode.

Further, the password authentication means issues a passcode in response to a write request from the external control device, and compares the password with a password obtained by a predetermined arithmetic expression based on the passcode. .

[0015] The authentication by the password authentication means is invalidated when the data stored in the number-of-writes storage means matches the data stored in the number-of-completions storage means and is equal to or less than a predetermined number.

Further, the memory control program and the communication control program transfer old data in the program storage memory to the external control device before writing, detect a difference from new data, and The function of erasing and writing only to a certain block can be selected.

Further, when the communication control program transfers write data with the external control device, the communication control program temporarily stores the data in the R.
It is arranged in the AM so that sum checks in the horizontal and vertical directions are performed.

Further, the communication control program increases the communication speed at the time of transferring write data with the external control device as compared with the case of transmitting a command.

Further, the write determination processing means includes a memory determination means, and identifies a type of a memory constituting the program storage memory.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a control unit according to an embodiment showing an embodiment of the present invention. This example shows an example in which a control program for a display device such as a plasma display is written in a program storage memory constituted by a flash memory. A case where a program change such as an upgrade of an apparatus using a flash memory as a program storage memory will be described below with reference to FIG. 1 is a display device, 2 is a CPU, and 3 is a communication means. The communication unit 3 is a serial interface based on RS232C, and transmits and receives commands and data to and from the external control device 7. Reference numeral 4 denotes a RAM, which is used as a register and a data buffer necessary for controlling the CPU 2. Reference numeral 5 denotes a program storage memory, which uses a flash memory that can be electrically erased and written. The program storage memory 5 composed of a flash memory is internally divided into, for example, seven blocks or blocks called B1 to B7 called sectors, and after each block is collectively erased, data is written to an individual address. Is to be included. Reference numeral 6 denotes a write control program stored in the block B1 of the program storage memory 5, and a memory control program for controlling erasing / writing of a flash memory constituting the program storage memory 5. 6a, a communication control program 6b for transmitting and receiving data by communication with the external control device 7, a transfer control program 6c for transferring the memory control program 6a and the communication control program 6b and the like to the RAM at the time of writing, and a program storage memory 5 A write count storage unit 6d for storing the number of writes, a completion count storage unit 6e for storing the number of write completions when writing is completed, and a write determination processing unit 6f are stored. The write determination processing means 6f determines the type of memory mounted on the program storage memory 5, that is, the ROM, RAM, or flash memory, by means of a password authentication means 6g for giving and receiving a password and determining whether or not the password matches. The memory control program 6a and the communication control program 6b at the time of writing determination such as whether the number of times of writing is within an allowable range, permission and writing.
And the like are transferred to a RAM and executed, and comprehensive writing processing such as writing completion processing at the time of writing completion is performed. The details of the number-of-writes storage unit 6d, the number-of-completions storage unit 6e, the password authentication unit 6g, and the memory determination unit 6h will be described later.

When a flash memory is used, the contents of the program storage memory 5 are retained even in the event of a power failure, but the block B1 is particularly prohibited from erasing and writing, and therefore includes the programs 6a to 6h. The write control program 6 is designed to prevent erasure and rewriting. However, only the number-of-writes storage means 6d for storing the number of times of writing and the number-of-completions storage means 6e for storing the number of times of completion of writing when the writing is completed are excluded. Details will be described later. In the above-described configuration, when the program needs to be changed, the CPU 2 determines the password and the memory type and determines the conditions such as the number of writes by the write determination processing unit 6f in response to a command from the external control device 7. Is determined, and if the writing is permitted, the transfer control program 6c
To transfer the contents of the write control program 6 to a predetermined address of the RAM 4, and execute the contents of the write control program 6 on the RAM 4. That is, the CPU 2 receives the program data by the communication control program 6b via the communication means 3,
The data is temporarily buffered in the RAM 4, a sum check is performed, and the program data is transferred and written to the program storage memory 5 by the memory control program 6a. After the writing is completed, the program stored in the program storage memory 5 may be executed.

FIG. 2 shows a control flow of the memory writing method of the present invention. FIG. 2A shows a processing flow of the write control program 6. Actually, the main routine of this program is transferred to the RAM 4 and executed, but the flow of the transfer is omitted. The reason for transferring to the RAM is that writing and reading cannot be performed simultaneously in the flash memory, so that when writing, it is necessary to transfer to another memory for execution. FIG. 2B shows an initial flow of a display control program executed in the program storage memory 5 after the transfer of the program. This will be described with reference to FIG.
When there is a program write request from the external control device 7, first, a password is received and collation is performed (ST1). The collation of the password is performed in order to limit the number of workers and to prevent inadvertent writing or writing errors as much as possible. If the passwords do not match, writing is prohibited (ST2). When the passwords match, the number of times of writing stored in the number-of-times-of-writing storage means 6d provided in the program storage memory 5 is read, and it is confirmed whether the number is within the specification of the memory. The number of writing times of the flash memory used in the present invention is, for example, 100
It is confirmed that the number of times has not exceeded 100 times (ST3). If the number of times has exceeded 100 times, a write-protection or a write-protection alarm is issued (ST18).
If it does not exceed 100 times, writing is permitted and the memory writing mode is started (ST5).

In the memory write mode, first, the number of times of writing is 1
The number of times is increased and stored in the number-of-writes storage unit 6d (S
T6). Next, a changed block to be written is extracted (ST
7). In the case of flash memory, erasing must be performed in block units, and the number of times of erasing and writing is limited.
It is not necessary to rewrite blocks whose write data does not change.
Batch erase only blocks that need to be rewritten (ST
8). When the erasure of the predetermined block is completed (ST9), data reception is performed (ST10). The data is transmitted in units of 256 bytes. At the same time, 2 bytes of address information and 32 bytes of sum check data are transmitted and temporarily buffered in the RAM 4 in a matrix of 16 × 16 bytes.
Thumb checks are performed in each direction. If the sum checks do not match, a retransmission request is made, and the process returns to ST10 (ST11). If the sum check is OK, writing to the flash memory is performed (ST12). In order to shorten the writing time, two buffer areas are secured in the RAM 4 for data transfer, and data is written to one buffer even during data transfer. When the writing of the transmission unit is completed (ST13), and when the writing of all the blocks is completed (ST14), the completion number of the writing completion number storage means 6e is increased by one and stored (ST1).
5). After the above series of processing is completed, the memory write mode is released (ST16), and the process ends (ST17).

Next, FIG. 2B will be described. FIG.
3B shows a processing flow of an initial start portion of the display control program written and stored in the program storage memory 5. First, the number of times of writing stored in the number-of-times-of-writing storage means 6d is read (ST21). Next, the number of completions stored in the number-of-completions storage means 6e is read (ST22),
The two are compared (ST23). If they match, it means that the writing of the program has been completed successfully, and the subsequent display control program is executed (ST24). If they do not match, it can be determined that the writing of the program has been interrupted for some reason. Therefore, the state is set to the memory writing mode (ST25), and a request for retransmission of data is made to the external control device 7 (ST26). The reception standby state is maintained (ST27).

FIG. 3 is an explanatory diagram in the case where the number of times of writing in the program storage memory 5 is determined. The flash memory utilizes the fact that it is not possible to write 1 to a bit of bit data 0, but it is possible to write 0 to a bit of bit data 1. The number-of-writes storage means 6d and the number-of-completions storage means 6e are specifically registers and have a counting function, and are arranged in erasure-inhibited blocks of the flash memory. Therefore, the number of writings from the beginning of manufacturing can be reliably managed. For the storage of the number of times of writing, one bit of a predetermined memory is regarded as one time and each number is managed from the lower bit LSB. To store 100 times, 100 bits each,
Although a total of 32 bytes are required, the block B1 of the program storage memory 5 has a free space for special use, and a sufficient free space of about 1 Kbyte is secured. FIG. 3A shows the number of times of writing stored in the number-of-writings storage means 6d before writing and the number of times of completion of writing stored in the number-of-completions storage means 6e. In the example of FIG. This indicates that there are three write histories. FIG. 3B shows the state during the memory write mode, that is, the state during the write, and shows that the number of times of writing is four and the number of times of completion is three. Therefore, if the writing is interrupted in such a state, the number of times of writing and the number of times of completion are different, so that it can be determined that the writing of the program is incomplete, and the execution of the defective program is prevented, and the runaway is prevented. be able to. FIG. 3C shows a state in which the writing has been completed. Since each of these matches four times, it is determined that the writing has been completed normally, meaning that the written program can be executed. ing.

In the memory writing mode, the green and red power lamps of the display device are repeatedly blinked continuously at different periods so as to be clearly distinguished from other modes. You can call attention. In the case of such a display, the operator determines that there is some kind of writing error, and investigates and confirms a defect, and then performs the writing operation again.

FIG. 4 is a control flow for explaining a control method of the password authentication means 6g for exchanging passwords between the display device 1 and the external control device 7. A description will be given based on FIG. For general password transfer, a specific password is determined in advance, and it is determined whether or not the transmitting side and the receiving side match. In the memory writing device and the writing method of the present invention, the following method is used. And First, the external control device 7 issues a memory write request to the display device (S
T31). When the display device 1 receives the write request (ST
32) First, a passcode is internally extracted and transmitted (S)
T33). The passcode is extracted from the random function generator and is different each time the operation is performed. When the external control device 7 receives the passcode (ST34), it calculates a password based on the passcode by a certain procedure and an arithmetic expression (ST36), and displays the calculated password on the display device 1.
(ST37). The same program for calculating the password is also incorporated in the display device 1, and the display device 1 also calculates the password (ST35), collates the received password with the received password (ST38), and outputs the password collation result to an external control device. 7 (ST39). The external control device 7 proceeds to the data transmission process step (ST41) if the passwords match according to the received password collation result, and ST31 if the passwords do not match.
And a write request is made again if necessary. In the display device 1, when the passwords match (ST
42), the process proceeds to the data receiving step (ST43), and if there is no match, the process returns to the standby state of ST32.

By adopting the password authentication method as described above, version number management such as program change can be made more reliable. In the conventional management method using only a password, there is a risk that an unspecified operator may rewrite a program due to leakage of only the password. According to the present invention, the writing operation can be performed only by a specific person who owns a writing program containing the same program as the program in the display device.
In addition, more strict version number management can be performed by changing the writing program for each version or each sales destination such as an OEM, or by combining with a normal password.

In the memory writing method according to the present invention,
If the number of times of writing is less than three, the password authentication step is passed so that writing can be performed without a password. This is because the program data at the time of adjustment in the factory process and the final shipment may be different,
In a factory, workers and procedures are limited, so that unnecessary labor such as inputting a password is reduced. Therefore, at the time of shipment, the number of times of writing and the number of times of completion are set to numerical values of 3 or more.

When rewriting the program data,
Prior to the writing process, the version of the old data stored in the program storage memory 5 is read, transferred to the external control device 7, and compared with the version of the new data to be rewritten. In addition, it is possible to select a function of reading the old data itself stored in the program storage memory 5, transferring the old data to the external control device 7, and comparing it with the contents of the new data to be rewritten. As a result of the comparison, only the blocks that have changed are targeted for rewriting. By doing so, it is possible to prevent mistakes in writing the same data repeatedly, and it is possible to extend the service life by minimizing the number of write blocks to a necessary minimum.

FIG. 5 is a diagram for explaining a sum check when transferring program data. The transferred program data is temporarily stored in a predetermined buffer area of the RAM 4 in a matrix. Although two systems are prepared for the buffer area so that they can be transferred simultaneously during writing to the memory, only one system is shown in the figure. Numerical values in FIG. 5 indicate the order in which the transferred data is stored. As shown in the figure, 256 bytes of data are arranged in a matrix of 16 bytes × 16 bytes. After the transfer of 256 bytes of data, a 16-byte checksum of x1 to x16 in the horizontal direction and a 16-byte checksum of y1 to y16 in the vertical direction are transferred to the transferred data, and each checksum is performed. . The reliability is further improved by performing the sum check in the horizontal direction x and the vertical direction y. In addition,
By performing strict checks during data transfer, RA
During the transfer of data to M4, the communication speed is doubled as compared with the transmission and reception of the command, so that the transfer time is shortened.

FIG. 6 is a view for explaining a determination method by the memory determination means 6h for determining the type of the memory of the program storage memory 5. Program storage memory 5 for writing
Is written so as to invert the bit of the data content to the address including the specific 1 and 0, and the type of the memory is determined based on the result. The program storage memory 5 may be any of electrically writable memories such as a ROM, a RAM, and a flash memory. In some cases, these may be mixed, or at the beginning of development, the ROM may be used. The case of shifting to a flash memory and vice versa may be considered. The method described below shows an example of a method that can be determined even when memories are mixed. FIG. 6A shows a case of a ROM. It is impossible to write inverted data with respect to data before writing, and the same data is obtained before and after writing. Fig. 6 (2)
Shows the case of a flash memory. Bit data 1 can be written to 0, but bit data 0 cannot be set to 1. The bit data is set to 1 because only the erase command is used. Therefore, it is possible to identify whether bit data 1 changes to 0. FIG. 6 (3)
Is the case of a RAM, and can be determined as a RAM since reverse writing is possible. By employing the above-described determination method, it is possible to freely select a memory to be used for the program storage memory 5 while keeping the write control program 6 common, and it is not necessary to write data into the ROM. The operation can be omitted, and writing can be performed only in a necessary memory portion.

In the program written in the program storage memory 5, even if only one program code is increased or decreased, for example, depending on the configuration, the arrangement of the program after the changed part is shifted, and all blocks are rewritten. All blocks including a program that directly becomes a target or a program that directly refers to a program to be changed become a target of rewriting. In order to reduce the number of times of erasing and rewriting due to these factors, the program to be arranged in the program storage memory 5 is completely arranged in units of blocks, and is transferred from the external block to the internal main program of each block. Is referred to via a jump table arranged at a specific location. Even if the content of the jump table is changed, if the jump table itself is not changed, the change is limited to only the target block, and the number of erasures / rewrites can be reduced. As mentioned above, although one Example of this invention was described, this invention is not limited to this Embodiment, It cannot be overemphasized that various forms can be employ | adopted in the range which does not deviate from the summary. .

[0034]

As described above, according to the memory writing device and the writing method thereof according to the present invention, at least one erase / write inhibit block is provided in the program storage memory, and the erase / write inhibit block is provided. A memory control program, a communication control program, and a write determination processing unit having a password authentication unit; a write count storage unit for storing the write count; and a completion count storage unit for storing the write completion count. In response to a memory write request from an external control device, the password and the number of times of writing in the number-of-writes storing means are determined. By judging whether or not writing has been completed by matching of the data, an inexperienced operator may perform an inadvertent writing operation, a power supply error during writing, or a memory element failure. Incomplete writing of a program due to, for example, the number of times of writing exceeding the limit is prevented as much as possible, and it is easy to upgrade and change the program, and a highly reliable memory writing device and its writing method are provided. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory writing device and a writing method according to the present invention.

FIG. 2 is a control flow of an embodiment of a memory writing device and a writing method according to the present invention.

FIG. 3 is an explanatory diagram of the number of times of writing in the memory writing device and the writing method according to the present invention.

FIG. 4 is an explanatory diagram for explaining transmission and reception of a password in the memory writing device and the writing method according to the present invention;

FIG. 5 is an explanatory diagram for explaining a memory writing device and a data checking method of the writing method according to the present invention;

FIG. 6 is an explanatory diagram for explaining a memory writing device and a method of determining a memory type in the writing method according to the present invention;

FIG. 7 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Display apparatus 2 CPU 3 Communication means 4 RAM 5 Program storage memory 6 Write control program 6a Memory control program 6b Communication control program 6c Transfer control program 6d Number of times of writing storage means 6e Number of times of completion storage means 6f Write determination processing means 6g Password authentication means 6h Memory determination means 7 Control device 51 Display device 52 CPU 53 Communication means 54 RAM 55 Program storage memory 56 Write control program 56a Memory control program 56b Communication control program 56c Transfer control program B1-B7 blocks B51-B57 blocks

Claims (15)

[Claims] 1. A CPU, communication means connected to the CPU for transmitting and receiving data to and from an external control device, RAM built in or connected to the CPU, and a program storage memory comprising a plurality of blocks. A communication control program for controlling communication, a memory control program for erasing and writing the program storage memory, and a transfer program for transferring the stored program code to the RAM. When writing, the communication control program and the memory control program are arranged in the RAM by the transfer program, and data from the external control device is transferred to the program storage memory and written. In the memory writing device, the memory for storing the program may be stored in the memory for storing the program. At least one erasure / write-inhibition block comprising a communication control program, the transfer program, write determination processing means, a write count storage means for storing a write count, and a completion count storage means for storing a write completion count. A memory writing device. 2. The memory writing device according to claim 1, wherein the memory for storing the program is constituted by an electrically erasable / writable nonvolatile memory. 3. The program to be written into the program storage memory is completely arranged in each block unit of the program storage memory in order to reduce the number of erasures.
3. The memory writing device according to claim 1, further comprising a jump table to an internal main program for each block referenced from an external block. 4. A CPU, communication means connected to the CPU for transmitting and receiving data to and from an external control device, and a RAM built in or connected to the CPU and a program storage memory comprising a plurality of blocks. The program storage memory includes a communication control program for controlling communication, a memory control program for erasing and writing the program storage memory, and a transfer program for transferring stored program codes to the RAM. A memory for arranging the communication control program and the memory control program in the RAM according to the transfer program at the time of writing, and transferring data from the external control device to the program storage memory for writing In the writing device, the memory for storing the program may be stored in the memory for storing the program. At least one erasure write-inhibit block including a communication control program, the transfer program, write determination processing means, a write count storage means for storing a write count, and a completion count storage means for storing a write completion count. In response to a memory write request from an external control device, the write determination processing means sets a memory when the number of writes is equal to or less than a predetermined number and the number of writes matches the number of completions. A writing mode, and increasing the number of writings by one,
A memory writing method for executing a writing process and increasing the number of completions by one after the writing is completed. 5. The program written in the program storage memory compares data of the number of times of writing and the number of times of completion when executing the program, and when the program does not match, determines that a writing error has occurred and writes the written program. 5. The memory writing method according to claim 4, wherein the method is not executed. 6. The memory write mode is held until the data stored in the number-of-writes storage means and the data stored in the number-of-completions storage means do not match, until the data is retransmitted. Memory writing method. 7. The memory according to claim 1, wherein said number-of-writes storage means and said number-of-completions storage means are configured such that an increase in the number of writes erases a bit, and stores the number of times as the number of erased bits. 7. The memory writing method according to claim 4, wherein: 8. A display for identification is performed during the memory writing mode.
The memory writing method described in the above. 9. The memory writing method according to claim 4, wherein said writing determination processing means includes a password authentication means, and does not enter the memory writing mode when the passwords do not match. 10. The password authentication unit issues a passcode in response to a write request from the external control device,
10. The memory writing method according to claim 9, wherein the password is collated with a password obtained by a predetermined arithmetic expression based on the passcode. 11. The authentication by the password authentication means,
11. The memory writing method according to claim 9, wherein when the data stored in the number-of-writes storage means matches the data stored in the number-of-completions storage means and is equal to or less than a predetermined number, the memory write method is invalidated. 12. The memory control program and the communication control program transfer old data in the program storage memory to the external control device before writing, detect a difference from new data, and 5. The function of erasing and writing only in a certain block can be selected.
9. The memory writing method according to any one of claims 8 to 8. 13. The communication control program according to claim 1, wherein the transfer of the write data to and from the external control device causes the data to be temporarily stored in the RA.
9. The memory writing method according to claim 4, wherein the memory writing method is arranged at M and a sum check in the horizontal and vertical directions is performed. 14. The memory writing method according to claim 12, wherein the communication control program increases a communication speed at the time of transfer of write data with the external control device compared with the time of command transmission. 15. The memory writing method according to claim 4, wherein said write determination processing means includes a memory determination means, and identifies a memory type constituting the program storage memory.