CN111082669A - Method for generating complementary drive signals for a converter and oscillator - Google Patents

Method for generating complementary drive signals for a converter and oscillator Download PDF

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CN111082669A
CN111082669A CN201811231551.3A CN201811231551A CN111082669A CN 111082669 A CN111082669 A CN 111082669A CN 201811231551 A CN201811231551 A CN 201811231551A CN 111082669 A CN111082669 A CN 111082669A
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power tube
driving
output
voltage detection
pulse width
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CN111082669B (en
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崔能伟
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Suzhou Yuante Semiconductor Technology Co ltd
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Suzhou Yuante Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H02M3/3376—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a method for generating complementary driving signals of a converter and an oscillator, wherein the driving process of a power tube is used as a part of the cyclic oscillation of the oscillator, a driving voltage detection module starts to generate dead time and generate a pulse width signal after detecting and judging the turn-off of the power tube, and the next oscillation is performed, so that the whole process is closed loop, and the phenomenon of large dead time error caused by the driving delay of the power tube can be effectively avoided.

Description

Method for generating complementary drive signals for a converter and oscillator
Technical Field
The present invention relates to a method for generating complementary driving signals of a converter and an oscillator, and more particularly, to a method for generating complementary driving signals of a converter and an oscillator.
Background
As shown in fig. 1, the self-excited push-pull converter in the prior art is widely applied to the DCDC isolated converter of the micro-power module due to its characteristics of simple structure, high magnetic flux utilization rate and small size. However, due to some inherent defects of self-excited push-pull and the rapid development of integrated circuit technology in recent years, the self-excited push-pull technology is gradually replaced by the excited push-pull technology of the integrated circuit, because the integrated circuit has better device matching and signal detection and control, the consistency and reliability of the converter can be greatly improved, for example, the low-noise push-pull controller SN6501 proposed by TI.
As shown in fig. 2, push-pull controller SN6501, oscillator OSC generates two complementary logic signals S and S through frequency divider freq
Figure BDA0001837276790000011
Then, two paths of complementary signals G with certain dead time are generated by a BBM Logic module2And G1. Of complementary drive signalsThe generation is from frequency division, then the width of the two signals is the same, the duty ratio is 50%, therefore, the symmetry is extremely high, and the symmetry is independent of the parameters of the oscillator OSC, and it only affects the oscillation period, i.e. the width of the two signals. The high symmetry of the drive is just needed by the push-pull and full-bridge power supply topologies, and the parameters of the MOS transistor Q1 and the MOS transistor Q2 can meet the high consistency, so that the magnetic bias phenomenon of the power supply can be effectively reduced. The BBM Logic module enables two paths of signals to generate dead time, because the MOS transistor Q1 and the MOS transistor Q2 cannot be simultaneously switched on, after one MOS transistor is switched off, the other MOS transistor is switched on for a short time, as shown in fig. 3, tBBMIs the dead time of the drive.
The polarity of the voltage applied by the transformer when the MOS transistor Q1 is on is indicated in FIG. 2, and the primary current enters the winding N from VINP2And MOS transistor Q1 to ground, the secondary current from the secondary windingS1And forward biasing diode D1 to capacitor COAnd charging, the MOS tube Q2 and the diode D2 are in a reverse bias cut-off state. When the MOS transistor Q2 is conducted, energy is transferred from VIn through the primary winding and the secondary winding of the transformer and then stored in the output capacitor C through the forward biased rectifier diode D2OIn the circuit, MOS transistor Q1 and MOS transistor Q2 are switched alternately and repeatedly, and energy is transmitted from primary side VIN to secondary side V of the isolation transformerOUTThe load side that needs to be isolated can obtain the required energy from there.
As shown in fig. 4, the oscillator provides driving timing for two power transistors Q1 and Q2 of the push-pull converter, and the oscillator includes: the pulse width generating module 101, the frequency dividing module 102, two driving modules 103 and the delay circuit 105. The frequency dividing module 102 separates the CLK signal output by the pulse width generating module 101 into two complementary signals S and
Figure BDA0001837276790000025
the two driving modules 103 drive the power tube according to the complementary time sequence under the action of the two paths of complementary signals. The CLK signal is used as the input of the circuit after passing through the NOT and the NAND gates NAND, the NOT and the NAND gates NAND do two times of 'NOT' operation on the CLK signal, and the NOT and the NAND gates are directly connected with the delay circuit 10 logically along with the CLK signalThe input ends Ldi of the two-way drivers 5 are connected in the same way, and NAND gates are specially added for strong contrast, and the function of the NAND gates is to generate time intervals of two paths of complementary driving signals, namely dead time.
As shown in fig. 5, a clock CLK with a set low level width generated by an oscillator is divided to generate two selection signals, and two complementary control signals S and S are separated by two and gates
Figure BDA0001837276790000021
Rising edge of S and
Figure BDA0001837276790000022
or S, or
Figure BDA0001837276790000023
The time width between rising edges of (a) is also a dead time width, i.e., t2 to t3, t4 to t5, and t6 to t7 in the figure. According to S and
Figure BDA0001837276790000024
with the timing provided, the driving circuit turns on the two power transistors Q1 and Q2 at active high level, respectively, generating gate voltage waveforms G2 and G1, respectively. S becomes low level at time t2, the voltage G2 begins to drop after a short time, the voltage is actually turned off until the voltage at time t23 is smaller than the threshold voltage of the power tube Q2, and the voltage is turned off after a while
Figure BDA0001837276790000026
When the voltage level becomes high, the gate voltage G1 of the power transistor Q1 reaches the threshold voltage at time t3, and turns on. It can be seen that the voltage of the gate is gradually reduced, the power transistor is really turned off at the time t23, so that the time from t23 to t2 is consumed due to the driving delay between t2 to t3, and the real dead time is equal to t3 minus t 23. Therefore, due to the poor parameter accuracy or temperature variation of the device, the situation of small dead time and large driving delay is easy to occur, and the phenomenon that the two power tubes are conducted simultaneously is caused.
As shown in FIG. 6, the gate voltage G2 of power transistor Q2 has not dropped below the threshold voltage until t23 ' during the dead time t 2't 3 ', so that both power transistors Q1 and Q2 are common during the time t 3't 32 '.
Whether the oscillator which is designed by adopting the traditional scheme and generates complementary signals or the push-pull controller SN6501 has the common characteristic that the complementary driving signals are generated by the oscillator into two paths of complementary control signals and then transmitted to the driving module to drive the power tube, and the process is open loop, so that the defect of poor consistency exists in practical application. The reason is as follows:
firstly, dead time must exist in the driving of two power tubes of the push-pull converter, otherwise, the phenomenon that the two power tubes are common occurs, and thus, the performance problems of efficiency, EMI, noise and the like exist.
Secondly, in order to reduce the switching noise and EMI of the push-pull converter, a circuit such as a resistor is added to the output of the driving circuit to reduce the driving speed of the power tube, and particularly, the driving delay is large as the chip of the company TI is made to have low noise characteristics.
Third, the dead time of the complementary control signals is generated by a separate circuit, independent of the driver circuit.
Fourthly, although the matching performance between devices in the integrated circuit can be well made, the absolute value of the parameter is not accurate, the precision of the resistor and the capacitor is about +/-20%, and the resistor has a larger temperature coefficient. Therefore, the dead time of the complementary control signals and the time delay generated by the power tube driving circuit are not accurate, the difference value between the dead time and the time delay is the real dead time tBBM of the driving voltage of the two power tubes, and if the dead time of the control signals is smaller, the driving time delay of the power tubes is larger, the common operation is easy to cause.
Fifthly, if the dead time of the control signal is increased, the dead time may become large, and the dead time is too large, so that the actual duty ratio of the power tube becomes small, the output voltage becomes small, and the ripple becomes large.
Moreover, the higher the switching frequency of the converter, the more pronounced the above-mentioned drawbacks.
Disclosure of Invention
To solve the above technical problem, the present invention provides a method and an oscillator for generating complementary driving signals of an inverter. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The invention adopts the following technical scheme:
in some illustrative embodiments, the present invention provides a method for generating complementary drive signals for a transducer, comprising: the driving voltage detection module detects the driving voltage of the currently-switched power tube, and when the driving voltage is detected to be reduced to a set value, the currently-switched power tube is judged to be switched from an on state to an off state; and when the dead time is finished, the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width again so as to drive another power tube to enter an on state.
Wherein the method for generating complementary drive signals for an inverter further comprises: the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width, and drives the two power tubes in a crossed manner within the effective time of the pulse width.
The dead time is generated by the driving voltage detection module or a falling edge single-side delay circuit; and the output of the driving voltage detection module and the output of the falling edge unilateral delay circuit are used as the input of the time sequence pulse width generation circuit module.
In some illustrative embodiments, the present invention also provides an oscillator for generating complementary drive signals for an inverter, comprising: the time sequence pulse width generating circuit module and the frequency divider module further comprise: two drive voltage detection modules for respectively detecting the on/off states of the power tube Q1 and the power tube Q2; the input ports of the two driving voltage detection modules are respectively connected with the gates of the power tube Q1 and the power tube Q2, the output ports of the two driving voltage detection modules are respectively connected with the two input ends of the NAND gate, and the output of the NAND gate is used as the input of the time sequence pulse width generation circuit module.
Wherein the driving voltage detection module includes: a common source amplifier and a Schmitt trigger; the NMOS tube Mtest and a pull-up resistor Rvdd form the common source amplifier, and the grid electrode of the NMOS tube Mtest is used as an input port of the driving voltage detection module; and the Schmitt trigger shapes the output voltage of the common source amplifier and outputs a logic level, and the output logic level is used as the output of the driving voltage detection module.
Wherein the oscillator for generating complementary driving signals of the converter further comprises: and the output end of the NAND gate is connected with the input end of the falling edge single-sided delay circuit, and the output of the falling edge single-sided delay circuit is used as the input of the time sequence pulse width generation circuit module.
Wherein, the driving voltage detection module further comprises: the capacitance Cdelay; one end of the capacitor Cdelay is connected with the input end of the Schmitt trigger, and the other end of the capacitor Cdelay is grounded.
Wherein the oscillator for generating complementary driving signals of the converter further comprises: a P-type power tube P1 and a P-type power tube P2; the grid electrode of the P-type power tube P1 is connected with the output end of a first NOT gate, the input end of the first NOT gate is connected with one path of the output of the frequency divider module, and the drain electrode of the P-type power tube P1 is connected with the drain electrode of the power tube Q2; the grid electrode of the P-type power tube P2 is connected with the output end of a second NOT gate, the input end of the second NOT gate is connected with the other output path of the frequency divider module, and the drain electrode of the P-type power tube P2 is connected with the drain electrode of the power tube Q1.
Wherein the oscillator for generating complementary driving signals of the converter further comprises: two additional drive units; the output end of one additional driving unit is connected with the grid electrode of the P-type power tube P1, and the input end of the additional driving unit is connected with the output end of the first NOT gate; the output end of the other additional driving unit is connected with the grid electrode of the P-type power tube P2, and the input end of the other additional driving unit is connected with the output end of the second NOT gate.
The invention has the following beneficial effects: the driving process of the power tube is used as a part of the cyclic oscillation of the oscillator, dead time is generated and the next oscillation is performed to generate a pulse width signal after the power tube is detected and judged to be turned off, and the whole process is closed-loop, so that the phenomenon that the dead time error is large due to the time delay of the power tube driving can be effectively avoided. The time interval for driving the power tube twice continuously is generated after the driving voltage detection module is actually turned off, so that the time required by the driving circuit to turn off the power tube does not influence the size of dead time, and the driving process belongs to the whole closed loop of the oscillator. Therefore, for low noise in the power switching process, even if the driving capability of the driving circuit is large and the driving time is long, the common phenomenon cannot be caused, namely, the power tubes are driven twice continuously without time intervals or even overlapped, so that the oscillator with a simpler structure can be ensured to be provided while the overall performance of the oscillator is improved, and the cost is reduced.
Drawings
FIG. 1 is a circuit schematic of a prior art self-excited push-pull converter;
FIG. 2 is a circuit diagram showing an application of a push-pull controller SN6501 by TI corporation;
FIG. 3 shows the drain waveform of the MOS transistor of the push-pull transformer SN 6501;
FIG. 4 is a schematic diagram of an oscillator designed to generate complementary signals using a conventional scheme;
FIG. 5 is a signal timing waveform for a normal case of an oscillator designed to generate complementary signals using a conventional scheme;
FIG. 6 is a signal timing waveform for an abnormal condition for an oscillator designed to generate complementary signals using a conventional scheme;
FIG. 7 is a schematic diagram of an oscillator of the present invention in embodiment 1;
FIG. 8 is a diagram of a falling edge single-side delay circuit of an oscillator according to the present invention in embodiment 1;
FIG. 9 shows the input-output characteristics of the falling edge single-side delay circuit of the oscillator of the present invention in embodiment 1;
fig. 10 is a schematic diagram of a driving voltage detection module in embodiment 1 of the oscillator of the present invention;
fig. 11 is a signal timing waveform of the oscillator of the present invention in embodiment 1;
FIG. 12 is a schematic diagram of an oscillator of the present invention in embodiment 2;
FIG. 13 is a schematic view of a driving voltage detecting module in embodiment 2 of the oscillator of the present invention;
FIG. 14 is a schematic diagram of an oscillator of the present invention in embodiment 3;
FIG. 15 is a schematic diagram of the driving circuit and additional driving units of the present invention;
FIG. 16 is a flow chart illustrating a method of the present invention for generating complementary drive signals for the inverter.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims.
The oscillator provided by the invention generates a time sequence pulse width as a time sequence for driving the power tube, the driving circuit turns on the power tube Q1 and the power tube Q2 after the time sequence pulse width is sent, the driving circuit 203 starts to turn off the power tube when the time sequence pulse width is finished, the power tube cannot be immediately turned off due to the limited driving current provided by the driving circuit 203, at the moment, the driving voltage detection module 204 judges whether the power tube is turned off, the timing is started when the power tube is determined to be turned off, the oscillator generates the time sequence pulse width again after a period of dead time is delayed, the next power driving is carried out, and the steps are repeated continuously to form oscillation.
Example 1:
as shown in fig. 7, there is provided an oscillator for generating complementary drive signals for a converter, comprising: the circuit comprises a timing pulse width generation circuit module 201, a frequency divider module 202, a driving circuit 203, a driving voltage detection module 204 and a falling edge single-side delay circuit 205.
The timing pulse width generation circuit module 201 includes: oscillator capacitor COSCCharging reference current source Iref, comparator CMP and comparison voltage Vref, switch NM, NOT gate 2. Oscillator capacitor COSCWhen the upper voltage is less than the comparison voltage Vref, the output CLK of the comparator CMP is high, the switch NM is turned off, and the oscillator capacitor COSCThe capacitor is charged by the current Iref, and when the capacitor is charged to the comparison voltage Vref, the comparator CMP is turned over to turn on the switch NM, so that the charge of the capacitor is discharged to be used as a starting point for next charging.
The divider module 202 includes: the falling edge action D flip-flop DFF, the NOT gate NOT1, the AND gate AND1, AND the AND gate AND2 are configured to separate the CLK signal input by the timing pulse width generation circuit module 201 into two complementary signals S AND
Figure BDA0001837276790000081
Two driving circuits 203 are provided, and two paths of complementary signals S and
Figure BDA0001837276790000082
under the action of the driving circuit, the power tube Q1 and the power tube Q2 are respectively driven according to complementary time sequences, certain driving current is provided for the power tube Q1 and the power tube Q2 according to time sequence pulse width, and the control end voltage of the power tube Q1 and the control end voltage of the power tube Q2 are raised or pulled down so as to be switched on.
The falling edge single-side delay circuit 205 is used for generating a time interval of two complementary driving signals, namely dead time. As shown in fig. 8 and 9, when Ldi is input to 0, Ldo is 0; when Ldi is input to 1, Ldo is 1, but Ldi changes from high to low with a delay, and t in fig. 9 is lowHL1～tHL2The delay time; ldi changes from low level toHigh with no delay, t in FIG. 9LHThe time instant changes from low to high without delay.
The two driving voltage detection modules 204 respectively detect the on/off states of the power transistor Q1 and the power transistor Q2. The input ports of the two driving voltage detection modules 204 are respectively connected to the gates of the power transistor Q1 and the power transistor Q2, the output ports are respectively connected to two input ends of the NAND gate NAND, the output end of the NAND gate NAND is connected to the input end of the falling edge single-sided delay circuit 205, and the output of the falling edge single-sided delay circuit 205 is used as the input of the timing pulse width generation circuit module 201. When the two power transistors have high gate voltages and are turned on, a logic high level is output, and conversely, a logic low level is output, so that the two driving voltage detection modules 204 have a logic negation relationship on the input and output voltages.
As shown in fig. 10, the driving voltage detection module 204 includes: common source amplifier and Schmitt trigger SMT; NMOS tube MtestAnd pull-up resistor RvddForm a common source amplifier, NMOS transistor MtestAs the input port V of the driving voltage detection module 204GT(ii) a The Schmitt trigger SMT shapes the output voltage of the common source amplifier and outputs a more ideal logic level, and the output logic level is used as the output V of the driving voltage detection module 204FB. The schmitt trigger SMT is characterized in that the output is low when a low level is input, and the output is high when a high level is input.
When the grid voltage of the two power tubes is in the NMOS tube MtestIs gradually reduced from a short distance above the threshold value, the NMOS tube MtestUntil V is gradually increasedFBAnd outputting a high level to indicate that the power tube is completely switched off. By means of NMOS tubes M for detectiontestThe threshold voltage is used for sensing and judging whether the power tube is started or not, and the method has high parameter matching performance and high precision; and the detection speed is high, and because the turn-off time of the power tube is between dozens of nanoseconds and hundreds of nanoseconds, the realization circuit has a simple and practical structure.
As shown in fig. 7, the two-way driving voltage detection module 204 outputs a logic VFB2And VFB1After NAND operationAs an input of the falling edge single-sided delay circuit 205, the timing pulse width generation circuit module 201, the frequency divider module 202, the driving circuit 203, the driving voltage detection module 204, and the falling edge single-sided delay circuit 205 form a whole closed-loop oscillation, and generate a complementary driving signal with dead time and less influence from driving delay.
As shown in fig. 11, after the signal S goes low, the input signal Ldi of the falling-edge one-sided delay circuit 205 does not go low immediately to generate a dead time, but goes low when the gate voltage G2 of the power transistor Q2 goes down to the off voltage to generate a dead time. Therefore, the dead time is generated when the feedback signal of the power tube is turned off, the feedback process is a closed loop, if the driving delay is changed, the starting moment of the dead time is changed, but the width of the dead time is not influenced by the driving delay, so that the common phenomenon can never occur, and the precision of the dead time can be ensured.
Example 2:
as shown in fig. 12 and 13, the difference between the embodiment 2 and the embodiment 1 is that the embodiment 2 does not have a falling edge single-side delay circuit for generating a dead time, but implements the function of generating a delay in the driving voltage detection module 204, and specifically, the driving voltage detection module 204 further includes: capacitor Cdelay(ii) a Capacitor CdelayOne end of the output terminal is connected with the input end of the Schmitt trigger SMT, and the other end of the output terminal is grounded and used for generating the required dead time. The output ports of the two driving voltage detection modules are respectively connected to two input ends of the NAND gate NAND, and the output of the NAND gate NAND is used as the input of the timing pulse width generation circuit module 201. When the grid voltage of the power tube is reduced to a certain degree, the NMOS tube MtestAlso gradually turns off, then vdd passes through pull-up resistor RvddGradually giving capacitance CdelayCharging, which flips to output a high level when reaching the upper threshold voltage of the schmitt trigger SMT, generates the required dead time.
The implementation circuit of the embodiment is simple, and the two functions of the detection function of the grid electrode of the power tube and the generation of dead time are simultaneously realized. Since the dead time from the turn-off of the power transistor Q2 to the turn-on of the power transistor Q1 and the dead time from the turn-off of the power transistor Q1 to the turn-on of the power transistor Q2 are generated by the two driving voltage detection modules 204, respectively, in practical application, the two driving voltage detection modules 204 need to be matched on an integrated circuit layout, that is, the layouts of the two driving voltage detection modules are close to each other, so that good symmetry is obtained because the circuit parameters are basically the same. Although the mode of the embodiment 1 has a little more circuits, the dead time of two different time periods is generated by the same circuit, so that the dead time is the same, and the layout special processing is not required. Example 1 and example 2 are two different ways to achieve highly symmetric complementary driving.
Example 3:
referring to fig. 14, in order to describe the application principle of the oscillator in the present embodiment, a primary winding N is shown in fig. 14PSecondary winding NS1Secondary winding NS2Transformer, secondary rectifier circuit consisting of rectifier CR1, rectifier CR2 and output capacitor Co, RLIs a load resistor.
Compared with embodiment 1, the present embodiment is different in that it further includes: the power transistor P1, the power transistor P2, and two additional driving units 206, wherein the two additional driving units 206 are used for driving the power transistor P1 and the power transistor P2, respectively.
The gate of the P-type power transistor P1 and the output terminal V of one of the additional driving units 206OThe input end Vi of the additional driving unit 206 is connected to the output end of the first NOT gate NOT3, the input end of the first NOT gate NOT3 is connected to one of the outputs of the frequency divider module 202, and the drain of the P-type power transistor P1 is connected to the drain of the power transistor Q2.
The gate of the P-type power transistor P2 and the output terminal V of the other additional driving unit 206OThe input end Vi of the additional driving unit 206 is connected with the output end of the second NOT4, the input end of the second NOT4 is connected with the other path of the output of the frequency divider module 202, and the drain of the P-type power tube P2And the pole is connected with the drain electrode of the power tube Q1.
Since the driving logic of the P-type power transistor is opposite to that of the N-type power transistor, a first NOT gate NOT3 and a second NOT gate NOT4 are required to be added, the switch of the P-type power transistor P2 is controlled by the signal S, and the switch of the P-type power transistor P1 is controlled by the signal S
Figure BDA0001837276790000121
And (5) controlling. When S is equal to 1, the power tube Q2 and the P-type power tube P2 are simultaneously turned on the primary side of the transformer, and then current flows into the primary side winding N of the transformer from the positive terminal Vdd of the input power supply through the P-type power tube P2PThen flows out from the homonymous end of the primary side winding, and flows into the negative end of the input power supply through a power tube Q2, thereby forming an excitation current loop of the primary side. On the secondary side of the transformer, current is passed through the secondary winding NS2Then flows into the cathode through the anode of the rectifier diode CR2, and is used as the output capacitor Co and the load resistor RLAnd supplying power, thereby forming a rectifying loop of the secondary side. It can be seen that under the control of S ═ 1, the energy of the input power source is transmitted to the load side from the primary and secondary paths in an isolated manner. Easily deducted from the symmetry of the topology when
Figure BDA0001837276790000122
When the transformer is started, the power tube Q1 and the P-type power tube P1 are simultaneously started, and current flows into the different-name end from the same-name end of the primary side winding of the transformer and flows out from the different-name end to form another primary side loop; current secondary winding NS1The output capacitor Co and the load end are supplied with power after passing through a rectifier diode CR1, and another rectifier loop of the secondary side is formed. The number of the S-alpha,
Figure BDA0001837276790000123
the alternating action forms the complementary control and the drive of the full-bridge converter.
The full-bridge converter has the greatest advantage that only one winding is needed on the primary side of the transformer, so that the design of the converter is simplified, and the size of the converter is reduced. But requires a pair of P-type power transistors and provides them with complementary drive at the expense of driving the transformer windings from two opposite directions to form two complementary current loops. As with the push-pull converter, it is necessary to generate highly symmetrical complementary drive signals with a certain dead time. Assuming that the driving time of the N-type power transistor and the P-type power transistor are the same or not different, if the difference is much smaller than the dead time, the closed-loop complementary signal oscillator of the present invention can be formed by detecting only the gate voltages of the power N-type power transistors, i.e., the power transistors Q1 and Q2, as in the driving of the push-pull converter, and of course, the gate voltages of the two P-type power transistors P1 and P2, or the gate voltages of the N-type power transistors Q1 and Q2 and the P-type power transistors P1 and P2 can be detected at the same time to determine their off states.
As shown in fig. 15, the same structure is used for the driving circuit 203 in embodiments 1 to 3 and the additional driving unit 206 in embodiment 3, and the driving circuit is implemented by using a set of not gates with gradually amplified driving capability and a driving resistor in CMOS integrated circuit, the driving resistor is used to reduce the switching noise of the power transistor, and it is a matter of course that current type driving is used instead of the driving resistor in practice.
As shown in fig. 7, 12, 14, 16, there is provided a method for generating complementary drive signals for a converter, comprising:
s1: the time sequence pulse width generating circuit module generates a logic signal CLK for driving the time sequence pulse width.
The timing pulse width generating circuit module generates driving timing pulse width, and the frequency divider module separates the CLK signal from the timing pulse width generating circuit module into two complementary signals S and S
Figure BDA0001837276790000131
So that the timing pulse width generation circuit module drives the power transistor Q1 and the power transistor Q2 in a crossed manner within the effective time of the pulse width.
S2: the driving voltage detection module detects the driving voltage of the currently-switched power tube, and when the driving voltage is detected to be reduced to a set value, the currently-switched power tube is judged to be switched from an on state to an off state.
The number of the driving voltage detection modules is two, and the two driving voltage detection modules respectively correspond to the detection power tube Q1 and the detection power tube Q2.
S3: and when the currently switched-on power tube is judged to be switched to the off state, generating the dead time.
S4: and when the dead time is finished, the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width again so as to drive the other power tube to enter an on state.
Specifically, in steps S2 to S4, on the premise that the power transistor Q1 is selected to be turned on within the effective time of the pulse width, when the driving voltage detection module corresponding to the power transistor Q1 detects that the driving voltage of the power transistor Q1 drops to the set value, it is determined that the power transistor Q1 is turned from the on state to the off state, and after the detection and determination that the power transistor Q1 is turned off, the dead time and the next oscillation are started to generate the pulse width signal, and then the power transistor Q2 is driven to enter the on state.
On the contrary, on the premise that the power transistor Q2 is selected to be turned on within the effective time of the pulse width, when the driving voltage detection module corresponding to the power transistor Q2 detects that the driving voltage of the power transistor Q2 drops to the set value, it is determined that the power transistor Q2 is changed from the on state to the off state, and after the detection and determination that the power transistor Q2 is turned off, the dead time and the next oscillation are started to generate the pulse width signal, and then the power transistor Q1 is driven to enter the on state.
As shown in fig. 11, the active level of the logic signal CLK is high, i.e., at a high level, as a control signal for driving the power transistor Q1 or the power transistor Q2. Then two control signals S and S are separated out
Figure BDA0001837276790000141
S is 1 and
Figure BDA0001837276790000142
the alternating current also drives the power transistor Q1 and the power transistor Q2. After the first pulse width S ═ 1 is changed to 0, the driving voltage G2 of the power transistor Q2 is decreased from the high voltage until the driving voltage detected at time T2 is smaller than the set value, a dead time is generated from this time, and a delay time is ended at time T3, and the driving pulse width signal is generated again, i.e., CLK ═ 1 again, because the last driving was performedWhen S of the dynamic power transistor Q2 is 1, the next time the driving power transistor Q1 is selected
Figure BDA0001837276790000143
And finally, continuously circulating to generate a complementary driving signal CLK and alternately driving the two paths of power tubes, so that the detection process of the driving voltage of the power tubes is included in the closed-loop oscillation process of the oscillator, and the adverse effect caused by the driving delay of the power tubes is effectively avoided.
The dead time is generated by a driving voltage detection module or a falling edge single-side delay circuit; the output of the driving voltage detection module and the output of the falling edge single-side delay circuit are used as the input of the time sequence pulse width generation circuit module. Therefore, the method for generating the complementary driving signal of the converter takes the driving process of the power tube as a part of the cyclic oscillation of the oscillator, detects and judges that the dead time is generated after the power tube is turned off and generates the pulse width signal by carrying out the next oscillation, and is closed loop, thereby effectively avoiding the phenomenon of large dead time error caused by the driving delay of the power tube.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Claims (9)

1. A method for generating complementary drive signals for a transducer, comprising:
the driving voltage detection module detects the driving voltage of the currently-switched power tube, and when the driving voltage is detected to be reduced to a set value, the currently-switched power tube is judged to be switched from an on state to an off state;
and when the dead time is finished, the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width again so as to drive another power tube to enter an on state.
2. The method for generating complementary drive signals for a transducer according to claim 1, further comprising:
the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width, and drives the two power tubes in a crossed manner within the effective time of the pulse width.
3. The method of claim 2, wherein the dead time is generated by the driving voltage detection module or by a falling edge single-sided delay circuit; and the output of the driving voltage detection module and the output of the falling edge unilateral delay circuit are used as the input of the time sequence pulse width generation circuit module.
4. An oscillator for generating complementary drive signals for an inverter, comprising: the time sequence pulse width generating circuit module and the frequency divider module are characterized by further comprising: two drive voltage detection modules for respectively detecting the on/off states of the power tube Q1 and the power tube Q2; the input ports of the two driving voltage detection modules are respectively connected with the gates of the power tube Q1 and the power tube Q2, the output ports of the two driving voltage detection modules are respectively connected with the two input ends of the NAND gate, and the output of the NAND gate is used as the input of the time sequence pulse width generation circuit module.
5. The oscillator of claim 4, wherein the driving voltage detection module comprises: a common source amplifier and a Schmitt trigger; NMOS tube MtestAnd abovePulling resistance RvddForming the common source amplifier, the NMOS transistor MtestThe gate of the driving voltage detection module is used as an input port of the driving voltage detection module; and the Schmitt trigger shapes the output voltage of the common source amplifier and outputs a logic level, and the output logic level is used as the output of the driving voltage detection module.
6. The oscillator for generating complementary drive signals for a converter of claim 5, further comprising: and the output end of the NAND gate is connected with the input end of the falling edge single-sided delay circuit, and the output of the falling edge single-sided delay circuit is used as the input of the time sequence pulse width generation circuit module.
7. The oscillator for generating complementary drive signals for a converter of claim 5, wherein the drive voltage detection module further comprises: capacitor Cdelay(ii) a The capacitor CdelayOne end of the Schmitt trigger is connected with the input end of the Schmitt trigger, and the other end of the Schmitt trigger is grounded.
8. The oscillator for generating complementary drive signals for a converter of claim 6, further comprising: a P-type power tube P1 and a P-type power tube P2; the grid electrode of the P-type power tube P1 is connected with the output end of a first NOT gate, the input end of the first NOT gate is connected with one path of the output of the frequency divider module, and the drain electrode of the P-type power tube P1 is connected with the drain electrode of the power tube Q2; the grid electrode of the P-type power tube P2 is connected with the output end of a second NOT gate, the input end of the second NOT gate is connected with the other output path of the frequency divider module, and the drain electrode of the P-type power tube P2 is connected with the drain electrode of the power tube Q1.
9. The oscillator for generating complementary drive signals for a converter of claim 8, further comprising: two additional drive units; the output end of one additional driving unit is connected with the grid electrode of the P-type power tube P1, and the input end of the additional driving unit is connected with the output end of the first NOT gate; the output end of the other additional driving unit is connected with the grid electrode of the P-type power tube P2, and the input end of the other additional driving unit is connected with the output end of the second NOT gate.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06237158A (en) * 1993-02-09 1994-08-23 Sony Corp Cmos drive circuit
CN101388664A (en) * 2007-09-13 2009-03-18 株式会社理光 Output circuit
US20150349632A1 (en) * 2014-06-03 2015-12-03 Infineon Technologies Austria Ag Controlling a pair of switches
CN107272478A (en) * 2016-03-31 2017-10-20 瑞萨电子株式会社 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06237158A (en) * 1993-02-09 1994-08-23 Sony Corp Cmos drive circuit
CN101388664A (en) * 2007-09-13 2009-03-18 株式会社理光 Output circuit
US20150349632A1 (en) * 2014-06-03 2015-12-03 Infineon Technologies Austria Ag Controlling a pair of switches
CN107272478A (en) * 2016-03-31 2017-10-20 瑞萨电子株式会社 Semiconductor device

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